High-density Trench Capacitors Research Articles

A Proposal of Analog Correlated Multiple Sampling with High Density Capacitors for Low Noise CMOS Image Sensors

In this paper we propose a low power consumption high speed analog correlated multiple sampling (CMS) technique with high density switched capacitors for low noise CMOS image sensors. A CIS with 256 analog memories per pixel using high density trench capacitors was employed in order to verify the noise reduction effect dependent on operation timings. The noise characteristics were measured at sampling numbers of M=1~64 with various CMS sampling period of 10ns to 1µs and time interval between reset and signal samplings, thanks to the high flexibility owing to the proposed analog CMS technique. The measurement results agree well with the theoretical calculation results, showing that conducting CMS with highly correlated signals is effective in noise reduction.

Wafer level high-density trench capacitors by using a two-step trench-filling process

This paper reports on the design, fabrication and electrical characterization of high-density SIS trench capacitors by using a two-step deposition process for fast-filling the deep trenches. LPCVD silicon nitride is employed as the dielectric material to provide high efficiency deposition in the high aspect ratio trenches. The capacitance density in trench capacitors with 25 nm thick Si3N4 is characterized as high as 57.8 nF/mm2, while the breakdown voltage in trench capacitors with 35 nm thick Si3N4 is recorded to be as high as 14.5 V. Furthermore, the capacitances are measured over an applied voltage range from ź5 to 5 V, showing a small voltage-dependence of 1.2 and 0.6 % Vź1 for the 25 and 35 nm thick Si3N4 trench capacitor, respectively. The leakage currents are measured and the current transport mechanisms are analyzed. The ESR and ESL of the capacitors with 25 and 35 nm thick Si3N4 are very small, as low as 35---65 mΩ and 0.2---0.28 pH for 0.04 mm2 electrode surface.

Integrated Passive Devices and TSV, a disruptive technology for miniaturization

The 3D Silicon technology of IPDiA is a disruptive technology for miniaturization adopted by the best players in the Medical and Industrial segments for its outstanding performance and reliability demonstrated in harsh environments. The high density capacitors with multiple metal-insulator-metal (MIM) layer stacks in 3D structures reaching 250nF/mm2 already in production for several years is at the forefront of the research program where CEA-Leti and IPDiA are jointly providing innovative platforms for customers who want to combine these capacitors with Through Silicon Vias in order to demonstrate new technological concepts. The via last approach selected by IPDIA allows large possibility of integration combining TSV with active or passive devices such as High-density trench capacitors, MIM capacitors, Resistors, High-Q inductors or Zener diodes. In this paper, the interaction between TSV and IPD will be studied. Emphasis will be placed on the robustness of the 3D trench capacitor technology. Examples of applications using chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) will be illustrated.

Ultra High Density Capacitors merged with Through Silicon Vias to enhance performances.

IPDIA presents itself as the 3D Silicon leader providing innovative platforms for customers who want to demonstrate technological concepts based on Through Silicon Vias. The market segments Medical, Lighting, and Industrial addressed by the Ipdia Technology are adopting 2.5-D and 3-D technologies to increase the performance and density of their devices through the use of silicon interposers and through-silicon vias (TSVs). The via last approach developed by IPDIA allows large possibility of integration combining TSV with active or passive devices such as High-density trench capacitors, MIM capacitors, Resistors, High-Q inductors or Zener diodes . The purpose of this paper is to focus on through-silicon via (TSV) combined with IPD , providing an interposer which could have two surfaces with devices. Emphasis is placed on 3D trench capacitor technology with an update of the roadmap .Examples of applications using chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) are briefly presented. Some important results and recommendations are summarized: the process steps for passive devices interposer /TSV/redistribution layer (RDL)/microbumps /, the design rules .A comparison between TSV on active chips and passive interposer with TSV will be detailed.

Characterization and Modeling of Atomic Layer Deposited High-Density Trench Capacitors in Silicon

A detailed electrical analysis of multiple layer trench capacitors fabricated in silicon with atomic-layer-deposited Al2O3 and TiN is presented. It is shown that in situ ozone annealing of the Al2O3 layers prior to the TiN electrode deposition significantly improves the electric properties of the devices such as the dielectric constant, leakage current, and the breakdown voltage of the devices. The self-inductance and self-resistance of the capacitors as derived from S-parameter measurements up to 10 GHz are very small, as low as 4 pH and 6 mΩ for 19.1 mm2 electrode surface. These data are shown to be consistent with a theoretical model.

Ultrahigh-density trench capacitors in silicon and their application to integrated DC-DC conversion

This paper addresses silicon-based integration of passive components applied to 3D integration with dies of other technologies within one package. Particularly, the development of high-density trench capacitors has enabled the realization of small-formfactor DC-DC converters. As illustration, an integrated inductive DC-DC converter based on flip-chipping a 65-nm CMOS active die on a PICS™ (Passive-Integration Connecting Substrate) passive die is described. The PICS die includes high-density (80 nF/mm2) integrated MOS trench capacitors. A converter peak efficiency of 87.5% is achieved at Vin=1.2 V, Vout=0.95 V, Iout=100 mA and 100-MHz switching frequency. The concept enables further integration with sensors, actuators and MEMS.

Nearly bird's beak-free local oxidation technology for controlled dielectric formation in deep silicon trenches

Silicon deep trench isolation technology using local oxidation is reported. Scaled, high-density trench capacitors were fabricated with varying trench aspect ratios. Nearly bird's beak-free local oxidation resulted in a controlled growth of silicon dioxide on the trench bottom surfaces and significantly improved the trench gate MOS isolation characteristics. Detailed MOS capacitance measurements were performed and wafer yield in excess of 90% was demonstrated across 4 inch diameter silicon wafers.