High Density Interconnect Applications Research Articles

Optimization of novel two-step curing method for die stack epoxy bonding to reduce voids in Ball Grid Array packages for high-density interconnect applications

This research explores the optimization of epoxy curing parameters to minimize void formation in 3-IC-Chip-MAPBGA packages, a subset of BGA packages, crucial components in high-density interconnect applications. The study utilizes a systematic approach involving design of experiments (DOE) assisted by statistical JMP tool to manipulate curing profiles, aiming to achieve void reduction while preserving adhesion properties. Various analytical techniques, including X-ray imaging, differential scanning calorimetry (DSC), thermogravimetric analysis (TGA), die shear strength tests, and C-Sam analysis for delamination, are employed to analyze void formation, material characteristics, mechanical properties, and structural integrity. The findings demonstrate that the sample with a 2nd step curing profile, identified as sample#3, which includes a ramp time of 15 min, a 1st step curing temperature of 90 °C with a soak time of 20 min, and a 2nd step ramp time of 20 min, exhibits the most favourable outcome in void reduction. This sample shows a notably lower void presence of 3.66 % and the highest die shear strength of 126 MPa. In contrast, the control sample, serving as a reference, displays a void percentage of 7.28 %, nearly twice as high as that of sample#3, and much lower die shear strength of 80 MPa at 25 °C. Adopting the curing profile of sample#3 also leads to a substantial 18.75 % reduction in cycle time compared to the control sample. The study highlights the importance of balancing curing parameters to mitigate void formation and maintain optimal mechanical properties, offering valuable insights for improving the reliability of high-density interconnect applications.

Three-Dimensional Interconnection With Magnetically Coupled Transition for W-Band Integration Applications

In this article, a new class of 3-D interconnection with the magnetically coupled transition is proposed at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> -band. In contrast to planar approaches, it can connect different components or modules in a complex package with wideband and low-loss performance, even if in separate circuit boards. To overcome the radiation loss, the micromachined rectangular microcoaxial line ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}\mu $ </tex-math></inline-formula> CL) is chosen to be the 3-D signal line, owing to its low-weight robust structure and low-crosstalk transmission. The substrate integrated waveguide (SIW) is chosen to act as the common signal line around the components and modules. The soldering process will introduce the unpredictable parasitic reactance, which can deteriorate the transmission performance. To construct a nonsoldering field transformation structure from the TEM mode to the TE10 mode, the U-shaped magnetic slot is etched on the SIW through the direction orthogonal to the current field vector, and the tail of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}\mu $ </tex-math></inline-formula> CL is directly open. Meanwhile, the transmission characteristics is studied by analyzing the physics-based equivalent-circuit model of this interconnection. The extraction methods of the key parameters, such as turn ratios in the equivalent circuit, are studied for simplifying the synthesis approach. A back-to-back interconnection prototype is designed by the synthesis guideline. The prototypes are fabricated and measured to validate the correctness of this design. The measured results show that the proposed transition achieves a bandwidth from 85 to 100 GHz with the return loss better than 13 dB and the insertion loss around 1.5 dB, which make it promising for high-density interconnection applications at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> -band.

Reliable Nickel-Free Surface Finish Solution for High-Frequency, HDI PCB Applications

Abstract The evolution of Internet-enabled mobile devices has driven innovation in the manufacturing and design of technology capable of high-frequency electronic signal transfer. Among the primary factors affecting the integrity of high-frequency signals is the surface finish applied on printed circuit board copper pads—a need commonly met through the electroless nickel immersion gold process (ENIG). However, there are well-documented limitations of ENIG due to the presence of nickel, the properties of which result in an overall reduced performance in the high-frequency data transfer rate for ENIG-applied electronics, compared with bare copper. An innovation over traditional ENIG is a nickel-less approach involving a special nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer. In this study, assemblies involving this nickel-less novel surface finish have been subjected to extended thermal exposure, then intermetallics analyses, contact resistance comparison after every reflow cycle (up to six reflow cycles) to assess the prevention of copper atom diffusion into the gold layer, solder ball pull and shear tests to evaluate the aging and long-term reliability of solder joints, and insertion loss testing to gauge whether this surface finish can be used for high-frequency, high-density interconnect applications.

A 1.8 pJ/bit &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$16 \times 16\;\text{Gb/s}$&lt;/tex-math&gt; &lt;/inline-formula&gt; Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

A source-synchronous I/O architecture is reported that includes redundant receiver lanes to enable lane recalibration with reduced power and area overhead. Key features and considerations of the proposed architecture are described. A proof-of-concept 16 lane, 16 Gb/s per lane source-synchronous I/O test chip was designed and fabricated in a 32 nm SOI CMOS technology. Several circuit techniques employed in the design of this test chip are described. These include a phase rotator based on current-integrating phase interpolator cores with architecture and circuit improvements to performance as compared to prior art, an active-inductor-based RX CTLE, and an 8:1 TX serializer with 8-phase clocking. Measurements demonstrate the operation of the test chip over ultra-short-reach channels with up to 10 dB of loss with greater than 30% timing margin. The I/O circuitry operates from 1 V supplies and achieves a power efficiency of better than 2 pJ/bit, making the proposed architecture suitable for use in high-density interconnect applications required for high-performance computing systems.

Reliability of thermally stressed rigid–flex printed circuit boards for High Density Interconnect applications

The thermal fatigue of vias in rigid–flex printed circuit boards (PCB) is considered in the paper. Dedicated printed circuit boards have been designed with different geometrical configurations (plating thickness, drilled hole diameter and PCB thickness). The PCB is made of hundreds of vias or holes which are wired by copper path to create a daisy chain. The PCB is subject to cyclic thermal loading (−55°C, +125°C). Electrical connectivity is recorded during tests. Cross sectioning is performed finally to characterize the loss of electrical connectivity. Fracture of plated copper, due to the thermal expansion mismatch between constituents, is shown to be responsible for the failure of the PCB. In addition to environmental tests, finite element model is developed to analyze the deformation of PCBs during thermal cycling. Areas of strain concentration determined by Finite Element Analysis (FEA) are consistent with locations where cracks were observed in experiments. In addition, the numerical estimation of the plastic strain increment per cycle enables the prediction of the fatigue life. The results confirm that for rigid flex boards, the fatigue life of vias increases with higher plating thickness, larger drilled hole size and lower PCB thickness. Numerical results are shown to be in good agreement with experiments.

Printable Materials and Devices for Next Generation Packaging

This paper examines the use of different materials in the area of printing technology. A variety of printable nanomaterials for electronic packaging have been developed. This includes nano capacitors and resistors as embedded passives, nano laser materials, optical materials, etc. Materials can provide high capacitance densities, ranging from 5nF/inch2 to 25 nF/inch2, depending on composition, particle size and film thickness. The electrical properties of capacitors fabricated from BaTiO3-epoxy nanocomposites showed a stable dielectric constant and low loss over a frequency range from 1MHz to 1000MHz. The change in capacitance after 3X IR-reflow and after 1000 cycles of deep thermal cycling (DTC) between −55°C and 125°C was within 5%. A variety of printable discrete resistors with different sheet resistances, ranging from ohm to Mohm, processed on large panels (19.5 inches × 24 inches) have been fabricated. Low resistivity materials, with volume resistivity in the range of 10−4 ohm-cm to 10−6 ohm-cm depending on composition, particle size, and loading can be used as conductive joints for high frequency and high density interconnect applications. The CITC (Current Induced Thermal Cycling) life at 245C is greater than 10 cycles and life at 220C is over 25 cycles to fail, which is at least equivalent to copper PTH (plated through hole) performance. Thermosetting polymers modified with ceramics or organics can produce low k and low loss dielectrics. Altogether, this is a new direction in the development of printable materials and devices suitable for next generation packaging.

Nanomaterials for “Green” Electronics

This paper examines the use of nanomaterials in the area of “green” technology. A variety of green materials for advanced organic packaging have been developed. These include capacitors and resistors as embedded passives, resin coated Cu (RCC) as buildup layers, highly conducting nano-micro media for Z-interconnects, lead free assembly paste, ZnO based additives, magnetic materials, inductors and thermal interface materials (TIM). Nanocomposites can provide high capacitance densities, ranging from 5 nf/inch2 to 25 nF/inch2, depending on composition, particle size and film thickness. The electrical properties of capacitors fabricated from BaTiO3-epoxy nanocomposites showed a stable capacitance over a temperature range from 20°C to 120 °C. A variety of printable discrete resistors with different sheet resistances, ranging from 1 ohm to 120 Mohm, processed utilizing a large panel format (19.5 × 24 inches) have been fabricated. Low resistivity nanocomposites, with volume resistivity in the range of 10−4 ohm-cm to 10−6 ohm-cm depending on composition, particle size, and loading can be used as conductive joints for high frequency and high density interconnect applications. A variety of metals including Cu, Ag, LMP (low melting point) and LMP-coated Cu fillers have been used to make halogen free, lead free electrically conducting adhesive technology as an alternative to solders. Halogen free resin modified with ceramics/organic particles can produce low Dk resin coated Cu (RCC) with Dk value in the range between 4.2 and 2.5. Similarly, low loss RCC materials can be produced by combining HF resin with low loss fillers. The mechanical strength of the various RCC was characterized by a 90 degree peel test and measurement of tensile strength. RCC exhibited peel strength with Gould's JTC-treated Cu as high as 6 lbs/inch for halogen free RCC. These halogen free RCC materials exhibit coefficients of thermal expansion (CTE), ranging from 27 ppm/°C to 32ppm/°C. The paper also describes a nanoparticle dispersion approach to prepare nanogels and nanofluids as thermal interface materials. Altogether, this is a new direction in the development of Green Packages and more specifically in the development of coreless substrates for semiconductor packaging.

Reliability testing for microvias in printed wire boards

PurposeThe purpose of this paper is to identify and expand upon the understanding of the reliability of high density interconnect (HDI) technologies containing multi‐level microvia interconnections with 2, 3 or 4 stacked and staggered configured structures.Design/methodology/approachMicrovia testing was performed with interconnect stress testing (IST) using a modified methodology documented in the IPC test methods manual TM650, Method 2.6.26, titled DC current induced thermal cycle test. The IST coupon designs utilize mathematical modeling, in combination with prior experience in the fields of printed wiring board (PWB) processing, chemistry, materials and statistics, to improve the sensitivity of testing.FindingsSingle and 2 stack microvias are generally the most robust type of copper interconnection used in HDI applications, 3 stack and 4 stack require greater discipline to assure product reliability. Ranking the inherent reliability of 3 stack and 4 stack structures to other interconnects like plated through holes, blind, or buried vias, may need to be reconsidered in future reliability test programs.Research limitations/implicationsThis work was focused on the reliability of bare board and does not address failure modes associated with the additional stresses applied to the microvia structures created by the devices and their associated solder joints formed during surface mount assembly and rework operations.Originality/valueThis paper was written to improve the understanding of various aspects of design and their influence on reliability for stacked and staggered microvia structures. The design function must understand the physical construction as a critical influence on microvia reliability that should be taken into consideration in parallel with the electrical requirements.

Investigation of the curing behavior of a novel epoxy photo‐dielectric dry film (ViaLux™ 81) for high density interconnect applications

Investigation of the curing behavior of a novel epoxy photo‐dielectric dry film (ViaLux™ 81) for high density interconnect applications

Conversion between standard and low-alpha lead in solder bumping production lines

Soft-errors caused by lead in solder-bumping have been a concern for many years. The problem is of special concern for high-density interconnection applications requiring solder to be placed directly over active circuitry. In that situation, alpha particles emitted by radioactive lead cause soft-errors with no possibility of shielding circuitry. For optimal cost-effectiveness, though, not all solder bumped wafers require low-alpha lead. MCNC has developed a solder bumping facility with both a research branch at MCNC and a full-scale production facility at its spin-off, Unitive Electronics Inc. We present results here of our work in incorporating low-alpha lead as part of our solder bumping process. We describe the amount of cross-contamination measured when alternating plating baths of regular lead and low-alpha lead.

Investigation of the curing behavior of a novel epoxy photo-dielectric dry film (ViaLux? 81) for high density interconnect applications

The objective of this work was to determine the cure kinetics of ViaLux™ 81 photo-dielectric dry film and to optimize its curing schedule for the fabrication of sequentially built up high density interconnect-printed wiring boards. Photosensitive epoxy materials such as the photo-dielectric dry film studied herein have complicated curing regimes. This is attributed to the long lifetime of the curing catalyst that is generated by ultraviolet exposure. Dynamic differential scanning calorimetry (DSC) experiments revealed a two-peak curing mechanism, which could not be separated at lower heating rates. The activation energies for the two cure events, calculated using the Kissinger method, were found to be 129 and 124 kJ/mol, respectively. A cure-dependent activation energy was also determined using the isoconversional method, and a “model-free” approach was adopted to simulate the evolution of degree-of-cure under dynamic and isothermal conditions. The results suggest that cure cycles of approximately 15 min at temperatures above 165°C can result in a degree-of-cure of 90% and above. This implies that faster fabrication is possible with either rapid thermal curing equipment or continuous cure surface mount technology furnaces. © 2000 John Wiley & Sons, Inc. J Appl Polym Sci 78: 430–437, 2000

Design of an optical interconnect for photonic backplane applications

A compact alignment-tolerant interconnect has been developed for use within a prototype modulator-based free-space photonic backplane. The interconnect design encompasses several unique features. Microlens arrays are used, and several beams share each microlens by clustering the optical input-output in a small field about the optical axis of each lens. For simplifying the layout, the optical input and output of each smart-pixel array are clustered separately, thereby allowing a Fourier plane patterned-mirror array to be used in the beam-combination optics. This allows a suitable balance between high interconnection densities and reasonable optical relay distances between adjacent boards to be achieved. The primary advantages of this scheme are the simplicity of the optical design and its alignability, making it ideally suited for high-density interconnection applications.

A Large Format Modified TEA CO2 Laser Based Process for Cost‐effective Small Via Generation

Recently, a Transverse Excited Atmospheric (TEA) CO2 laser technology has been developed for the micro‐machining of vias in non‐reinforced glass laminates. This system has been designed to accommodate the large panel sizes associated with PWB processing. The salient features of this modified CO2 laser technology are summarised. A joint Lumonics/Motorola study was carried out to assess the applicability of this laser processing technology for use in higher density PWB and MCM‐L substrate processing and its compatibility with currently available classes of dielectrics used in high density interconnect applications. A 10x improvement in cycle time/throughput over the existing raster scanning laser ablation process has been demonstrated.

Laser ablation of polymers for high-density interconnect

Abstract Fabrication of micro-vias with a diameter of less than 100 μm in polymeric materials is a key processing technology for high-density interconnect applications. This paper discusses material properties that are relevant to laser ablation and describes several laser techniques (e.g. excimer, UV YAG and CW argon ions lasers) for micro-via fabrication in a thin-film multilayer structure for high-density interconnect applications.