High-density Circuits Research Articles

Analysis of Near Field Noise Voltage Caused by Pulse Current on Power Electronics Circuits

Recently, the design procedure of a power electronics circuit structure is discussed for high power density circuits or thin structure converters. Control circuits of the converter circuit may connect close to the power circuit. When the pulse current flows into the power circuit, it radiates the magnetic field and may generate near field noise voltage to the control circuit. Therefore, it is important for the power electronics circuits to evaluate the near field noise voltage by experiment. This paper shows the measurement results of the near field noise voltage and the electromagnetic force voltage of a small area loop antenna from the 15A, 100kHz buck chopper circuit. Moreover, this paper discusses that the noise voltage may affect the control circuits in the high power density circuits.

Enhancement of Stress-Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering

An enhanced stress memorization-technique that utilizes a strain proximity free technique (SPFT) and a stacked-gate structure has been demonstrated by multiple strain-gate engineering. The electron mobility of n-channel metal-oxide semiconductor field effect transistors (nMOSFETs) with SPFT exhibit a 16% increase compared to that of counterpart techniques. SPFT avoids the limitation of stressor volume for performance improvement in high-density complementary metal oxide semiconductor circuits. We also found that optimization of stacked, random poly-Si-grain gate structure in combination with SPFT can improve mobility further to 22% more than a single poly-Si gate structure without SPFT.

The stability of high refractive index polymer materials for high-density planar optical circuits

Owing to the structural flexibility, easy processing and fabrication capabilities, polymers are being increasingly attractive for a variety of optical applications. In order to increase the integration density of such optical circuits, higher index contrasts and, thus, polymers with considerably higher refractive index are essentially needed. An organometallic polymer and a conventional epoxy material are combined to form a compatible high index material. When cured at elevated temperatures, the organometallic polymer decomposes to form a highly dispersed metal oxide phase that imparts high index properties to the polymer films. These hybrid high refractive index polymer films must be stable in patterning of optical waveguide structure for photonic manufacturing. In this paper, we report the stability and optical characterization study of a modified organometallic high refractive index polymer film in manufacturing of optical waveguide devices.

Resonant-tunnelling-assisted crossing for subwavelength plasmonic slot waveguides

We theoretically investigate properties of crossing for two perpendicular subwavelength plasmonic slot waveguides. In terms of symmetry consideration and resonant-tunnelling effect, we design compact cavity-based crossing structures for nanoplasmonic waveguides. Our results show that the crosstalk is practically eliminated and the throughput reaches the unity on resonance. Simulation results are in agreement with those from coupled-mode theory. Taking the material loss into account, the symmetry properties of the modes are preserved and the crosstalk remains suppressed, while the throughput is naturally lowered. Our results may open a way to construct nanoscale crossings for high-density nanoplasmonic integration circuits.

Photonic bandgap crystal resonator enhanced, laser controlled modulations of optical interconnects for photonic integrated circuits

Ultrafast high-density photonic integrated circuit devices (PICDs) are not easily obtained using traditional index-guiding mechanisms. In this paper, photonic bandgap crystal resonator enhanced, laser-controlled modulations of optical interconnect PICDs were achieved in slab-type mix-guiding configuration - through developed CMOS-compatible processing technologies. The devices, with smallest critical dimensions of 90 nm have footprints of less than 5 x 5 microm(2). Quality-factors an order larger than previously realized was achieved. Through use of effective coupling structures; simultaneous alignment for probing and pumping laser beams, optical measurements of both instantaneous free carriers induced device modulations were obtained together with thermo-optical effects characterizations.

Towards Crossbar Nanoarray Structure via Microcontact Printing

The method for patterning arrays of multiwalled carbon nanotubes (MWCNT's) in symmetric patterns to form junctions has been demonstrated. This has been achieved by incorporating the technique of microcontact printing using poly-dimethylsiloxane (PDMS) molds. Relief structures in the order of a few micrometers were fabricated that enabled the transfer of continuous horizontal arrays of MWCNT's in aqueous suspension in a controlled manner. The MWCNT's were patterned onto silicon microelectrode substrates with metallic gold electrodes. These were fabricated using standard photolithography techniques. The silicon substrates served as a base platform with suitable measurement microelectrodes for electrically characterizing the crossbar junction arrays. Using a dual alignment and stamping process, PDMS molds were inked alternatively with p-type and n-type suspensions of MWCNT's and transferred in a grid-like manner onto the base platform. Parallel alignment of the MWCNT's was achieved due to the geometry of the mold relief structures. This step-by-step assembly resulted in the formation of crossbar MWCNT array structures. Each of these crosspoints in the individual junction can function as an addressable crossbar nanodevice. The functionality of this circuit was demonstrated through the current-voltage (I-V) characteristics. Using these high-density crossarray circuit patterns, addressable nanostructures that form the building blocks of highly integrated device arrays can be built.

A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications

In system-on-chip applications, the digital switching noise propagates through substrate and power distribution to analog circuits, degrading their performance. To monitor and analyze the digital switching noise coupling, small and compact sensors that can be embedded within high-density circuits are essential. This paper presents PMOS-based differential substrate and power-supply sensors and an on-chip waveform sampler, which focus on wide bandwidth, reduced parasitic interactions, and small compact size. The bandwidth of the proposed sensors, which is implemented with an IBM 0.13- CMOS technology, is useful from DC to 1.6 GHz. Linearity is better than 1.5% for substrate and 6% for power-supply sensors. Power-supply rejection of 64 dB has been achieved in the substrate probing. The substrate noise coupling into the power-supply probing was below detectable limits. Experimentally reconstructed waveforms with 20-ps time resolution allowed the measurement of amplitude, rise time, and overshoot of transition edges.

LTCC-based Fluidic Components for Chemical Applications

The material properties of low-temperature co-fired ceramics (LTCCs) enable new application areas beyond the use as basic material for high-density circuits. Therefore, LTCCs are increasingly used for microfluidic applications. A modular LTCC-based microreaction system is presented in this article. One focal point of our work was the development of a connecting system for these ceramic fluidic modules. Importance was attached to solid mechanical design, good temperature resistance of fluidic and electrical connections, and minimized dead volume. In contrast to LTCC-based substrates with only electrical circuits, integration of fluidic components makes great demands, especially on the mechanical processing of the green tapes. Mechanical processing of LTCC was made by laser cutting or laser ablation. Single modules and a complete system are the subject of chemical characterization. LTCC-based mixer structures are characterized using the Villermaux–Dushman method. The functionality of the whole system is shown with an example reaction.

Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits

As semiconductor processing technology advances, complex, high density circuits can be integrated in a chip. However, increasing energy consumption is becoming one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at later stages may significantly lengthen the design period and increase the costs. For efficient power estimation, we analyze the key control signals of a digital circuit and develop power models for several operational modes. The trade-off between accuracy and complexity can be made by choosing the number and the complexity of the power models. When compared with those of logic simulation based estimation, experimental results show that 13 to 15 times faster power estimation with an estimation error of about 5% is possible. We have also developed new logic-level power modeling techniques in which logic gates are levelized and several levels are selected to build power model tables. This table based method shows significant improvement in estimation accuracy and a slight improvement in efficiency when compared to a well-known previous method. The average estimation error has been reduced from 13.3% to 3.8%.

RF, DC, and Reliability Performance of MIM Capacitors Embedded in Organic Substrates by Wafer-Transfer Technology (WTT) for System-on-Package Applications

In this paper, radio frequency (RF), dc, and reliability performance have been studied on metal-insulator-metal (MIM) capacitors embedded in organic substrates. The MIM structure including ~74-nm SiN dielectric was prefabricated on Si and then transferred onto organic substrates (FR-4) by wafer-transfer technology (WTT). The RF characteristics up to 30 GHz were investigated by equivalent lumped circuit modeling, showing that the parameters associated with the MIM layers including the main capacitance, parasitic inductance, and resistance were only slightly changed by the WTT process. The substrate-related parasitics were reduced as a result of the replacement of lossy Si with insulating FR-4 substrates. Excellent capacitance linearity, low voltage coefficient (~2.2 ppm/V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), and temperature coefficient (~38 ppm/degC) were obtained for capacitors on FR-4 substrates. Current-voltage and time-dependent dielectric breakdown tests verified that, after the harsh processes of WTT, the MIM structures maintained the intrinsic reliability as those originally fabricated on Si. This paper, along with earlier reports, proved that WTT presented a new dimension to realize embedded capacitors for high-density circuit board and system-on-package applications

Economic Aspects of Memory Built-in Self-Repair

With the advent of deep-submicron technology and SoC design methodology, it's possible to integrate heterogeneous cores from different sources in a single chip containing millions of gates. The yield of such a large chip is usually too low to be profitable. Therefore, yield enhancement is an important issue in SoC product development. Memory cores usually occupy a large proportion of the area of a typical SoC, and they normally have higher circuit density, so they tend to dominate SoC yield. This article presents cost and benefit models to evaluate the economic effectiveness of typical memory BISR implementations. Experimental results with a simulator based on these cost models show that memory size impacts cost-effectiveness more than production volume does.

Heterogeneous Wafer-Scale Circuit Architectures

This article has presented circuit architectures that allow for the 3D integration and on-wafer packaging through the concept of an Si interposer. The presented 3D integration schemes have allowed for the design and fabrication of a fully integrated receiver that performs at 10 GHz. High-Q passives and 3D interconnects allow for the design of low-cost, high-density circuits that also exhibit very high performance

A New Demultiplexer Based Upon Two-Dimensional Photonic Crystals for Optical Integrated High-Density Circuits

ABSTRACT: A new conception of the wavelength division multiplexing on the basis of the two-dimensional photonic crystal was developed. The photonic crystals band structures were investigated in details. The method for the synthesis of the two-channel wavelength division multiplexer on the basis of two dimensional photonic crystals was developed using this method the device was synthesized. The spectral characteristics of the device and its dynamic pulse pattern response were investigated. INTRODUCTION At present photonic crystals (PhC) that are characterized by a periodic variation in a refractive index offer a fertile field for research. The matter is that these crystals have opened up fresh opportunities for controlling wave propagation over the range from millimeter wave to IR and visible spectral region [1,2]. Photonic crystal is an area of great interest in terms of transmitting and processing some information in fully optical systems because a photonic forbidden band originate an radiation is localized in the region of periodic-structure defects. Specifically, from among the critical areas where the PhCs find their use, one can refer not only to low threshold lasers that act as a factor of optical constraint but also to the filtering system for transmitting a definite optical spectrum in optical waveguides and devices intended for wavelength-

Static NMOS circuits for crossbar architectures using silicon nano-wire technology

This study shows the design and analysis of static NMOS gates composed of silicon nano-wire surrounding gate pull-down NMOSFETs (SGFETs) and p-type pull-up resistors as the primary building blocks to form high density circuits. The device geometry and doping concentration of NMOS transistors and p-type resistors are varied until the lowest noise margin and standby power dissipation are obtained for an inverter. The optimum NMOS transistor and p-type resistor configurations are subsequently used to build various NOR-type static logic gates including a full adder to evaluate the transient performance, power consumption and layout area of each gate. A power-saving technique that replaces the p-type pull-up resistor with a p-type MESFET is also investigated for large-scale logic strings. Simulation results indicate that the worst-case rise and fall delays for a full adder are 130 ps and 90 ps at no capacitive load, and increase by 27.5 ps and 10 ps per fan-out, respectively. The worst-case power dissipation for the same circuit is 186.4 µW. The full adder circuit occupies approximately a 25 μm2 area if laid out conventionally and 36 µm2 if laid out on a crossbar platform. Compared to same feature size conventional CMOS technologies, silicon nano-wire technology offers simplicity in interconnect routing and reduction in the layout area for similar circuit performance.

PATTERNED COPPER PLATING LAYER THICKNESS MADE UNIFORM BY PLACEMENT OF AUXILIARY GRID ELECTRODE ABOUT BALL GRID ARRAYS

The authors established a method to ensure uniform patterned copper plating layer thickness in semiconductor packages with high-density electrical circuits or ball grid arrays (BGA). A single BGA pattern unit was divided into small areas and for each, active area density was defined according to the area covered by the copper layer. Current distribution was determined for such an area by numerically solving Laplace and Butler-Voltmer equations, with consideration directed to active area density and plating solution conductivity. With the auxiliary grid electrode placed at a certain distance from the BGA so as to surround the latter by the former electrode, the current was found to be quite effectively prevented from becoming concentrated on sparsely dispersed circuit patterns generally situated near the edge of a unit BGA. Current distribution was noted to vary according to position and cross section size. Error could be made as little as 3.37% when this position was optimal.

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations

Development of 6.00Å graded metamorphic buffer layers and high performance In0.86Al0.14As∕In0.86Ga0.14As heterojunction bipolar transistor devices

In x Al 1 − x As ∕ In x Ga 1 − x As heterojunction bipolar transistors (HBTs) with lattice parameters ranging from 6.00to6.058Å employing the use of narrow band gap InxGa1−xAs base epitaxial layers toward InAs (0.86&amp;lt;Xln&amp;lt;1) allows for the development of high speed digital and mixed signal circuits to perform at half the power required for conventional group III-V-based HBT device technologies. However, one of the key challenges inhibiting the development of low power narrow band gap HBT device circuits is the absence of semi-insulating (SI) substrates with lattice parameters towards 6.058Å. Therefore, a metamorphic InxAl1−xAs (0.52&amp;lt;Xln&amp;lt;0.86) graded buffer layer (GBL) grown on InP by molecular beam epitaxy was investigated as a means to enable a SI template with a lattice parameter of 6.00Å. The metamorphic InxAl1−xAs GBL thickness is desired to be less than a micron in order for this approach to be compatible with the aggressive design rules of high-density transistor circuits. In this study, In0.86Al0.14As∕In0.86Ga0.14As double heterojunction bipolar transistor devices were grown on 0.90, 0.45, and 0.23μm thick InxAl1−xAs GBLs to assess the role of buffer layer thickness on both defect formation and device performance. The material characterization results for the 0.90 and 0.45μm thick buffer layers exhibited a crosshatch pattern with a surface rms roughness of 4nm and threading dislocation densities of ∼106cm−2. Excellent dc and rf characteristics from metamorphic HBT devices with submicron emitter widths were observed with low turn-on voltage of 0.45V, high current gain, low reverse junction leakage(&amp;lt;1μA), and rf peak performance in the vicinity of 150GHz. Finally, preliminary circuits (dividers and delay chains) have been designed, fabricated, and demonstrated with the 6.00Å HBT technology.

Modeling neutron ionization effects on high-density CMOS circuit elements

The mechanisms are analyzed of the action of neutrons on high-density CMOS circuit elements. A procedure is proposed for calculating the single-event-upset and single-hard-error cross sections of CMOS memory cells exposed to neutrons.

Effect of Metal Impurities on Shading and Thermal Conductivity of Aluminum Nitride

Because aluminum nitride (AlN) has a high thermal conductivity and a high electrical resistivity, it is used for substrates and packaging for high power or high density circuits. Silicon chips need to be protected from faults caused by exposure to ultra-violet rays. AlN packaging and substrates have to be shaded for UV protection. The characteristics of AlN are influenced by a number of factors. Specifically, metallic impurities affect the shading and thermal conductivity, and are particularly easily mixed with AlN as minerals or solutions during processing. It is very important to understand how metallic impurities influence the characteristics of AlN, and either refine processing to eliminate such effects, or add metal to achieve the desired industrial characteristics. Iron (Fe), silicon (Si), magnesium (Mg), and titanium (Ti) are metals that are easily mixed, so it is important to understand their influence. The metallic impurities Fe, Si, Mg, and Ti were added to raw powder AlN and uniformly distributed at a molecular level. The powder was sintered and tested for any effects on shading or reduction in thermal conductivity. Some Ti compounds were found at the grain boundaries, but these did not reduce the AlN thermal conductivity and provided efficient shading. In contrast, Si and Mg compounds were not found at the grain boundaries but formed solid solutions in the AlN grains, so they significantly reduced the AlN thermal conductivity and provided no shading. The effect of Fe was intermediate between that of Ti and Si and was characterized by its tendency to form solid metal ion solutions in the AlN grains.

ＩＴとソフトマテリアル ソルダーレジストの構成と要求特性

A recent trend of increasing circuit density and functions of PCB diversifies demands for a solder resist mask. When the solder resist mask was introduced, its demanded property was simply to prevent solder bridge on PCB. However, a photo-imageable solder resist mask, which correspond to high circuit density PCB design was developed to overcome the limitation of the solder resist mask's resolution made by silkscreen printing method. Now days, the photo-imageable solder resist mask that is contact UV exposure and alkaline develop type is a most common solder resist mask for PCB fabrication. The photo-imageable solder resist mask is used in various PCBs e. g. motherboards on PC or TV, IC package (BGA and CSP) substrates, flexible PCBs, and etc. Since these PCBs are made for specialized purposes and functions, demands for solder resist mask for these PCBs become more specific in features and performances.In this paper, basic composition of the photo-imageable solder resist mask and its curing system, features and performance to cope with environmental issues that are halogen free and lead free, UV exposure types, and difference of liquid type and dry film type solder masks are discussed.