Economic Aspects of Memory Built-in Self-Repair

Abstract

With the advent of deep-submicron technology and SoC design methodology, it's possible to integrate heterogeneous cores from different sources in a single chip containing millions of gates. The yield of such a large chip is usually too low to be profitable. Therefore, yield enhancement is an important issue in SoC product development. Memory cores usually occupy a large proportion of the area of a typical SoC, and they normally have higher circuit density, so they tend to dominate SoC yield. This article presents cost and benefit models to evaluate the economic effectiveness of typical memory BISR implementations. Experimental results with a simulator based on these cost models show that memory size impacts cost-effectiveness more than production volume does.