Hierarchical Memory System Research Articles

Analysis of branch handling strategies under hierarchical memory system

Branch instructions form a significant fraction of executed instructions in a computer program, and handling them is thus a crucial design issue for any architecture. In a hierarchical memory system, branch handling not only causes the pipeline drain but also results in more instructions being executed, which can result in a higher miss ratio. These phenomena are relevant to the resolution of the branch condition stage, the generation of branch target stage, and how the branch is handled. A new branch handling model to quantify the overall effects is developed. Eight kinds of branch handling strategies currently used are examined by this model. Tradeoffs among them can be made on a statistical and theoretical basis. Also, the results of prediction brought forth by this model among some architectures are compared with those of evaluation to justify this model.

Evaluation of a retrieval system using content addressable memory

AbstractBecause of the improvements in LSI technology, larger‐scale CAM's can now be developed at low cost. However, as the amount of data to be handled becomes larger, storing the totality of the data to be searched in CAM's ceases to be cost‐effective. A practical solution is to store the data in other storage devices and partition the full data set into blocks for transfer into the CAM. In such a hierarchical memory system there will occur data transfer bottlenecks and overhead for operations other than searching; furthermore, it is not known what search speed is achievable. In this paper, we therefore make model of such a CAM‐based memory system in order to determine the data transfer overhead, evaluate system performance, and investigate ways of reducing search time. It is concluded that: (1) data transfer time can be reduced more effectively by using a large‐capacity bus or by rapid data access than by using a large, high‐speed CAM; (2) there exists an optimum CAM size and configuration for rapid search; (3) the speed of the control mechanism that transfers the data blocks into the CAM is not critical to system performance.

Dense linear systems FORTRAN solvers on the IBM 3090 vector multiprocessor

The IBM 3090 is a vector multiprocessor with a hierarchical memory system. We show with two examples (the LU and Householder factorizations) that the complex memory system and the vector hardware can be used efficiently by recasting the basic algorithms in terms of high-level matrix-matrix modules.

Designing linear algebra algorithms on the IBM 3090 vector multiprocessor with a hierarchical memory system

The IBM 3090 is a vector multiprocessor with a hierarchical memory system. We show with two examples (the LU and Householder factorizations) that the complex memory system and the vector hardware can be used efficiently by recasting the basic algorithms in terms of high-level matrix-matrix modules.

Impact of Hierarchical Memory Systems On Linear Algebra Algorithm Design

Linear algebra algorithms based on the BLAS or ex tended BLAS do not achieve high performance on mul tivector processors with a hierarchical memory system because of a lack of data locality. For such machines, block linear algebra algorithms must be implemented in terms of matrix-matrix primitives (BLAS3). Designing ef ficient linear algebra algorithms for these architectures requires analysis of the behavior of the matrix-matrix primitives and the resulting block algorithms as a func tion of certain system parameters. The analysis must identify the limits of performance improvement possible via blocking and any contradictory trends that require trade-off consideration. We propose a methodology that facilitates such an analysis and use it to analyze the per formance of the BLAS3 primitives used in block methods. A similar analysis of the block size-perfor mance relationship is also performed at the algorithm level for block versions of the LU decomposition and the Gram-Schmidt orthogonalization procedures.

A 32-bit CMOS microprocessor with on-chip cache and TLB

A 32-b general-purpose microprocessor has been developed using 1-/spl mu/m CMOS technology. The chip, containing 372 K transistors, operates at a 80-ns machine cycle time with a 5-V power supply. For virtual and hierarchical memory system support, a 64-entry full-associative translation lookaside buffer (TLB) and a 2-kbyte instruction cache are implemented on the chip. The internal access times for the TLB and cache are 22 and 18 ns, respectively. The microarchitecture has been designed to reduce the pipeline to three stages, simplifying the control path and obtaining high-speed performance. The data path of this chip is also enhanced with hardware, such as a barrel shifter and multiplier/divider. The chip performance has been measured to be 5.1 million instructions per second (MIPS) and 50-ns-access main memory.

A study on hybrid switch architecture using hierarchical memory system

AbstractOn the premise that flexibility in communication is a primary objective for future digital networks providing various services, it is highly desirable to integrate circuit switching (CS) and packet switching (PS) functions into a single switching node. This paper proposes a hybrid switching system where PS and CS switching functions are integrated by making use of a hierarchical memory system in which the CS and PS switching buffers and program buffers reside in the same memory area, and the high‐speed memory in the hierarchy can be accessed both by transmission lines and processors. The design concept which adopts a new architecture necessary to meet the above requirement and the evaluation of its call processing capacity using traffic simulation and theoretical analysis are described.

Intelligent Magnetic Bubble Memories and Their Applications in Data Base Management Systems

We are concerned here with the design of intelligent magnetic bubble memories which may be used to support high-level data base management functions. They may also be used to provide users with large work spaces in which elementary file processing operations may be performed without external intervention. It is our intent to explore ways of incorporating in the design of these memories the novel chip organizations and unique features of magnetic bubble memories. In particular, we evaluate the performance of various memory organizations and storage organizations for different magnetic bubble chips. Retrieval times per word and per page are the parameters used to evaluate the different memory organizations. Performance of hierarchical bubble memory systems are discussed. The data rearrangement operations capable of being carried out in bubble memories are incorporated in the design of elementary file processing operations and basic relational algebraic operations. An architecture of intelligent magnetic bubble memory designed to support the relational data model and to enhance a relational algebraic interface is described.

On modeling program behavior

This is a paper about the history of the set model for program behavior. It traces briefly the origins and bases of the idea and some of the results subsequently obtained. The physical context is a hierarchical memory system consisting of a severely limited quantity of main (directly-addressable) storage and an essentially unlimited quantity of secondary (backup) storage. In this context, the intuitive notion of working as the set of words which are (or should be) loaded in main memory at any given time in order that a program may operate efficiently is as old as programming itself. The sharply increased interest in program models since the mid-1960s is a direct consequence of the widening use of virtual memory and multiprogramming techniques, which have shifted the responsibility of memory management from programmers to machines. I am assuming here that the purpose of memory management is ensuring that an active program's information is present in main memory, and the purpose of a program model is providing a basis for determining a program's information at a given time and predicting what it will be at a future time.