HF Wet Etching Research Articles

Evaluation of Air Gap structures produced by wet etch of sacrificial dielectrics: Critical processes and reliability of Air Gap formation

Two Air Gap technologies were investigated concerning critical process steps. Both approaches use SiO 2 for sacrificial material and buffered HF wet etch chemistry. These critical processes include pre-wet-etch-concerns and wet-etch-concerns. The results of a special spacer etch-back process are shown. A buffer layer of SiO 2 was introduced to relax the requirements on the dry back-etch process. The oxidation of SiC and SiCN films during dry etching and resist stripping is an issue of both technologies, because this may lead to an undercut of the interconnect lines during the buffered HF treatment. Nevertheless, this can be successfully avoided by the application of appropriate oxygen (O 2) free process media. Furthermore, the shifting of mechanical behaviour of such structures as a result of wet-etch treatment is investigated. The intrinsic stress of cantilever SiC films has the capability to cause pull-off forces to interfaces which may result in film delamination.

Realization of Silicon Nitride Template for Nanoimprint: A First Result

A first result of realization of silicon nitride templates on 100mm silicon wafer as nanoinprint mold using simple wet etching method is reported in this paper. The process is based on traditional photolithograph and following buffer HF wet etching, which started from a p-type wafer with 400nm thermal silicon oxide, 200nm PECVD silicon nitride and 400nm PECVD silicon oxide sandwich layer. After patterning with lithography, the patterned resist is used as mask for the isotropic underlayer wet etching of silicon dioxide with buffer HF solution. Using the obtained nanosacle silicon dioxide lines as RIE dry etching mask, silicon nitride template of 100nm width with steep sidewalls is successfully realized.

Laser-induced Modification in Glasses by CW Laser Backside Irradiation (CW-LBI)

We describe filamentary crack-free modification in silica glass and Pyrex glass by CW Laser Backside Irradiation (CW-LBI). In this paper, the properties of laser-induced modification in glasses by CW-LBI were examined. The cross-section of the modification was a concentric ring structure, which consisted of the core region and the clad region. In HF wet etching, the etching rates of the core region, the clad region and the non-irradiated area were 1.6, 3.3 and 1.8μm/h, respectively. Then, a Vickers hardness test showed that the hardness of the core region increased and that of the clad region decreased. Raman spectra of the core region showed that the intensity of the peaks around 490 and 605cm-1 were increased and indicated the increase of 4- and 3-fold ring structures in the silica network. On the other hand, 4- and 3-fold ring structures in the clad region decreased. Therefore, the structural changes of silica network had an effect on the change of properties.

Nanopattern transfer to SiO[sub 2] by ion track lithography and highly selective HF vapor etching

The authors present a method for high aspect ratio nanopatterning of high density (1010pores∕cm2) self-assembled porous alumina membrane pattern into thermally grown SiO2 on silicon. The pattern transfer is accomplished by irradiating through 2μm thick porous alumina membrane with swift heavy ions (4MeV Cl2+). Ions passing through the nanopores in the mask at a fairly high fluence (typically 1014ions∕cm2) are impinging on the substrate and creating a continuous volume of overlapping ion tracks of damage. The damage is sufficient to be selectively etched by HF vapor from an aqueous HF solution. From an alumina mask with pores of 70nm diameter, a pattern of pores of 77nm in diameter and the same distance of 100nm between the centers of the pores was transferred. The deepest observed etched pores were 355nm, giving an aspect ratio of 5, which is up to 40 times larger compare to earlier work where HF wet etching was used. This ion track lithography technique shows a potential to produce nanostructures with ev...

Focused ion beam microfabrication in Foturan™ photosensitive glass

The fabrication of nano-dimensional features in the photoetchable glass Foturan™ using focused ion beam technology has been characterized. To date, most microfabrication in this material has used UV lithography and UV lasers, with a minimum feature size of around 10 µm determined by the grain structure, though there has been some recent work using high energy proton irradiation. Focused ion beam technology offers two potential advantages: features are etched directly without post bake or HF wet etch and features can be generated with lateral and depth resolution on the nanoscale. Initial test features were milled to a depth of 1.46 µm, without distortion due to charging, at a milling rate of 0.23 µm3 nC−1, in agreement with our simulations.

AlGaN/GaN biosensor—effect of device processing steps on the surface properties and biocompatibility

The impact of typical device processing steps (KOH, HCl, HF wet chemical etching, SF 6 and Cl plasma etching) on the surface properties (roughness, chemical composition, contact angle to water) of group III-nitride based chemical sensors is investigated with emphasis on the electrical performance of the sensor and the biocompatibility. An AlGaN/GaN high electron mobility transistor serves as basic sensing device. For our studies, the widely distributed mammalian cell cultures HEK 293FT and CHO-K1 are used as biological model systems. The processing of the devices has only little influence on the cell growth onto the sensor, which is in all cases superior to that on silicon surfaces. Fluorine dry etching leads to oxidation and smoothing of the surface, thus, improving the electrical properties of the AlGaN/GaN sensor. In contrast, autoclave treatment enhances the carbon contamination with negative impact on the sensor properties and increased the contact angle to water, which can be used as indicator for the state of the sensor surface. For all other treatments the contact angle recaptures a stable value of about 50 ± 5° after exposure to air or water droplets for some hours due to contamination by hydrocarbons.

Comparative study on chemical stability of dielectric oxide films under HF wet and vapor etching for radiofrequency microelectromechanical system application

HF wet and vapor etching of dielectric oxide films, which were prepared by thermal atomic layer deposition (ALD) and plasma-enhanced ALD (PEALD), are examined for radiofrequency microelectromechanical system (RF MEMS) application. The chemical stability of oxide films was increased in the order of ALD–Al 2O 3 < PEALD–ZrO 2 < PEALD–TiO 2 ≈ ALD–Ta 2O 5 under wet etching in 6:1 buffered HF aqueous solution, but in a different order of Ta 2O 5 < ZrO 2 < TiO 2 ≈ Al 2O 3 under anhydrous HF/CH 3OH vapor etching at 4 kPa. The unstable films were uniformly and completely etched under the wet etching, while transformed to have increased thickness or non-uniformly etched with thicker residue under the vapor etching. Al 2O 3 and TiO 2 (Ta 2O 5 and TiO 2) can be used for RF MEMS capacitive switch fabricated by using HF vapor (wet) etching of sacrificial SiO 2.

The electrical and physical analysis of Pt gate/Al2O3/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

In order to examine the electrical and physical properties of Al2O3 layers with dual thickness on a chip, Pt gate/Al2O3 with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and 100:1 HF wet etching to remove the first Al2O3 layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ∼4.5 nm, equivalent oxide thicknesses (EOT): 2.8 nm) and thick (physical thickness, ∼8.2 nm, EOT: 4.3 nm) Al2O3 layers showed a good leakage current density of −5.4×10−6 A/cm2 and −2.5×10−9 A/cm2 at −1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus voltage measurements (C-V) hysteresis; and a good interface state density (∼7×1010 cm−2eV−1 near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al2O3 layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al2O3 layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors with a thin Al2O3 layer and high reliability regions with a thick Al2O3 layer.

Etching Mask Effect of the Nanoscratched Borosilicate Surface and Its Application to Maskless Pattern Fabrication

The purpose of this study is to suggest a maskless pattern fabrication technique using the combination of machining by Nanoindenter® XP and HF wet etching. Sample line patterns were machined on a borosilicate surface by constant load scratch (CLS) of the nanoindenter with a Berkovich diamond tip, and they were etched in HF solution to investigate chemical characteristics of the machined borosilicate surface. After the etching process, the convex structure was made. On the basis of this fact, some line patterns with convex structures were fabricated.

Maskless pattern fabrication on Pyrex 7740 glass surface by using nano-scratch with HF wet etching

Abstract Line patterns were machined on borosilicate (Pyrex 7740 glass) surface using the combination of mechanical machining by Nanoindenter® XP and HF wet etching, and a etch-mask effect of the affected layer of the nano-scratched Pyrex 7740 glass surface was investigated.

FABRICATION OF NEARFIELD OPTICAL PROBE ARRAY USING VARIOUS NANOFABRICATION PROCEDURES

The nanosize silicon oxide aperture on the cantilever array has been successfully fabricated as nearfield optical probe. The various semiconductor processes were utilized for subwavelength size aperture fabrication. The anisotropic etching of the Si substrate by alkaline solutions followed by anisotropic crystal orientation dependent oxidation, anisotropic plasma etching, isotropic oxide etching was carried out. The 3 and 4 micron size dot array were patterned on the Si(100) wafer. After fabrication of the V-groove shape by anisotropic TMAH etching, the oxide growth at 1000° C was performed to have an oxide etch-mask. The oxide layer on the Si(111) plane have been utilized as an etch mask for plasma dry etching and water-diluted HF wet etching for nanosize aperture fabrication. The Au thin layer was deposited on the fabricated oxide nanosize aperture on the cantilever array. The 160 nm metal apertures on (5×1) cantilever array were successfully fabricated using electron beam evaporator.

Fabrication of subwavelength-size aperture for a near-field optical probe using various microfabrication procedures

We successfully fabricated subwavelength-size silicon oxide apertures on a cantilever array as a near-field optical probe. Various semiconductor processes were utilized for subwavelength-size aperture fabrication. The anisotropic etching of the Si substrate by alkaline solutions followed by anisotropic crystal orientation dependent oxidation, anisotropic plasma etching, and isotropic oxide etching was carried out. 2, 3, and 4 μm size dot arrays were initially photolithographically patterned on a Si(100) wafer. After fabrication of a V-groove shape by anisotropic etching, oxide growth at 1000 °C was performed to have an oxide etch mask. The oxide layer on the Si(111) plane has been utilized as an etch mask for plasma dry etching and water-diluted HF wet etching for subwavelength-size aperture fabrication. A Au thin layer was deposited on the fabricated oxide aperture on the cantilever array. After this procedure, the initial opening, 300 nm of the oxide aperture was reduced down to ∼95 nm.

Development of Spin-on Pre Metal Dielectrics (PMD) for 0.10UM Design Rule and Beyond

AbstractSpin-on pre metal dielectric (PMD) materials are being developed for memory and logic devices at 0.10 um design rules and beyond. The stringent design rules require a PMD material with a low thermal budget, excellent gap fill capability, and etch resistance similar to that of a thermal oxide. Spin-on PMD is being developed to meet these requirements as current PMD technologies of HDP CVD and BPSG reflow are constrained by void formation or high thermal budget requirement. One common challenge that faces spin-on PMD is inhomogeneous densification, or “corner etch”. In this paper EELS-STEM, FTIR, SEM and HF wet etching were used to study the mechanism of this phenomenon. This information provides a possible route for the development of spin-on PMD resins.

Dry Patterning of Cu(Mg) Alloy Films Using a Self-Aligned MgO Mask In an Oxygen Plasma Plus H(hfac) Chemistry

AbstractA self-aligned surface MgO layer was used as a mask for dry etching the Cu(Mg) alloy films using an O2 plasma and H(hfac) chemistry. The surface MgO layer was formed by diffusion of Mg from Cu film to the free surface. Cu(4.5at%Mg) film having thickness of 300nm was annealed in O2 ambient at 10 mTorr, 500°C for 30min, followed by the patterning of the MgO layer using photolithography and HF wet etch process. The patterned MgO layer successfully served as a hard mask for dry etching the Cu(Mg) alloy films with a taper slope. In addition, the high quality self-aligned MgO layer was formed upon annealing the Cu(4.5 at.% Mg) alloy films at the low temperature of 300°C. Furthermore, the surface MgO layer grown on Cu(2.3at.% Mg) alloy films at 500°C withstood as a hard mask for dry etching, and thus achieving the patterned copper alloy lines with the low resistivity of 2.2 μΩ-cm. Consequently, this novel etch process using a self-aligned MgO mask can be used for patterning the low resistivity copper alloy lines with a low thermal budget, which is suitable for large-size TFT-LCDs.

Miniaturization of silicon nanopillars below 10 nm by NH 4OH, KOH and HF wet chemical etching for light emission study

This paper provides a comparative study of wet etching using NH 4OH, HF and KOH to minimize the nanopillar size down to 10 nm or even lower. The nanopillars were fabricated on the p-Si substrates by deposition of Fe metal clusters using vacuum evaporation method. Subsequent ECR etching of the samples produced 100 nm high and 20 nm thick silicon nanopillars. The results of NH 4OH, HF and KOH chemical wet etching showed that the slow etch rate, 0.7 nm/h can be achieved by 50% HF acid, whereas relatively faster etch rate of 0.7 nm/s can be obtained from 40% KOH solutions. As a result of wet chemical etching, the average pillar diameter was reduced to below 10 nm. The surface morphology of the etched nanostructures was analyzed by SEM and a preliminary PL measurement was performed on the etched samples.

Dendritic material as a dry-release sacrificial layer

A dry-release process using highly structured dendritic material, specifically, hyperbranched polymers (HBP's), has been developed. A particular HBP under study, known as HB560, has been characterized and successfully integrated with microelectromechanical systems processing. An array of electroplated nickel cantilever beams 100 /spl mu/m/spl times/100 /spl mu/m /spl sim/1000 /spl mu/m in length has been successfully fabricated and dry released. The required release time is 10 min at 600/spl deg/C in O/sub 2/. Single open-ended microchannels were fabricated to determine the etch time and tunneling length achieved using HB560 as a sacrificial material. The time improvement for the sacrificial release is on the order of 40/spl times/ compared to standard HF wet-etch processes. Etch lengths of 1 cm have been successfully demonstrated with a sacrificial layer aspect ratio of 1600. A photosensitive version of the dendritic material has also been synthesized and characterized to reduce the process steps.

Low-temperature anodic bonding using lithium aluminosilicate- β-quartz glass ceramic

Silicon-to-glass anodic bonding is performed at temperatures below 180 °C using lithium aluminosllicate- β-quartz glass ceramic. High alkaline ion mobility at low temperature, which is required for bonding, and thermal expansion coefficient matching to Si are realized by controlling the composition of the glass ceramic. Bonding is obtained at a lowest temperature of 140 °C. Useful bonding conditions are temperature above 160 °C (applied voltage above 500 V). Since the etch rate of the glass ceramic is five times higher than that of Pyrex glass in HF wet etching and the undercut is very small with a Cr-Au etch mask, three-dimensional structures are easily fabricated. Low-temperature anodic bonding using this type of glass ceramic is useful for the packaging and assembling of MEMS.

An improved multi-layer fabrication process for YBa/sub 2/Cu/sub 3/O/sub 7-x/-based circuits

Improved via connections in structures of YBa/sub 2/Cu/sub 3/O/sub 7-x//SrTiO/sub 3//YBa/sub 2/Cu/sub 3/O/sub 7-x/ (YBCO/STO/YBCO) multilayers have been made using a combined HF wet-etching and ion-milling process. The critical current density J/sub c/ of the via is as high as 2/spl times/10/sup 6/ A/cm/sup 2/ at 76 K, and is dominated by edge contacts in the ab-plane, YBCO and Sr/sub 2/AlNbO/sub 6/ (SAN) multilayer test circuits were also made with this process. The 4/spl deg/ crossovers in a SAN test chip had a critical temperature T/sub c/ of 88 K and J/sub c/ of 1.5/spl times/10/sup 6/ A/cm/sup 2/ at 81 K, very close to those of the planar film, showing no evidence of weak links in the YBCO crossing low angle SAN steps.

Effect of surface pretreatment of submicron contact hole on selective tungsten chemical vapor deposition

The effects of various predeposition treatments of silicon substrates on selective tungsten chemical vapor deposition were investigated using the silane reduction process. The predeposition treatments include HF or buffered HF wet etch and/or NF3 plasma etch. The experimental results show remarkable differences in the initial nucleation of W and the smoothness of the W surface and the W/Si interface among the various treatments, as revealed by scanning electron microscope inspection and atomic force microscope analysis. Plasma etch leads to a rough W/Si interface while wet treatment with HF dip results in a fairly smooth interface. The experimental results show that better I–V characteristics for the W/n‐Si Schottky contact can be obtained by the wet etch treatment prior to the W deposition. The reverse bias junction leakage for the wet etch pretreated W/p+n junction diode is smaller than that of the plasma pretreated diode. In addition, the substrate surface treatments were found to result in Si consumpt...

Analysis and removal of impurities and defects in reactive ion etched silicon using a novel depth-profiling technique

The analysis and removal of residual damage induced by reactive ion etching of silicon were studied with a new ultrashallow depth-profiling technique of silicon. In this technique, which is known to give a depth resolution of better than 0.5 nm [Lau et al., Appl. Phys. Lett. 63, 78 (1993)], a few atomic layers of silicon were oxidized by an ultraviolet/ozone exposure at room temperature and subsequently removed by an HF wet etch. In the present study, the compositional changes during depth profiling and the amount of silicon removed per oxidation/etch cycle were estimated by x-ray photoelectron spectroscopy. In addition, Rutherford backscattering spectroscopy was used to confirm the compositional changes and to measure defect depth distributions. Further, surface-charge spectroscopy was applied to determine the minimum oxidation/etching required to completely remove Fermi-level pinning associated with the residual damage. The results showed that these profiling and analysis techniques, when applied in a coherent manner, can provide an accurate picture of the residual damage induced by reactive ion etching. More importantly, the study also showed that the oxidation/etching technique can be applied as a well-controlled process for removing the residual damage.