Hf-based Gate Stacks Research Articles

Atom-Scaled Hafnium Doping for Strengthening the Germanium Oxide Interfacial Layer of The Gate Stack of Germanium P-Type Metal-Oxide-Semiconductor Field Effect Transistor

We have developed a method that uses a half-cycle Hf precursor adsorption to subtly dope GeO2 IL of the Hf-based gate stack through in situ plasma-enhanced atomic layer deposition. This technique can effectively reduce GeO vaporization and improve the thermal stability of the GeO2 layer. Our results indicated that the accumulation capacitance (Cacc) undergoing higher temperatures showed no noticeable increase in the capacitance-voltage (CV) curves once Hf was delicately introduced into the GeO2 layer. According to the Ge 3d spectra of X-ray photoelectron spectroscopy, we found that the IL had a signal from extra Hf-O bonds; thus, we conclude GeO evaporation can be suppressed substantially by Hf incorporation. As a result, adding metal into GeOx IL to form HfGeOx achieved a remarkably low leakage current of 9 × 10−5 A cm−2 and the lowest interface trap density (Dit) of approximately 2 × 1011 eV−1 cm−2 at 500 °C of PMA. In addition, applying this gate stack structure to device fabrication significantly reduced the leakage current of the off-state and improved the effective peak hole mobility.

High-Interface-Quality Hf-Based Gate Stacks on Si0.5Ge0.5 Through Aluminum Capping

High-Interface-Quality Hf-Based Gate Stacks on Si_0.5Ge_0.5 Through Aluminum Capping

(Invited) TmSiO As a CMOS-Compatible High-k Dielectric

High-k/metal gate stacks have been a core enabler of CMOS technology for almost a decade, allowing sub-nm equivalent oxide thickness (EOT) while keeping the gate leakage current density at acceptable levels [1]. State-of-the-art high-k/metal gate stacks employ a Hf-based high-k dielectric (typically HfO2) deposited on top of a thin interfacial layer (IL), which usually consists of chemical oxide (SiOx) and whose presence is crucial in order to guarantee the overall electrical quality of the gate stack [2]. It has indeed been shown that a thinner IL, while desirable from the point of view of EOT scaling, leads to problematic degradations in channel mobility [3], threshold voltage control [4], and device reliability [5]. Further scaling of high-k/metal gate stacks has been a central subject in recent research, and is usually addressed by replacing HfO2 with a higher-k material and/or by replacing SiOx with a high-k IL. The latter strategy is especially interesting, since the IL contributes ~1/2 of the total EOT of a scaled gate stack and since there are viable options to replace SiOx with a dielectric exhibiting significantly higher dielectric constant (~3x), whereas the same is not true for higher-k dielectrics. Lanthanide silicates have especially been shown to provide controllable thickness of the IL in the sub-nm regime and device-grade interface state density, rendering them extremely interesting as a potential replacement for SiOx IL [6]. Careful consideration of the material properties from the point of view of achieving controllable and reproducible formation of a sub-nm interfacial layer has led to the identification of thulium silicate (TmSiO) as a promising candidate IL for sub-10nm CMOS nodes. A straightforward process flow, compatible with industry-standard gate-first and gate-last integration schemes, has been demonstrated for integration of TmSiO in a high-k/metal gate stack, achieving EOT of the IL of 0.25±0.15 nm and interface state density ~1·1011 cm-2eV-1 [7]. Integration of TmSiO in Hf-based gate stacks has also been shown to be compatible with threshold voltage control techniques commonly used in gate-first and gate-last integration schemes [8], and gate-last MOSFETs achieving sub-nm EOT, 10 year device reliability and higher mobility than state-of-the-art SiOx/HfO2 devices have been demonstrated [9-10]. Replacing the SiOx IL with TmSiO can be especially advantageous in terms of channel mobility and device reliability, since both device properties have been shown to degrade strongly with decreasing IL thickness. Reliability in TmSiO/HfO2 MOSFETs has been investigated from the point of view of time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI), achieving expected lifetimes of 10 years for both nFETs and pFETs at EOT~0.8 nm and gate voltage ~1V (compatible with supply voltage in sub-10nm CMOS nodes). The effect of TmSiO on channel mobility has been analyzed by measuring electron mobility at high temperature and after constant voltage stress and comparing the observed trends with published data on SiOx/HfO2 devices, with the conclusion that replacing the SiOx IL with TmSiO can improve mobility by 20% at high effective field due to reduced remote phonon scattering. In this talk, the main advantages and challenges in the adoption of TmSiO as interfacial layer in scaled CMOS technology nodes will be addressed. [1] K. Mistry et al., IEDM Tech. Dig., pp. 247–250, 2007. [2] T. Ando, Materials, vol. 5, no. 3, pp. 478–500, 2012. [3] L.-Å. Ragnarsson et al., Int. Symp. VLSI Technol. Syst. Appl., 2011. [4] T. Ando et al., IEEE Electron Device Lett., vol. 34, no. 6, pp. 729–731, 2013. [5] E. Cartier et al., IEDM Tech. Dig., pp. 441–444, 2011. [6] T. Kawanago et al., IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 269–276, 2012. [7] E. Dentoni Litta et al., IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3271–3276, 2013. [8] E. Dentoni Litta et al., Solid-State Electron., vol. 108, pp. 24-29, 2015. [9] E. Dentoni Litta et al., IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 934–939, 2015. [10] E. Dentoni Litta et al., IEEE J. Electron Devices Soc., vol. 3, no. 5, pp. 397–404, 2015.

(Invited) Dielectric Breakdown in Ultra-Thin Hf Based Gate Stacks: A Resistive Switching Phenomenon

The gate dielectric breakdown (BD) reversibility in MOSFETs with ultra-thin hafnium based high-k dielectric is studied. The phenomenology is analyzed in detail and the similarities with the resistive switching phenomenon emphasized. The results show that after BD, the switch between two different conductive states in the dielectric is possible. We have demonstrated that the conduction in both states is local, which has been verified through CAFM measurements. Additionally, the injected charge to the first recovery (QR) has been proposed as a parameter to describe the BD reversibility phenomenon. The BD recovery partially restores not only the current through the gate, but also the MOSFET channel related characteristics. The electrical performance of MOSFETs after the dielectric recovery has been modeled and introduced in a circuit simulator. The simulation of several digital circuits shows that their functionality, though somehow affected, can be restored after BD recovery.

Effect of Y Content in (TaC)1-xYx Gate Electrodes on Flatband Voltage Control for Hf-Based High-k Gate Stacks

The effects of varying the yttrium (Y) level in a (TaC)1-xYx gate electrode on the structural and electrical properties of a hafnium (Hf)-based high-k metal–oxide–semiconductor (MOS) capacitor, including flatband voltage (Vfb), were evaluated. The composition of (TaC)1-xYx was controlled by the power of pure TaC and Y targets in magnetron sputtering. The structure of the formed (TaC)1-xYx film was that of either a face-center cubic (fcc) at all compositions of x≤0.4 or amorphous at x≥0.5 after annealing at temperatures below 600 °C. X-ray photoelectron spectroscopy (XPS) analysis revealed that the TaC and (TaC)1-xYx films all contained about 10% oxygen. The resistivity of the (TaC)1-xYx films was invariant for all compositions of x≤0.5, but it increased with increasing annealing temperature up to 600 °C for compositions of x≥0.68. In the as-deposited case, the effective work function, which was estimated from the relationship between Vfb and the equivalent oxide thickness of the HfO2 film, clearly changed from 4.8 to 4.3 eV as x increased. The Vfb of HfO2 and HfSiOx dielectrics could be controlled within 0.5 V after annealing at 500 °C by changing the composition of the (TaC)1-xYx film (in terms of x). Based on the experimental data, it is clear that (TaC)1-xYx composites are candidate materials for n-metal gate electrodes in the gate-last process.

Resistive switching-like behavior of the dielectric breakdown in ultra-thin Hf based gate stacks in MOSFETs

The gate dielectric breakdown (BD) reversibility in MOSFETs with ultra-thin hafnium based high-k dielectric is studied. The phenomenology is analyzed in detail and the similarities with the resistive switching phenomenon emphasized. The results suggest that the conductive path in the dielectric after BD can be ‘opened’ and ‘closed’ many times and that the BD recovery partially restores not only the current through the gate, but also the MOSFET channel related electrical characteristics.

A strong analogy between the dielectric breakdown of high-K gate stacks and the progressive breakdown of ultrathin oxides

The breakdown of high-K (HK) stack gate dielectrics is shown to be analogous to the failure of ultrathin SiO2-based oxides showing progressive breakdown. The breakdown of a HK stack is shown to occur in two phases. First, one or several percolation paths are formed in the SiO2-based interfacial layer. Then, these partial breakdowns propagate into the HK through defect generation in this layer. This propagation phase is equivalent to the progressive breakdown local degradation phenomenon. As a consequence of this analogy, the reliability assessment tools developed for ultrathin single-layer oxides can also be used without significant changes to assess the reliability of HK stacks. This analogy is so strong that the experimental distinction between HK propagation and conventional progressive breakdown appears to be rather difficult. However, the residual time distribution from first breakdown to final oxide failure is shown to be significantly different for both processes at low failure percentiles. This has allowed us to obtain experimental evidence of HK propagation (as opposed to conventional progressive breakdown effects) in relatively thick Hf-based gate stacks where the detection of first BD appears to be feasible.

Effects of TaN, Ru, and Pt electrodes on thermal stability of hafnium-based gate stacks

Potential p-FET high-work function metals, TaN, Ru, and Pt are shown to have distinct effects on the stability of Hf-based gate stacks during a thermal process. Ru and Pt promote catalytic decomposition of the underlying dielectrics, resulting in the formation of HfSix and Ru(Pt)Six at 950 (900) °C. With Ru, hydroxyl impurities are critical in silicidation which is localized in the vicinity of voids where the Si substrate is exposed through partial HfO2 and SiO2 decomposition. The degree of silicide formation is greater with Pt, occurring upon major decomposition of the underlying dielectrics with or without hydroxyl impurities. Transfer of electrons from the HfO2 oxygen vacancy to Ru and Pt may play a role in the decomposition of the dielectric films. In contrast, the thermal evolution of TaN-gate stacks is very similar to that of HfO2 stacks without any capping metal layer. With annealed HfO2 and HfO2/TaN stacks there is no detectable metal diffusion into the dielectrics, and the overall compositional stability is preserved except for the growth of interfacial SiO2.

Breakdown and degradation of ultrathin Hf-based (HfO2)x(SiO2)1−x gate oxide films

Ultrathin films of hafnium oxide (HfO2) and hafnium silicate (HfO2)x(SiO2)1−x gate stacks (∼3nm) have been subjected to localized electrical stress with a conductive atomic force microscope (C-AFM) in ultrahigh vacuum. The nanoscale current-voltage (I-V) characteristics, prebreakdown temperature dependent I-V measurements on large area metal-insulator-semiconductor capacitors, postbreakdown (BD) topography, current maps, and AFM tip-surface contact force are used to interpret the progressive degradation of the oxide under electrical stress. For the pre-BD phase, trap-assisted tunneling and Fowler–Nordheim tunneling were found to be dominant current transport mechanisms in Hf-based gate stacks contributing to oxide leakage current. For the post-BD phase, an overall effect of barrier limited tunneling current on the charge propagation is confirmed and related to post-BD conductivity features observed by constant voltage scanning. A critical trap density required to trigger a BD event of the ultrathin (HfO2)x(SiO2)1−x∕SiO2 gate stacks is postulated.

Dominant Layer for Stress-Induced Positive Charges in Hf-Based Gate Stacks

Positive charges in Hf-based gate stacks play an important role in the negative bias temperature instability of pMOSFETs, and their suppression is a pressing issue. The location of positive charges is not clear, and central to this letter is determining which layer of the stack dominates positive charging. The results clearly show that positive charges are dominated by the interfacial layer (IL) and that they do not pile up at the HfSiON/IL interface. The results support the assumption that positive charges are located close to the IL/substrate interface. Unlike electron trapping that reduces rapidly for thinner Hf dielectric layer, positive charges cannot be reduced by using a thinner HfSiON film.

Comparative Study of Plasma Source-Dependent Charging Polarity in Metal–Oxide–Semiconductor Field Effect Transistors with High-k and SiO2 Gate Dielectrics

The polarities of charging damage in n- and p-channel metal–oxide–semiconductor field effect transistors (MOSFETs) with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar- and Cl-based gas mixtures) and found to depend on plasma conditions, in contrast to those with conventional SiO2. It was also found that high-k devices were more susceptible to plasma charging damage than SiO2 devices. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-channel MOSFETs with high-k gate stacks suffer from negative charge trapping, whereas for Cl-plasma confirmed to induce less damage, both n- and p-channel MOSFETs with high-k gate stacks suffer from positive charge trapping. The above-mentioned plasma-source-dependent charging damage was also compared on the basis of the results obtained by the plasma diagnostics. From the results of constant-current stress tests, the unique charging polarity observed for the high-k gate stack was attributed to the characteristic hole and electron trapping phenomena, in accordance with the injected stress current and stress time, implying the necessity of taking the intrinsic charge trapping process into consideration for accurate evaluations of charging damage on high-k gate dielectrics.

Process-induced positive charges in Hf-based gate stacks

Hf-based gate stacks will replace SiON as a gate dielectric even though our understanding of them is incomplete. For an unoptimized SiO2 layer, an exposure to H2 at a temperature over 450 °C can lead to positive charging. In this work, we will show that a thermal exposure of Hf-based gate stacks to H2 can also induce a large amount of positive charge (∼1013 cm−2). There is little information available on this process-induced positive charge (PIPC) and the objective of this work is to fill this knowledge gap. The work is divided into two parts: an investigation of the features and properties of PIPC, followed by an exploration of its dependence on process conditions. It will be shown that PIPC does not originate from the generation of interface states, is stable both thermally and electrically, and has a large sample-to-sample variation. It consists of two components: fixed and mobile. Regarding its dependence on process conditions, PIPC occurs in both HfO2 and Hf-silicate stacks, in devices with either TaN or poly-Si gates, and in both p metal-oxide-semiconductor field-effect transistors (pMOSFETs) and nMOSFETs. PIPC is generally enhanced by nitridation, although it can also be observed in some Hf-based gate stacks without nitridation.

Theoretical Studies on Fermi Level Pining of Hf-Based High-k Gate Stacks Based on Thermodynamics

We have studied Fermi level pinning of Hf-based high-k gate stacks based on thermodynamics by our O vacancy model. Our study shows that FLP cannot be avoided when the system is under thermal equilibrium. O injection to aim O vacancy elimination is hopeless, since O vacancy elimination condition is equivalent to the Si substrate oxidation which leads to the increase in EOT. We also studied the mechanism of FLP induced by H2 anneal. FLP by H2 anneal is governed by the O vacancy annihilation reaction by reducing SiO2 interface layer. Moreover, we briefly discuss the recipe for obtaining band-edge-work-function metals.

Theoretical Studies on Fermi Level Pining of Hf-Based High-k Gate Stacks Based on Thermodynamics

not Available.

Threshold Voltage Control of Hf-based High-κ Gate Stack System by Fluorine Incorporation into Channel and Its Impact on Short-Channel Characteristics

A threshold voltage lowering of up to 400 mV in HfSiON/polycrystalline silicon (poly-Si) gate stack p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) by fluorine incorporation into the channel is observed. Physical analysis verifies that implanted fluorine exists only in the channel region. The characteristics of the short-channel devices are investigated in detail, and an acceptor generation model by fluorine implantation is proposed. The model successfully explains the characteristics of fluorine-incorporated short-channel pMOSFETs.

Thermal stability studies of fully silicided NiSi on Si-oxynitride and Hf-based high-κ gate stacks

The thermal stability of fully silicided (FUSI) NiSi∕Hf-based high-κ gate stacks upon exposure to a typical back-end-of-line (BEOL) N2 annealing or forming gas annealing is investigated. Our results demonstrate that there is no new phase formation during postsilicidation N2 annealing for blanket FUSI NiSi stack films. However, new phases are formed once the stack is exposed to forming gas annealing for 1h at 445°C. After a typical BEOL thermal budget annealing (350°C, 60min), Ni diffusion is observed into the Si channel through a thin 1.3nm Si-oxynitride layer, and increases with annealing temperature and time. The Ni penetration from the FUSI NiSi gate electrode structure is completely inhibited with thicker 5nm gate dielectric layers upon exposure to a similar BEOL annealing. The relatively weaker Ni–Ni bonds associated with Ni-rich phases coupled with grain boundary diffusion of liberated Ni likely contribute to Ni diffusion through dielectrics into the Si channel.

Beyond SiO 2 technology: Simulation of the impact of high- κ dielectrics on mobility

A critical challenge for the microelectronics industry is the need for higher permittivity dielectrics to replace silicon dioxide. A number of different high- κ materials have been proposed and analyzed as SiO 2 replacements in the next generation of MOSFETs. High- κ materials allow the use of a thicker gate dielectric, maintaining the gate capacitance with reduced gate leakage. However they all lead to mobility degradation due to, among other factors, the coupling of carriers to surface soft-optical (SO) phonons. A severe mobility degradation in the presence of high- κ becomes evident when comparing the vertical field dependence of mobility for a wide range of high- κ materials against SiO 2. As oxides containing Hf presently appears to be the leading high- κ contenders, we have performed a detailed analysis of Hf-based gate stacks, exploiting alternative structures and compositions. The introduction of a SiO 2 interfacial layer between the channel and the HfO 2 reduces the detrimental mobility degradation resulting from the mobility SO phonon scattering, but increases the equivalent oxide thickness (EOT) of the gate dielectric. A possible material of choice for the first commercial introduction of high- κ gate stacks is hafnium silicate (Si x Hf 1− x O 2), being thermally stable and offering a good compromise between small EOT and large electron mobility.

Breakdown characteristics of nFETs in inversion with metal/HfO 2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO 2 high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (⩽3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown ( T BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.

Modeling of Tunnelling Currents in Hf-Based Gate Stacks as a Function of Temperature and Extraction of Material Parameters

In this paper, we show that through electrical characterization and detailed quantum simulations of the capacitance-voltage and current-voltage (I-V) characteristics, it is possible to extract a series of material parameters of alternative gate dielectrics. We have focused on HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and HfSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Y</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</sub> gate stacks and have extracted information on the nature of localized states in the dielectric responsible for a trap-assisted tunneling (TAT) current component and for the temperature behavior of the I-V characteristics. Simulations are based on a one-dimensional Poisson-Schroumldinger solver capable to provide the pure tunneling current and TAT component. Energy and capture cross section of traps responsible for TAT current have been extracted

The effect of interfacial layer properties on the performance of Hf-based gate stack devices

The influence of Hf-based dielectrics on the underlying SiO2 interfacial layer (IL) in high-k gate stacks is investigated. An increase in the IL dielectric constant, which correlates to an increase of the positive fixed charge density in the IL, is found to depend on the starting, pre-high-k deposition thickness of the IL. Electron energy-loss spectroscopy and electron spin resonance spectra exhibit signatures of the high-k-induced oxygen deficiency in the IL consistent with the electrical data. It is concluded that high temperature processing generates oxygen vacancies in the IL responsible for the observed trend in transistor performance.