Heterojunction Field Effect Transistors Research Articles

Monolithic E/D-mode P-GaN/AlGaN/GaN HFETs using reactivation annealing process

A reactivation annealing process was developed to restore the deactivated p-type characteristics of an Mg-doped p-type GaN layer subsequent to exposure to the SiNx passivation step in a p-GaN gated AlGaN/GaN heterojunction field-effect transistor (HFET). The deactivation, induced by the formation of H–Mg complexes during the passivation process, necessitates an additional activation annealing procedure. Notably, it was observed that the passivation film on the p-GaN layer must be removed through etching prior to annealing, aiming to eliminate H atoms from H–Mg complexes. The reactivation annealing process was conducted at 800 °C. Employing this reactivation approach, we successfully demonstrated monolithic enhancement- and depletion-mode p-GaN/AlGaN/GaN HFETs.

Dual-Junction Field-Effect Transistor with Ultralow Subthreshold Swing Approaching the Theoretical Limit.

Metal-oxide-semiconductor field-effect transistors as basic electronic devices of integrated circuits have been greatly developed and widely used in the past decades. However, as the thickness of the conducting channel decreases, the interface electronic scattering between the gate oxide layer and the channel significantly impacts the performance of the transistor. To address this issue, van der Waals heterojunction field-effect transistors (vdWJFETs) have been proposed using two-dimensional semiconductors, which utilize the built-in electric field at the sharp van der Waals interface to regulate the channel conductance without the need of a complex gate oxide layer. In this study, a novel dual-junction vdWJFET composed of a MoS2 channel and a Te nanosheet gate has been developed. This device achieves an ultralow subthreshold swing (SS) and an extremely low current hysteresis, greatly surpassing the single-junction vdWJFET. In the transistor, the SS decreases from 475.04 to 68.3 mV dec-1, nearly approaching the theoretical limit of 60 mV dec-1 at room temperature. The pinch-off voltage (Vp) decreases from -4.5 to -0.75 V, with a current hysteresis of ∼10 mV and a considerable field-effect mobility (μ) of 36.43 cm2 V-1 s-1. The novel dual-junction vdWJFET provides a new approach to realize a transistor with a theoretical ideal SS and a negligible current hysteresis toward low-power electronic applications.

Bias-dependent electron velocity and short-channel effect in scaling sub-100 nm InAlN/GaN HFETs

This work reports on the extraction and simulation of the electron velocity–gate voltages relationship for sub-100 nm InAlN/GaN heterojunction field-effect transistors (HFETs). A peak electron velocity (ve) at an electron density (ns) of 0.41 × 1013 cm−2 was observed at 1.06 × 107 cm/s in an InAlN/GaN HFET with 60 nm gate length (Lg) by delay time analysis. The ve at a high ns of 1.5 × 1013 cm−2 was observed at 0.6 × 107 cm/s. This peak ve behavior is explained by polarization Coulomb field (PCF) scattering and optical phonon scattering based on a Monte Carlo method. As Lg scaled from 350 to 60 nm, the current gain cutoff frequency (fT) and transconductance (gm) were improved. However, the thermal performance was degraded with a bad figure of merit P150 °C. Although a weakening of the control capability of Vgs on ns (Δns/ΔVgs) was observed in the shorter Lg device, which leads to a decrease in device gm, the larger electron velocity by the increased lateral electric field (E) and the larger Δve/ΔVgs by the increased PCF scattering still enhance the peak gm. Results indicate that the enhancement of Δve/ΔVgs is a vital method to strengthen the modulation of the gate on current and to suppress the short channel effect in GaN HFET. Our work supports a deeper understanding and analysis of sub-100 nm InAlN/GaN HFET device performance and physical mechanisms.

Reduction in density of interface traps determined by C-V analysis in III-nitride-based MOSHFET structure

An in situ metal-organic chemical vapor phase epitaxy is used to grow a complete AlGaN/GaN metal oxide semiconductor heterojunction field effect transistor (MOSHFET) structure, gated by a gallium oxide (Ga2O3) layer; we observed reduction in the interfacial trap density compared to its version wherein the Ga2O3 was grown ex situ, after breaking the vacuum, all else being the same. A remarkable decrease in the interfacial charge density for in situ MOSHFET structures in the range of 70%–88% for 10–30 nm oxide layer thickness and improvements in other electrical parameters required for high-performing devices were observed.

Normally-off recessed gate β-Ga2O3 MOSHFETs with a modulation-doped heterostructure back-barrier

This study demonstrates enhancement-mode recessed-gate β-Ga2O3 metal–oxide–semiconductor heterojunction field-effect transistors (MOSHFETs) with a combination of the MOS channel and a modulation-doped heterostructure to improve maximum drain current and on-resistance (RON). In this proposed device concept, modulation doping in the heterostructure back-barrier inserted into the MOS channel increases the electron density in the MOS channel while maintaining a normally-off operation. First, 2D simulations of enhancement-mode recessed-gate β-Ga2O3 metal–oxide–semiconductor field-effect transistors (MOSFETs) were performed in a Silvaco ATLAS TCAD environment to calibrate the transfer characteristics with the measured data of the investigated device reported previously. Second, using calibrated physical models and parameters, the transfer and transconductance characteristics, and output and off-state characteristics of the enhancement-mode recessed-gate β-Ga2O3 MOSHFETs were comprehensively investigated. The maximum drain current at VGS = 8 V and VDS = 10 V could be increased up to 32.6 mA mm−1 from 9.1 mA mm−1 with the MOSHFET in comparison with that of the recessed-gate MOSFET. The breakdown voltage increased considerably from 186 V to 226 V for the recessed-gate MOSHFET. The proposed device also showed a lower RON, which decreased from 354 Ω.mm to 214 Ω.mm owing to greater electron accumulation in the channel owing to the introduction of the modulation-doped heterostructure.

A comparative study of work function variations in III-V heterojunction and homojunction tunnel field-effect transistors

In this paper, we present a comparative study on the impact of work function variations (WFV) between the III-V heterojunction and homojunction tunnel field-effect transistors (TFETs) vis TCAD simulation. It reveals that, in general, the current variation of both devices decrease as the gate voltage increases, and the threshold voltage variations generally increase with the increase of threshold current. However, in comparison to homojunction TFET, heterojunction TFET exhibits the following two differences. 1) The current fluctuation is stronger near the device's OFF-state and weaker near the ON-state, and thus it has a stronger dependence on bias. 2) Both the threshold voltage fluctuations and its dependence on the threshold current are weaker. On the other hand, with an increase in grain size, both homojunction and heterojunction devices manifest more prominent performance fluctuations. Moreover, the dependence of these fluctuations on grain size is roughly comparable for these two device types. Finally, it is observed that 1) the significant current fluctuation at the OFF-state can be mitigated when the device's OFF-state is designed within a region with weaker gate control, and 2) the current normalized coefficient of variation parameter may be unreliable to assess the fluctuation for the case with a few “abnormal” high current values.

Polarized Coulomb field scattering in LaAlO3/SrTiO3 heterojunction field-effect transistors

LaAlO3/SrTiO3 heterojunction field-effect transistors (HFETs) were fabricated. Using a combination of measured current–voltage (I–V) output curves and gate-source capacitance–voltage (C–V) characteristic curves for the fabricated LaAlO3/SrTiO3 HFETs, and considering scattering mechanisms for longitudinal optical phonon, interface rough, electron-electron (E-E), acoustic phonon, and polarized Coulomb field (PCF), the channel electron mobility of LaAlO3/SrTiO3 HFETs has been calculated and analyzed. The results showed that PCF scattering is a significant carrier scattering mechanism in LaAlO3/SrTiO3 HFETs. The heterostructure of the LaAlO3/SrTiO3 system has strong polarization characteristics. This paper is the first to demonstrate that PCF scattering is a significant carrier scattering mechanism in LaAlO3/SrTiO3 HFETs, following GaN HFETs, thus demonstrating that LaAlO3/SrTiO3 HFETs also have PCF scattering effect.

Bidirectional rectifier with gate voltage control based on Bi2O2Se/WSe2 heterojunction

Two-dimensional (2D) WSe2 has received increasing attention due to its unique optical properties and bipolar behavior. Several WSe2-based heterojunctions exhibit bidirectional rectification characteristics, but most devices have a lower rectification ratio. In this work, the Bi2O2Se/WSe2 heterojunction prepared by us has a type Ⅱ band alignment, which can vastly suppress the channel current through the interface barrier so that the Bi2O2Se/WSe2 heterojunction device has a large rectification ratio of about 105. Meanwhile, under different gate voltage modulation, the current on/off ratio of the device changes by nearly five orders of magnitude, and the maximum current on/off ratio is expected to be achieved 106. The photocurrent measurement reveals the behavior of recombination and space charge confinement, further verifying the bidirectional rectification behavior of heterojunctions, and it also exhibits excellent performance in light response. In the future, Bi2O2Se/WSe2 heterojunction field-effect transistors have great potential to reduce the volume of integrated circuits as a bidirectional controlled switching device.

Effect of SiO2 Surface Passivation on the Performance of GaN Polarization Superjunction Heterojunction Field Effect Transistors

In this article, the effects of the SiO2 surface passivation layer are reported on normally‐on 1.2 kV GaN polarization superjunction (PSJ) heterojunction field effect transistors (HFETs) by comparing the electrical performances of PSJ HFETs with and without SiO2 surface passivation. A slight recovery of the 2D electron gas sheet density is observed in the slight negative shift of Vth after SiO2 surface passivation. Passivation also increases the breakdown voltage. This improvement may result from removing positive surface charges in defects along the P‐GaN gate sidewall and top u‐GaN layer after the specifically designed SiO2 surface passivation. Furthermore, the SiO2 surface passivation can also effectively suppress the surface gate leakage currents in the PSJ HFETs by eliminating the conductive channel created by the positive surface charges in defects.

Simulation study of multi-source hetero-junction TFET-based capacitor less 1T DRAM for low power applications

A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The analysis of the three memory functions: Write, Hold and Read of 1T DRAM has been carried out using Synopsys TCAD simulations. A storage region of Ge material is used for the accumulation of holes/to store the charge carriers. The variation in length of Ge-storage region, under lap length (Lunder), and temperature is performed to analyse the DRAM performance. In the Write operation, the tunneling window reduces to 15 nm and holes can be easily stored in the Ge-storage region. In case of Hold1 and Read1 operations, the potential barriers are reduced by 0.24 eV, and 0.1 eV respectively. In the proposed multi-source TFET with 14 nm gate length, read current ratio i.e. IR1/IR0 of 4.4, retention time (RT) greater than 10 sec, and sense margin (SM) of 1.27 × 10−6 A/µm is achieved at room temperature. The proposed multi-source TFET based 1T DRAM is operating at very low gate voltages. Therefore, this device is well suited for low power applications.

Ferroelectric passivation layer derived high performance AlGaN/GaN heterojunction field-effect transistor

The density of interface states is strongly related to the performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) and is normally attributed to the degradation of the carrier mobility and gate leakage current. The density of interface states is optimized in conventional AlGaN/GaN HEMTs through the use of different passivation layers. However, different passivation layers may create more complex interface structures. In our previous work, ferroelectric polarization was used to regulate the carrier concentration in AlGaN/GaN HEMTs. Herein, we propose a ferroelectric passivation-layer-induced pure field effect modulation within the AlGaN/GaN heterojunction field-effect transistors. After positive poling, the interface trap density (Dit) decreases by 71% and current collapse is reduced. The output current (IDS) increases from 408 to 462 mA/mm and transconductance (gm) increases from 88 to 149 mS/mm. Simultaneously, the carrier mobility in the channel is also greatly improved after positive poling. When negative poling is applied, the gate leakage decreases and the breakdown voltage of the device increases by 55%. Our work provides a simple and effective way to study the density of interface states in GaN device design and optimization.

Fluorine-Based Low-Damage Selective Etching Process for E-Mode p-GaN/AlGaN/GaN HFET Fabrication

In this study, we conducted an optimization of a low-damage selective etching process utilizing inductively coupled plasma-reactive ion etch (ICP-RIE) with a fluorine-based gas mixture. This optimization was carried out for the fabrication of p-GaN gated AlGaN/GaN enhancement-mode (E-mode) heterojunction field-effect transistors (HFETs). The optimum process conditions resulted in an etch selectivity of 21:1 (=p-GaN:Al0.2Ga0.8N) with a p-GaN etch rate of 5.2 nm/min and an AlGaN etch rate of 0.25 nm/min. In comparison with an oxygen-based selective etching process, the fluorine-based selective etching process demonstrated reduced damage to the etched surface. This was confirmed through current–voltage characteristics and surface roughness inspections. The p-GaN gated AlGaN/GaN E-mode device, fabricated using the optimized fluorine-based selective etching process, achieved a high threshold voltage of 3.5 V with a specific on-resistance of 5.3 mΩ.cm2 for the device and with a gate-to-p-GaN gate distance of 3 μm, a p-GaN gate length of 4 μm, and a p-GaN gate-to-drain distance of 12 μm. The catastrophic breakdown voltage exceeded 1350 V.

Normally-off n-ZnO/p-diamond heterojunction field effect transistor with recessed gate and current distribution layer

In this paper, an n-ZnO/p-diamond heterojunction field effect transistor (HJ-FET) with recessed gate and current distribution layer is designed and optimized by using TCAD software. It demonstrates that the threshold voltage and breakdown voltage can be remarkably affected by the doping concentration and thickness of both n-ZnO and p-diamond. Additionally, the threshold voltage can be further enhanced by introducing a recessed gate due to the enhanced depletion capacity on the channel layer. Although the conduction modulation by the enhanced electric field decreases the on-resistance, the obviously decreased breakdown voltage by the recessed gate degrades the electrical performances. Finally, a current distribution layer between source and drain electrodes is added to decrease the on-resistance of diamond HJ-FET. After optimizing the parameters, the diamond HJ-FET exhibits a larger threshold voltage, a smaller on-resistance and a higher breakdown voltage.

Detection of lead ions with enhancement-mode GaN-based heterojunction field-effect transistors

Detection of lead ions with enhancement-mode GaN-based heterojunction field-effect transistors

Novel Vertical Fin-Based NiO/β-Ga2O3 Heterojunction Field-Effect Transistor with a Low Ron,sp

In this paper, a novel vertical fin-based NiO/β-Ga2O3 heterojunction field-effect transistor (Fin-HJFET) is proposed and studied by TCAD. Theoretically high conduction band offset () enables Ga2O3 Fin-HJFET to produce electron confinement effect at certain gate bias voltage. According to the simulation results, this effect makes Ga2O3 Fin-HJFET can not only form surface-conducting fin channels that are not available in conventional fin-based junction field-effect transistor (Fin-JFET) but also have a stronger electron accumulation capability than Ga2O3 vertical FinFET due to the deep potential well, which leads to a lower specific on-resistance (). In addition, Ga2O3 Fin-HJFET inherits the advantages of Ga2O3 FinFET as a vertical normally-off device and has a higher breakdown voltage compared to FinFET without field plates due to the protection of the highly doped NiO layer. Particularly, Fin-HJFET with different heterojunction band alignments are also considered and discussed. At last, the parameter influence and future optimization space of this highly promising device are explored, providing guidance for actual device fabrication and future device improvement.

Robust Al0.23Ga0.77N channel HFETs on bulk AlN for high voltage power electronics

AlxGa1-xN heterojunction FETs (HFETs) have been an eye catcher for high voltage power electronics with its potential to outperform the predecessors by virtue of high critical breakdown field of the material, which can be tuned by varying Al mole-fraction. In this work, we demonstrate Al0.23Ga0.77N channel HFETs on bulk AlN with a maximum drain current density > 300 mA/mm and a specific Ron = 4 mΩ·cm2. A buffer electric breakdown field >10 MV/cm was measured. A high voltage robustness comparison of Al0.23Ga0.77N channel HFETs and thin GaN HFETs close to their respective hard breakdown voltages is also concluded, which reveals the superior reliable operation of Al0.23Ga0.77N channel HFETs up to 80% of hard breakdown voltages along with a consistent ION/IOFF ratio subsequent to 2000V voltage sweep.

The isolation feature geometry dependence of reverse gate-leakage current of AlGaN/GaN HFETs

Reverse gate-leakage current of AlGaN/GaN heterojunction field-effect transistors (HFETs) realized on array of submicron sized fins and conventional mesa isolation feature geometries is investigated at room temperature and zero drain-source bias. For each of the abovementioned device categories, the significance of leakage from the top surface gate as well as gated etched GaN surfaces, especially sidewalls, is studied for a wide range of gate-source voltages (VGS) (i.e. below and above the threshold voltage). It is proven that in the explored fin-type HFETs, for all values of VGS leakage through the gated GaN surfaces, especially the sidewalls, is more significant than the leakage from the top surface gate. This is while in the mesa category, the sidewall leakage is of importance only at less negative values of VGS, and leakage from the top surface gate substantially takes over at more negative VGS values. The discrepancy in the dominance of the aforementioned leakage paths at more negative VGS values among the explored fin and mesa-type HFETs is demonstrated to be due to the stronger electric field across the barrier in the gated region of the mesa-type HFET for this range of VGS. While in the explored fin-type HFETs Ion/Ioff ratio is as high as 2 × 107, the total amount of reverse gate-leakage at all values of VGS is substantially larger compared to the mesa category sharing an equal value of the overall gate width, which substantiates the significance of leakage through etched GaN surfaces in devices composed of larger number of sidewalls, incorporating larger area of gate-overlapping etched GaN surface.

Visible–infrared dual-band detection with a polarization sensitivity based on GeSe/Ge heterojunction field effect transistor

Electronic and optoelectronic devices based on two-dimensional (2D)/three-dimensional (3D) semiconductor heterostructures, combining their respective advantages, have attracted wide attention. In this work, we fabricate a mixed-dimensional GeSe/Ge heterojunction field effect transistor (HJFET), which combines high carrier mobility of 2D GeSe and near-infrared detection of 3D bulk Ge. A significant on/off ratio of 5 × 102 and a transconductance of 0.23 μS are obtained, indicating a convincing gate control ability. Under 532 nm illumination, the HJFET exhibits an excellent photoresponse with high responsivity, detectivity, and external quantum efficiency (88.4 A/W, 2.25 × 1012 Jones, and 3280%), and it also can detect the infrared light of 1550 nm due to the absorption of Ge gate. The photogenerated electrons at 532 nm flow to Ge back gate when HJFET works at the reverse voltage bias, which prolongs the lifetime of photogenerated holes in the GeSe channel, thus increasing photocurrent and obtaining better the detection properties. Additionally, the transistor also exhibits polarization-sensitive behavior with a dichroic ratio of 2.37, which can be attributed to the strong anisotropic absorption property of GeSe in armchair and zigzag directions. These results indicate that the device has promising potential as a multifunctional optoelectronic unit, including on/off characteristic, broadband photodetection, and polarization sensitivity.

Electrical and Electronic Properties of Magnesium/Molybdenum Disulfide Heterojunction Field Effect Transistors: A Theoretical Study

The present article designs two-dimensional heterojunction duplex material FETs based on binary monolayer material, Mg and molybdenum disulfide. Despite having a hexagonal crystal structure, the monolayer Mg and molybdenum disulfide have good lattice matching ability, with a mismatch degree of approximately 5%. The electrostatic characteristics of Mg/molybdenum disulfide field effect transistors (FETs) are well suited for compact fabrication. Electronic structure of first-principles investigations, optical, mechanical, and electrochemical properties of MODES field-effect transistors based on density functional theory are mastered in order to master the electrostatic doping associated features of FETs. Based on the Silvaco TCAD platform, this simulation study was performed. There is theoretical value in engineering practice, both in terms of design and application.

Piezotronic and Piezo-Phototronic Effects-Enhanced Core-Shell Structure-Based Nanowire Field-Effect Transistors.

Piezotronic and piezo-phototronic effects have been extensively applied to modulate the performance of advanced electronics and optoelectronics. In this study, to systematically investigate the piezotronic and piezo-phototronic effects in field-effect transistors (FETs), a core-shell structure-based Si/ZnO nanowire heterojunction FET (HJFET) model was established using the finite element method. We performed a sweep analysis of several parameters of the model. The results show that the channel current increases with the channel radial thickness and channel doping concentration, while it decreases with the channel length, gate doping concentration, and gate voltage. Under a tensile strain of 0.39‱, the saturation current change rate can reach 38%. Finally, another core-shell structure-based ZnO/Si nanowire HJFET model with the same parameters was established. The simulation results show that at a compressive strain of -0.39‱, the saturation current change rate is about 18%, which is smaller than that of the Si/ZnO case. Piezoelectric potential and photogenerated electromotive force jointly regulate the carrier distribution in the channel, change the width of the channel depletion layer and the channel conductivity, and thus regulate the channel current. The research results provide a certain degree of reference for the subsequent experimental design of Zn-based HJFETs and are applicable to other kinds of FETs.