Heterojunction Field Effect Transistors Research Articles

AlN/AlGaN heterojunction field-effect transistors with a high-AlN-mole-fraction Al0.72Ga0.28N channel grown on single-crystal AlN substrate by metalorganic chemical vapor deposition

This paper presents research results on AlN/AlGaN heterojunction field-effect transistors (HFETs) with a high-AlN-mole-fraction Al0.72Ga0.28N channel grown on a single-crystal AlN substrate by metalorganic chemical vapor deposition. Material evaluation results confirmed that the grown AlGaN layer was 100% coherently grown for the underlying AlN substrate and thereby had superior crystal quality as well as the substrate. The fabricated AlGaN-channel HFETs with a gate length of 2 μm exhibited pinch-off characteristics with the max. current density (I DS_MAX) of 21 mA mm−1, the on-state resistance of 250 Ωmm, the peak transconductance of 4.5 mS mm−1 with the threshold voltage of –4.6 V, and the on/off ratio of 4 × 10−5. The temperature dependence of DC characteristics confirmed that the I DS_MAX decreased by 15% and the off-leakage current increased from 60 nA mm−1 to 10 μA mm−1 within the temperature range from room temperature to 200 °C.

Gate modulation of barrier height of unipolar vertically stacked monolayer ReS2/MoS2 heterojunction

This study investigates vertically stacked CVD grown ReS2/MoS2 unipolar heterostructure device as Field Effect Transistor (FET) device wherein ReS2 on top acts as drain and MoS2 at bottom acts as source. The electrical measurements of ReS2/MoS2 FET device were carried out and variation in Ids (drain current) Vs Vds (drain voltage) for different Vgs (gate voltage) revealing the n-type device characteristics. Furthermore, the threshold voltage was calculated at the gate bias voltage corresponding to maximum transconductance (gm) value which is ~ 12 V. The mobility of the proposed ReS2/MoS2 heterojunction FET device was calculated as 60.97 cm2 V−1 s−1. The band structure of the fabricated vDW heterostructure was extracted utilizing ultraviolet photoelectron spectroscopy and the UV–visible spectroscopy revealing the formation of 2D electron gas (2DEG) at the ReS2/MoS2 interface which explains the high carrier mobility of the fabricated FET. The field effect behavior is studied by the modulation of the barrier height across heterojunction and detailed explanation is presented in terms of the charge transport across the heterojunction.

High performance E-mode NiO/β-Ga2O3 HJ-FET with high conduction band offset and thin recessed channel

In this paper, an enhancement-mode (E-mode) NiO/β-Ga2O3 heterojunction field-effect transistor (HJ-FET) with high conduction band offset (ΔEC) and thin recessed channel is proposed and studied by Sentaurus TCAD. Different from the existing HJ-FET with low ΔEC alignment, the High ΔEC HJ-FET can achieve a much lower on-resistance (Ron) due to the strong electron confinement effect. More importantly, the disadvantage in the threshold voltage (Vth) is compensated by reducing the thickness of the recessed channel, maintaining an almost unchanged Ron with the help of the special surface conduction channel. Compared with the corresponding Low ΔEC HJ-FET, at the same Vth (∼ 0.82 V), the Ron is decreased from 135 Ω/mm to 90.7 Ω/mm and the maximum drain current is increased from 14.9 mA/mm to 83.1 mA/mm. By adding a top p-NiO layer for further optimization, a greatly improved power figure of merit (P-FOM) of 2.29 GW/cm2 is achieved among the E-mode HJ-FETs. These results show that the proposed High ΔEC HJ-FET with thin recessed channel is probably a better choice to achieve the high-performance E-mode lateral HJ-FET.

Novel superjunction Fin-based NiO/β-Ga2O3 HJFET with additional surface drift region channels for record-high performance

—In this paper, a novel superjunction fin-based NiO/β-Ga2O3 heterojunction field-effect transistor (SJ Fin-HJFET) is proposed and studied by simulations. Compared with the conventional Ga2O3 SJ FinFET, Ga2O3 SJ Fin-HJFET can generate surface conduction channels instead of depletion zones near the p-n junction interface in the SJ drift region. The additional surface conduction channel significantly improves the specific on-resistance of the SJ Fin-HJFET (from 1.091 mΩ cm2 to 0.397 mΩ cm2, reduced by 63.6 %) and dramatically improves the Baliga figure of merit (BFOM, form 11.75 GW/cm2 to 32.28 GW/cm2) at the same breakdown voltage (3580 V). The effect of different conduction band offset (ΔEC) on the performance of the SJ Fin-HJFET is also investigated. The simulation results show that the on-resistance advantage of the SJ Fin-HJFET applies to a wide range of ΔEC, exhibiting strong applicability and stability. These results indicate that the SJ Fin-HJFET has record-high performance and promising application prospects.

Multidimensional Deep Ultraviolet (DUV) Synapses Based on Organic/Perovskite Semiconductor Heterojunction Transistors for Antispoofing Facial Recognition Systems.

Reliably discerning real human faces from fake ones, known as antispoofing, is crucial for facial recognition systems. While neuromorphic systems offer integrated sensing-memory-processing functions, they still struggle with efficient antispoofing techniques. Here we introduce a neuromorphic facial recognition system incorporating multidimensional deep ultraviolet (DUV) optoelectronic synapses to address these challenges. To overcome the complexity and high cost of producing DUV synapses using traditional wide-bandgap semiconductors, we developed a low-temperature (≤70 °C) solution process for fabricating DUV synapses based on PEA2PbBr4/C8-BTBT heterojunction field-effect transistors. This method enables the large-scale (4-in.), uniform, and transparent production of DUV synapses. These devices respond to both DUV and visible light, showing multidimensional features. Leveraging the unique ability of the multidimensional DUV synapse (MDUVS) to discriminate real human skin from artificial materials, we have achieved robust neuromorphic facial recognition with antispoofing capability, successfully identifying genuine human faces with an accuracy exceeding 92%.

Monolithic E/D-mode P-GaN/AlGaN/GaN HFETs using reactivation annealing process

A reactivation annealing process was developed to restore the deactivated p-type characteristics of an Mg-doped p-type GaN layer subsequent to exposure to the SiNx passivation step in a p-GaN gated AlGaN/GaN heterojunction field-effect transistor (HFET). The deactivation, induced by the formation of H–Mg complexes during the passivation process, necessitates an additional activation annealing procedure. Notably, it was observed that the passivation film on the p-GaN layer must be removed through etching prior to annealing, aiming to eliminate H atoms from H–Mg complexes. The reactivation annealing process was conducted at 800 °C. Employing this reactivation approach, we successfully demonstrated monolithic enhancement- and depletion-mode p-GaN/AlGaN/GaN HFETs.

Dual-Junction Field-Effect Transistor with Ultralow Subthreshold Swing Approaching the Theoretical Limit.

Metal-oxide-semiconductor field-effect transistors as basic electronic devices of integrated circuits have been greatly developed and widely used in the past decades. However, as the thickness of the conducting channel decreases, the interface electronic scattering between the gate oxide layer and the channel significantly impacts the performance of the transistor. To address this issue, van der Waals heterojunction field-effect transistors (vdWJFETs) have been proposed using two-dimensional semiconductors, which utilize the built-in electric field at the sharp van der Waals interface to regulate the channel conductance without the need of a complex gate oxide layer. In this study, a novel dual-junction vdWJFET composed of a MoS2 channel and a Te nanosheet gate has been developed. This device achieves an ultralow subthreshold swing (SS) and an extremely low current hysteresis, greatly surpassing the single-junction vdWJFET. In the transistor, the SS decreases from 475.04 to 68.3 mV dec-1, nearly approaching the theoretical limit of 60 mV dec-1 at room temperature. The pinch-off voltage (Vp) decreases from -4.5 to -0.75 V, with a current hysteresis of ∼10 mV and a considerable field-effect mobility (μ) of 36.43 cm2 V-1 s-1. The novel dual-junction vdWJFET provides a new approach to realize a transistor with a theoretical ideal SS and a negligible current hysteresis toward low-power electronic applications.

Bias-dependent electron velocity and short-channel effect in scaling sub-100 nm InAlN/GaN HFETs

This work reports on the extraction and simulation of the electron velocity–gate voltages relationship for sub-100 nm InAlN/GaN heterojunction field-effect transistors (HFETs). A peak electron velocity (ve) at an electron density (ns) of 0.41 × 1013 cm−2 was observed at 1.06 × 107 cm/s in an InAlN/GaN HFET with 60 nm gate length (Lg) by delay time analysis. The ve at a high ns of 1.5 × 1013 cm−2 was observed at 0.6 × 107 cm/s. This peak ve behavior is explained by polarization Coulomb field (PCF) scattering and optical phonon scattering based on a Monte Carlo method. As Lg scaled from 350 to 60 nm, the current gain cutoff frequency (fT) and transconductance (gm) were improved. However, the thermal performance was degraded with a bad figure of merit P150 °C. Although a weakening of the control capability of Vgs on ns (Δns/ΔVgs) was observed in the shorter Lg device, which leads to a decrease in device gm, the larger electron velocity by the increased lateral electric field (E) and the larger Δve/ΔVgs by the increased PCF scattering still enhance the peak gm. Results indicate that the enhancement of Δve/ΔVgs is a vital method to strengthen the modulation of the gate on current and to suppress the short channel effect in GaN HFET. Our work supports a deeper understanding and analysis of sub-100 nm InAlN/GaN HFET device performance and physical mechanisms.

Reduction in density of interface traps determined by C-V analysis in III-nitride-based MOSHFET structure

An in situ metal-organic chemical vapor phase epitaxy is used to grow a complete AlGaN/GaN metal oxide semiconductor heterojunction field effect transistor (MOSHFET) structure, gated by a gallium oxide (Ga2O3) layer; we observed reduction in the interfacial trap density compared to its version wherein the Ga2O3 was grown ex situ, after breaking the vacuum, all else being the same. A remarkable decrease in the interfacial charge density for in situ MOSHFET structures in the range of 70%–88% for 10–30 nm oxide layer thickness and improvements in other electrical parameters required for high-performing devices were observed.

Normally-off recessed gate β-Ga2O3 MOSHFETs with a modulation-doped heterostructure back-barrier

This study demonstrates enhancement-mode recessed-gate β-Ga2O3 metal–oxide–semiconductor heterojunction field-effect transistors (MOSHFETs) with a combination of the MOS channel and a modulation-doped heterostructure to improve maximum drain current and on-resistance (RON). In this proposed device concept, modulation doping in the heterostructure back-barrier inserted into the MOS channel increases the electron density in the MOS channel while maintaining a normally-off operation. First, 2D simulations of enhancement-mode recessed-gate β-Ga2O3 metal–oxide–semiconductor field-effect transistors (MOSFETs) were performed in a Silvaco ATLAS TCAD environment to calibrate the transfer characteristics with the measured data of the investigated device reported previously. Second, using calibrated physical models and parameters, the transfer and transconductance characteristics, and output and off-state characteristics of the enhancement-mode recessed-gate β-Ga2O3 MOSHFETs were comprehensively investigated. The maximum drain current at VGS = 8 V and VDS = 10 V could be increased up to 32.6 mA mm−1 from 9.1 mA mm−1 with the MOSHFET in comparison with that of the recessed-gate MOSFET. The breakdown voltage increased considerably from 186 V to 226 V for the recessed-gate MOSHFET. The proposed device also showed a lower RON, which decreased from 354 Ω.mm to 214 Ω.mm owing to greater electron accumulation in the channel owing to the introduction of the modulation-doped heterostructure.

A comparative study of work function variations in III-V heterojunction and homojunction tunnel field-effect transistors

In this paper, we present a comparative study on the impact of work function variations (WFV) between the III-V heterojunction and homojunction tunnel field-effect transistors (TFETs) vis TCAD simulation. It reveals that, in general, the current variation of both devices decrease as the gate voltage increases, and the threshold voltage variations generally increase with the increase of threshold current. However, in comparison to homojunction TFET, heterojunction TFET exhibits the following two differences. 1) The current fluctuation is stronger near the device's OFF-state and weaker near the ON-state, and thus it has a stronger dependence on bias. 2) Both the threshold voltage fluctuations and its dependence on the threshold current are weaker. On the other hand, with an increase in grain size, both homojunction and heterojunction devices manifest more prominent performance fluctuations. Moreover, the dependence of these fluctuations on grain size is roughly comparable for these two device types. Finally, it is observed that 1) the significant current fluctuation at the OFF-state can be mitigated when the device's OFF-state is designed within a region with weaker gate control, and 2) the current normalized coefficient of variation parameter may be unreliable to assess the fluctuation for the case with a few “abnormal” high current values.

Polarized Coulomb field scattering in LaAlO3/SrTiO3 heterojunction field-effect transistors

LaAlO3/SrTiO3 heterojunction field-effect transistors (HFETs) were fabricated. Using a combination of measured current–voltage (I–V) output curves and gate-source capacitance–voltage (C–V) characteristic curves for the fabricated LaAlO3/SrTiO3 HFETs, and considering scattering mechanisms for longitudinal optical phonon, interface rough, electron-electron (E-E), acoustic phonon, and polarized Coulomb field (PCF), the channel electron mobility of LaAlO3/SrTiO3 HFETs has been calculated and analyzed. The results showed that PCF scattering is a significant carrier scattering mechanism in LaAlO3/SrTiO3 HFETs. The heterostructure of the LaAlO3/SrTiO3 system has strong polarization characteristics. This paper is the first to demonstrate that PCF scattering is a significant carrier scattering mechanism in LaAlO3/SrTiO3 HFETs, following GaN HFETs, thus demonstrating that LaAlO3/SrTiO3 HFETs also have PCF scattering effect.

Bidirectional rectifier with gate voltage control based on Bi2O2Se/WSe2 heterojunction

Two-dimensional (2D) WSe2 has received increasing attention due to its unique optical properties and bipolar behavior. Several WSe2-based heterojunctions exhibit bidirectional rectification characteristics, but most devices have a lower rectification ratio. In this work, the Bi2O2Se/WSe2 heterojunction prepared by us has a type Ⅱ band alignment, which can vastly suppress the channel current through the interface barrier so that the Bi2O2Se/WSe2 heterojunction device has a large rectification ratio of about 105. Meanwhile, under different gate voltage modulation, the current on/off ratio of the device changes by nearly five orders of magnitude, and the maximum current on/off ratio is expected to be achieved 106. The photocurrent measurement reveals the behavior of recombination and space charge confinement, further verifying the bidirectional rectification behavior of heterojunctions, and it also exhibits excellent performance in light response. In the future, Bi2O2Se/WSe2 heterojunction field-effect transistors have great potential to reduce the volume of integrated circuits as a bidirectional controlled switching device.

Effect of SiO2Surface Passivation on the Performance of GaN Polarization Superjunction Heterojunction Field Effect Transistors

In this article, the effects of the SiO2surface passivation layer are reported on normally‐on 1.2 kV GaN polarization superjunction (PSJ) heterojunction field effect transistors (HFETs) by comparing the electrical performances of PSJ HFETs with and without SiO2surface passivation. A slight recovery of the 2D electron gas sheet density is observed in the slight negative shift ofVthafter SiO2surface passivation. Passivation also increases the breakdown voltage. This improvement may result from removing positive surface charges in defects along the P‐GaN gate sidewall and top u‐GaN layer after the specifically designed SiO2surface passivation. Furthermore, the SiO2surface passivation can also effectively suppress the surface gate leakage currents in the PSJ HFETs by eliminating the conductive channel created by the positive surface charges in defects.

Simulation study of multi-source hetero-junction TFET-based capacitor less 1T DRAM for low power applications

A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The analysis of the three memory functions: Write, Hold and Read of 1T DRAM has been carried out using Synopsys TCAD simulations. A storage region of Ge material is used for the accumulation of holes/to store the charge carriers. The variation in length of Ge-storage region, under lap length (Lunder), and temperature is performed to analyse the DRAM performance. In the Write operation, the tunneling window reduces to 15 nm and holes can be easily stored in the Ge-storage region. In case of Hold1 and Read1 operations, the potential barriers are reduced by 0.24 eV, and 0.1 eV respectively. In the proposed multi-source TFET with 14 nm gate length, read current ratio i.e. IR1/IR0 of 4.4, retention time (RT) greater than 10 sec, and sense margin (SM) of 1.27 × 10−6 A/µm is achieved at room temperature. The proposed multi-source TFET based 1T DRAM is operating at very low gate voltages. Therefore, this device is well suited for low power applications.

Ferroelectric passivation layer derived high performance AlGaN/GaN heterojunction field-effect transistor

The density of interface states is strongly related to the performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) and is normally attributed to the degradation of the carrier mobility and gate leakage current. The density of interface states is optimized in conventional AlGaN/GaN HEMTs through the use of different passivation layers. However, different passivation layers may create more complex interface structures. In our previous work, ferroelectric polarization was used to regulate the carrier concentration in AlGaN/GaN HEMTs. Herein, we propose a ferroelectric passivation-layer-induced pure field effect modulation within the AlGaN/GaN heterojunction field-effect transistors. After positive poling, the interface trap density (Dit) decreases by 71% and current collapse is reduced. The output current (IDS) increases from 408 to 462 mA/mm and transconductance (gm) increases from 88 to 149 mS/mm. Simultaneously, the carrier mobility in the channel is also greatly improved after positive poling. When negative poling is applied, the gate leakage decreases and the breakdown voltage of the device increases by 55%. Our work provides a simple and effective way to study the density of interface states in GaN device design and optimization.

Fluorine-Based Low-Damage Selective Etching Process for E-Mode p-GaN/AlGaN/GaN HFET Fabrication

In this study, we conducted an optimization of a low-damage selective etching process utilizing inductively coupled plasma-reactive ion etch (ICP-RIE) with a fluorine-based gas mixture. This optimization was carried out for the fabrication of p-GaN gated AlGaN/GaN enhancement-mode (E-mode) heterojunction field-effect transistors (HFETs). The optimum process conditions resulted in an etch selectivity of 21:1 (=p-GaN:Al0.2Ga0.8N) with a p-GaN etch rate of 5.2 nm/min and an AlGaN etch rate of 0.25 nm/min. In comparison with an oxygen-based selective etching process, the fluorine-based selective etching process demonstrated reduced damage to the etched surface. This was confirmed through current–voltage characteristics and surface roughness inspections. The p-GaN gated AlGaN/GaN E-mode device, fabricated using the optimized fluorine-based selective etching process, achieved a high threshold voltage of 3.5 V with a specific on-resistance of 5.3 mΩ.cm2 for the device and with a gate-to-p-GaN gate distance of 3 μm, a p-GaN gate length of 4 μm, and a p-GaN gate-to-drain distance of 12 μm. The catastrophic breakdown voltage exceeded 1350 V.

Normally-off n-ZnO/p-diamond heterojunction field effect transistor with recessed gate and current distribution layer

In this paper, an n-ZnO/p-diamond heterojunction field effect transistor (HJ-FET) with recessed gate and current distribution layer is designed and optimized by using TCAD software. It demonstrates that the threshold voltage and breakdown voltage can be remarkably affected by the doping concentration and thickness of both n-ZnO and p-diamond. Additionally, the threshold voltage can be further enhanced by introducing a recessed gate due to the enhanced depletion capacity on the channel layer. Although the conduction modulation by the enhanced electric field decreases the on-resistance, the obviously decreased breakdown voltage by the recessed gate degrades the electrical performances. Finally, a current distribution layer between source and drain electrodes is added to decrease the on-resistance of diamond HJ-FET. After optimizing the parameters, the diamond HJ-FET exhibits a larger threshold voltage, a smaller on-resistance and a higher breakdown voltage.

Detection of lead ions with enhancement-mode GaN-based heterojunction field-effect transistors

Detection of lead ions with enhancement-mode GaN-based heterojunction field-effect transistors

Novel Vertical Fin-Based NiO/β-Ga2O3 Heterojunction Field-Effect Transistor with a Low Ron,sp

In this paper, a novel vertical fin-based NiO/β-Ga2O3 heterojunction field-effect transistor (Fin-HJFET) is proposed and studied by TCAD. Theoretically high conduction band offset () enables Ga2O3 Fin-HJFET to produce electron confinement effect at certain gate bias voltage. According to the simulation results, this effect makes Ga2O3 Fin-HJFET can not only form surface-conducting fin channels that are not available in conventional fin-based junction field-effect transistor (Fin-JFET) but also have a stronger electron accumulation capability than Ga2O3 vertical FinFET due to the deep potential well, which leads to a lower specific on-resistance (). In addition, Ga2O3 Fin-HJFET inherits the advantages of Ga2O3 FinFET as a vertical normally-off device and has a higher breakdown voltage compared to FinFET without field plates due to the protection of the highly doped NiO layer. Particularly, Fin-HJFET with different heterojunction band alignments are also considered and discussed. At last, the parameter influence and future optimization space of this highly promising device are explored, providing guidance for actual device fabrication and future device improvement.