Heterojunction Bipolar Transistor Process Research Articles

A fully integrated GaAs HBT power amplifier for WLAN 802.11ax applications

AbstractA fully integrated gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) power amplifier (PA) for wireless local area network 802.11ax applications is presented in this paper. The structure consists of two‐stage power cells. To satisfy the high linearity requirements of IEEE 802.11ax, we analyzed the distortion of amplitude‐to‐amplitude and amplitude‐to‐phase. Due to the thermal and voltage sensitivity of GaAs HBT, an adaptive bias circuit is designed to ensure linearity. Moreover, an efficient passive output matching network is designed by analyzing the efficiency of the passive network. The design electromagnetic structure is fabricated in a 2‐μm GaAs HBT process. Under continuous wave testing, the output power reaches 27.2 dBm and the maximum efficiency of 28% at 2.4 GHz. Under the excitation of a 40 MHz 1024‐quadratic amplitude modulation signal, the output power meeting error vector magnitude of −35 dB reaches 16.8–17.2 dBm from 2.4 to 2.5 GHz.

Design and Optimization of a Highly Linear Power Amplifier with Novel Active Bias Circuit in InGaP/GaAs HBT MMIC Technology

This paper introduces a highly linear power amplifier (PA) that utilizes a 2-μm InGaP/GaAs hetero-junction bipolar transistor (HBT) process. As communication systems evolve in complexity, the demands for the linearity and static power consumption of HBT power amplifiers are becoming more stringent. Typically, there exists a trade-off relationship between linearity and static power consumption in the design process. Hence, this paper proposes a novel active bias circuit for HBT power amplifiers, along with its layout design. The proposed active bias circuit consists of a differential pair and a current mirror structure, designed to enhance PA linearity while maintaining low quiescent current. Additionally, a novel layout structure is implemented to achieve thermal coupling between the RF transistors and the active bias, further improving PA linearity. As a result of the implementation of the proposed active bias and layout structure, the PA demonstrates high linearity in both amplitude modulation to phase modulation (AM/PM) and amplitude modulation to amplitude modulation (AM/AM) performance, while simultaneously maintaining a low quiescent current. The three-stage PA prototype achieves notable performance metrics, including a peak gain of 32.6 dB at 5.6 GHz, gain flatness of ±0.5 dB from 5.15 GHz to 5.85 GHz, and P1dB of 32.1 dBm at a quiescent emitter current of 180 mA.

Switchless Dual-Power-Mode Fully Differential HBT Power Amplifier for Mobile Applications

This study proposes a switchless dual-power-mode (DPM) power amplifier (PA), which operates independently in high-powermode (HPM) and low-power mode (LPM) to improve the efficiency. The DPM PA optimizes the output impedances using bias control of the PA and the proposed bidirectional output matching structure with a transformer (TF) for each power mode with no switches for isolation between the LPM and the HPM with high passive efficiency. The proposed output structure realizes a high impedance in the nonoperating mode network to ensure that the operating mode network realizes the optimal impedance by utilizing bidirectional matching of the off characteristics of transistors and TF output for each mode. The differential DPM PA is implemented using a 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \mathrm{m}$</tex-math> </inline-formula> InGaP/GaAs heterojunction bipolar transistor (HBT) process on a nine-layer printed circuit board with low insertion loss to demonstrate the proposed structure. The HPM and LPM, operating independently, achieved the gains of 24–25.5 and 11.4–12.9 dB and the saturated output power of 34.2–34.8 and 23.2–23.5 dBm, with a peak power-added efficiency (PAE) of 44.4%–49% and 32%–34.4%, respectively, under a continuous-wave (CW) signal test of over 5.15–5.925 GHz. The proposed PA error vector magnitude (EVM) is tested with 160 MHz of a 64-quadrature amplitude modulator (QAM) signal and achieves the average output powers of 24.5 and 14 dBm (EVM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ -$</tex-math> </inline-formula> 32 dB) and a PAE of 10.5% and 10.1% for HPM and LPM with digital predistortion, respectively.

A compact 9–23 GHzlow noise amplifier with bandwidth extension techniques in 0.18‐μmSiGe BiCMOS

AbstractIn this paper, a novel wideband low noise amplifier (LNA) operating in the 9–23 GHz frequency range is presented. The proposed LNA design utilizes a combination technique consisting of pole‐tuning technique, shunt resistive‐capacitor negative feedback, and gate‐capacitive peaking technique to achieve significant bandwidth extension while maintaining acceptable overall performance. For verification, a one‐stage triple‐stacked LNA using the combination technique is designed and implemented in a 0.18‐μm SiGe BiCMOS heterojunction bipolar transistor (HBT) process. The fabricated prototype demonstrates a peak gain of 13.8 dB at 19.5 GHz, minimum noise figure of 3.1 dB at 14 GHz, 3‐dB bandwidth of 14 GHz, and a fractional bandwidth of 87.5%, while consuming a dc power of 39.6 mW. Moreover, the chip occupies a small silicon area of 0.39 mm2including all testing pads with a core size of only 0.192 mm2.

A Physics-Based Analytical Formulation for the Tunneling Current Through the Base of Bipolar Transistors Operating at Cryogenic Temperatures

A physics-based analytical solution for the direct tunneling current through the base region of bipolar transistors operating at cryogenic temperatures (CTs) is derived. The obtained formulation is continuously differentiable over the entire bias region and contains only few experimentally determinable model parameters, which makes it well-suited for compact circuit modeling. Very good agreement of the new formulation with both a numerical evaluation of the tunneling current integral and experimental data of two silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) process generations is demonstrated.

완전집적형 임피던스 변환 다중권선 90° 커플러의 설계

In this paper, a design methodology for a fully integrated impedance-transforming multi-winding 90° coupler is proposed. The operation of the proposed coupler was verified using measurement results. These couplers were fabricated using the WIN semiconductor InGaP/GaAs heterojunction bipolar transistor (HBT) process. To provide an impedance transformation, the proposed couplers were designed with 3, 4 and 5 turn coils for 50-, 75-, and 100-Ω impedance transformations, respectively. The center frequencies of each coupler were 5.5, 3.33, and 2.47 GHz. Two copper metal layers were combined together with a via to attain a high Q factor, and its improvement was analyzed. The measurement results show that the insertion losses of the proposed couplers are less than 0.37 dB and phase imbalances are less than 2.74°.

Wideband SiGe down-converter for millimeter-wave radio astronomy applications

A Q-band down-converter module with high conversion gain (CG) is presented for a wideband radio astronomy receiver. This down-converter module is designed on a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) process (0.13 μm) to realize high CG, low LO power operation, and wideband frequency impedance matching for RF/LO/IF ports. The down-converter consists of a double-balanced Gilbert mixing core with on-chip RF/LO transformer baluns, an IF buffer, and bandpass filter. The performance of the down converter is largely dependent on the passive components and signal line interconnection. The design of all passive structures is analyzed and optimized with FEM simulations for a high-quality factor to minimize losses and parasitic effects. This module achieves 8 dB of CG at a low LO power of −6 dBm over a wide RF bandwidth from 28 to 56 GHz and IF bandwidth from 6 to 18 GHz. It demonstrates LO-to-IF/LO-to-RF/RF-to-IF isolations > dB / 40 dB/35 dB, respectively. The critical FEM simulation is described in the design of this high-density SiGe HBT RF circuit. The measured performance confirms the simulation results. The module meets the original design requirements of the DVA-2 Q-band receiver.

K-Band Digital Power Amplifier Based on InP DHBT

Based on 0.7-μm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) process, this paper designs a digital power amplifier (DPA) monolithic microwave integrated circuit. Digital-to-analog converter (DAC), modulation and power amplifier are integrated into the DPA, reducing losses and improving linearity of traditional radio frequency (RF) links. The test results show that the DPA can achieve an output power of 23-23.5 dBm and power added efficiency (PAE) of 21.5-23% within 19.2-21.2 GHz. And the mean squared error of normalized output voltage is 0.0158 at 20 GHz. Then, asymmetrical synthesis technology is used to improve the efficiency of DPA in non-full amplitude state. Simulation results of DPA demonstrate saturated output power of 23.5 dBm and the maximum PAE of 21.9% in 19-21 GHz. At 20 GHz, the PAE between full and half amplitude state is greater than 20%.

A temperature‐compensated linear GaAs HBT power amplifier for small‐cell applications in −25 to 125∘C$^\circ \rm C$ lunar environment

A two-stage 920–960 MHz power amplifier (PA) in GaAs heterojunction bipolar transistor (HBT) process is demonstrated for small-cell communications in the lunar environment. To cope with the temperature fluctuations during lunar days, a novel complementary to absolute temperature (CTAT) biasing scheme is proposed for the PA to achieve an ultra-wide-range temperature compensation. Moreover, to meet the linearity requirements of the small-cell applications while producing high output power, a band-stop filter is employed in the biasing circuit of the second stage to reduce the AM– AM distortions. Over the temperature range of −25 to 125°C, the PA is capable of operating for the small-cell applications over a gain ranging from 30.2 to 32.8 dB. The proposed PA achieves 24.5 dBm linear power with −47 dBc adjacent channel leakage ratio (ACLR) and a PAE of 15%.

A Multi-Source Co-Simulation Method for the Thermal Stability of GaAs Sub-6G Power Amplifier with Adjustable Bias Current

In this paper, the thermal stability of GaAs heterojunction bipolar transistor (HBT) power amplifier (PA) in a sub-6G band has been improved by a multi-source co-simulation method. To reduce the parameter errors caused by the variations of thermal resistances, a co-simulation method for the multiple heat sources of fully-integrated PA is proposed. Specifically, an adjustable bias circuit is applied on the PA for temperature compensation using a zero-to-absolute-temperature (ZTAT) current. To verify the proposed method, a sub-6G PA is realized in the GaAs HBT process. The experimental results show that the variations in power added efficiency and output power is stabilized due to the 3.5% error ZTAT current. The errors between simulation and measurement are reduced from 6% to 1%. According to the thermal factor defined in co-simulation, the working temperature decreases 10 °C, while the area only increases 27%. The above results prove that that thermal stability and the simulation reliability can be co-designed with the minimal area cost.

A fully integrated GaAs HBT power amplifier with enhanced efficiency for 5-GHz WLAN applications

An efficiency-enhanced fully integrated power amplifier (PA) for wireless local area networks (WLANs) was implemented based on the GaAs heterojunction bipolar transistor (HBT) process. A harmonic tuning network that can absorb the parasitic inductance of the bonding wires is proposed, which reduces the chip area significantly. The network provides nearly optimum fundamental and second harmonic impedances from 5.0 to 5.5 GHz. Additionally, a novel adaptive bias circuit that corrects the AM-AM and AM-PM distortion and improve thermal stability at high input power was proposed. With a chip dimension of only 1.06 mm2, the PA achieves a gain of 31.1-31.6 dB and saturated power of 29.9-30.3 dBm with a peak power-added efficiency (PAE) of 49.3%-51.8% across 5.0-5.5 GHz. The PA also shows an output power of 22.1 dBm (EVM=-32 dB) with 18.4% PAE under an 802.11ac MCS9 VHT160 test signal. In addition, the PA delivers 17.5 dBm (EVM=-42 dB) output power when tested with the 802.11ax MCS11 VHT160 signal at 5.25 GHz.

General Approach to the Calibration of Innovative MFP Multichannel Digitizers

Innovative digitizers exploiting mixing, filtering, and processing (MFP) operations can grant ultrahigh bandwidth and sampling rate. Their operation combines analog processing stages with a digital signal processing stage, where massive operations are performed to obtain the digital representation of the input signal. In fact, the samples returned by the analog-to-digital converter (ADC) consist of a transformed, namely, mixed and filtered, version of the input, which shall be processed in the digital domain to reconstruct the input signal. The digital processing is also designed to attain streamline calibration, which provides both the removal of nonideal effects, such as mismatches between individual channels, and the improvement of the frequency response flatness. Calibration strategies represent an asset of manufacturers’ know-how since the performance of the digitizer largely depends on the effectiveness of the calibration process. Gain equalization and aliasing removal are performed in the digital domain by finite impulse response (FIR) filtering of the ADCs’ outputs. A general method for the identification of the calibration filters, and their translation into algorithms for MFP digitizers using two, four, or any number of channels, is proposed here. Functional- and circuit-level Cadence Virtuoso simulations in an STMicroelectronics Si–Ge heterojunction bipolar transistor (HBT) process are also carried out to evaluate the performance of the proposed method through a comparison between the digital representations of the signals obtained with and without calibration.

Integrated Low Noise Amplifier with Capacitive Shunt Feedback Impedance Matching for Radio Astronomy

The noise performance of integrated low noise amplifiers (LNAs) is impaired by on-chip inductors owing to their low-quality factor, especially when inductors are used in the signal path at the input, such as for the inductively degenerated common-emitter amplifier. The inductively degenerated common-emitter configuration is largely used in LNA design, owing mainly to its ability to achieve impedance and noise matching simultaneously. This paper proposes an LNA configuration that achieves impedance matching and noise matching simultaneously without an inductor in the input signal path, owing to capacitive feedback and transistor sizing. Only the resistive component of the optimum noise resistance is matched to the source resistance. The impact of the mismatch due to the reactive component to the noise figure is reduced by the ratio G s /R n . A technique initially developed for the broadband matching of a single-layer microstrip patch antenna is used for the output matching network. Using a 130 nm silicon–germanium heterojunction bipolar transistor process, simulation results indicate a noise figure of 2.3 dB, a gain of 26 dB and S 11 and S 22 that are better than −12 dB at 1.42 GHz. This frequency corresponds to the 21 cm hydrogen line. This novel multi-stage LNA can be used for the detection of electromagnetic radiation from neutral hydrogen atoms from space in radio astronomy and the proposed design methodology can be generalized to LNAs.

A Wideband Gain-Enhancement Technique for Distributed Amplifiers

In this article, a new bandpass distributed amplifier (DA) using a wideband gain-boosting technique is presented. In particular, a feedback network, including a series inductor and a shunt capacitor, is used to generate two peaks at the lower and upper cutoff frequencies of the amplifier's bandpass response. This technique provides a gain enhancement over a wide bandwidth without sacrificing the upper cutoff frequency. A detailed analysis of the two frequencies peaking effect is carried out to support the theory. To verify the concept, a conventional and a gain-enhanced DA are fabricated in an indium-phosphide (InP) heterojunction bipolar transistor (HBT) process. The gainenhanced DA exhibits a measured gain of 10.5 dB with a 4-dB gain improvement compared with the conventional one, covering a 3-dB bandwidth from 60 to 145 GHz. The maximum saturated (Psat) is 20.9 dBm at 75 GHz with the measured 1-dB compression power (P1dB) of 18.5 dBm. The dc power consumption is 440 mW, and the chip size is 1.6 mm × 0.6 mm. To the best of our knowledge, the proposed DA achieves the highest gain boosting over a broad bandwidth compared with the published works.

A 4.2-to-5.4 GHz stacked GaAs HBT power amplifier for C-band applications

PurposePower amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications.Design/methodology/approachA common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks.FindingsBy using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz.Originality/valueThe technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

A 1–160-GHz InP Distributed Amplifier Using 3-D Interdigital Capacitors

A wideband monolithic microwave/millimeter-wave integrated circuit (MMIC) distributed amplifier (DA) using a 3-D interdigital capacitor at the input of the gain cell is demonstrated in an indium phosphide (InP) heterojunction bipolar transistor (HBT) process. The proposed DA using interdigital capacitors improves the input return loss at high frequencies compared with the one implemented with conventional metal–insulator–metal (MIM) capacitors. The fabricated amplifier achieves a measured average gain of 10.5 dB over a 3-dB bandwidth from 1 to 160 GHz. The maximum measured saturated power ( $P_{\mathrm {sat}}$ ) is 17.8 dBm with the corresponding 1-dB compression power ( $P_{\mathrm {1\,dB}}$ ) of 15 dBm at 55 GHz. The amplifier achieves a minimum $P_{\mathrm {sat}}$ of 14.6 dBm up to 110 GHz.

Methodology of Noise Flatness Based on Network Quality Factor in RF Wideband Applications

A noise optimization method for millimeter-wave RF wideband applications is reported. Intrinsic noise laws in wideband RF systems are discovered, and a noise flatness methodology based on a network quality factor algorithm is proposed. This algorithm aims to reduce the total noise in an RF system and increase the noise flatness over a full operating band. An RF wideband front end is investigated to verify the noise optimization theory and maintain circuit performance. Using noise flatness methodology and a SiGe heterojunction bipolar transistor process featuring a fT/fmax of 240/280 GHz, the front-end results show good performance and compliance with the proposed method.

Broadband InGaP/GaAs HBT Power Amplifier Integrated Circuit Using Cascode Structure and Optimized Shunt Inductor

This article presents a broadband two-stage cascode power amplifier integrated circuit (PAIC) using a 2- $\mu \text{m}$ InGaP/GaAs heterojunction bipolar transistor process. Since higher supply voltage of cascode power amplifier (PA) results in lower impedance transformation ratio of the matching network due to lower current, cascode PAs generally have broader bandwidth than common-emitter (CE) PAs. However, bandwidth analysis for handset PAs with a single-section load matching network, including transistors output capacitance, revealed that cascode PAs had bandwidth similar to CE PAs. Through bandwidth analysis based on power and efficiency contours at the internal plane of the transistor, an optimized shunt inductor with a single-section load matching network was proposed in this article to increase the bandwidth of cascode PA. Performances of both cascode and CE PAs with and without the optimized shunt inductor were compared. A broadband two-stage cascode PAIC with a compensating shunt inductor and an L-section matching network was designed and implemented. The implemented PAIC exhibited an output power of at least 30.1 dBm at frequency band ranging from 1.55 to 2.65 GHz for continuous-wave excitation. Using a long-term evolution signal with a peak-to-average power ratio of 7.5 dB and a signal bandwidth of 10 MHz, a power gain of more than 23.7 dB, power-added efficiency of 30.9% to 38.4%, and average output power of 26.7 to 27.7 dBm were obtained at a given adjacent channel leakage power ratio of −30 dBc. A fractional bandwidth was calculated to be 54.3% based on measured results.

Efficient active multiplier‐based signal source for &gt;300 GHz system applications

This Letter presents a 300 GHz signal source, realised using an 800 nm transferred-substrate InP double heterojunction bipolar transistor process. The source is based on an active frequency tripler. It delivers −1.6 dBm peak output power at 306 GHz. The DC consumption is only 36 mW, which corresponds to 2% conversion efficiency. The measured tripler achieves more than 30 GHz bandwidth and exhibits very low unwanted harmonics. The chip area of the source is only 0.94 × 0.84 mm2.

A low phase noise InGaP–GaAs HBT Colpitts VCO with a high quality differential inductor

A balanced Colpitts voltage controlled oscillator (VCO) topology with its two implementations in a GaAs heterojunction bipolar transistor (HBT) process is introduced in this paper. A detailed analysis of phase noise, originating from the work by Hajimiri and Lee, is given, which depicts a specific outline of the phase noise generation mechanisms in GaAs HBT based harmonic oscillators including LC cross coupled/Colpitts/class C VCOs. In addition, phase noise expressions for HBT based VCOs are derived, compared and act as an optimization tool in oscillator designs. The theoretical analysis of phase noise is authenticated with two balanced Colpitts VCOs with their respective center oscillation frequencies of 850 MHz and 1670 MHz, which are fabricated in a 2 µm GaAs HBT H20HL process. Measurement results show a phase noise of − 139 dBc/Hz at 1 MHz offset from an 850 MHz carrier and a phase noise of − 134 dBc/Hz or less at 1 MHz offset from a 1700 MHz carrier. The output power variation is less than 0.5 dBm over the tuning range. A relatively good match between numerical simulation and measurements is observed.