Heterojunction Bipolar Transistors Devices Research Articles

An Accurate Electro-Thermal Coupling Model of a GaAs HBT Device under Floating Heat Source Disturbances.

Taking into consideration the inaccurate temperature predictions in traditional thermal models of power devices, we undertook a study on the temperature rise characteristics of heterojunction bipolar transistors (HBTs) with a two-dimensional cross-sectional structure including a sub-collector region. We developed a current-adjusted polynomial electro-thermal coupling model based on investigating floating heat sources. This model was developed using precise simulation data acquired from SILVACO (Santa Clara, CA, USA). Additionally, we utilized COMSOL software (version 5.6) to simulate the temperature distribution within parallel power cells, examining further impacts resulting from thermal coupling. The research findings indicate that the rise in current induces modifications in the local carrier concentration, thereby prompting variations in the local electric field, including changes in the heat source's peak location and intensity. The device's peak temperature exhibits a non-linear trend regulated by the current, revealing an error margin of less than 1.5% in the proposed current-corrected model. At higher current levels, the drift of the heat source leads to an increase in the heat dissipation path and reduces the coupling strength between parallel devices. Experiments were performed on 64 GaAs (gallium arsenide) HBT-based power cells using a QFI infrared imaging system. Compared to the traditional temperature calculation model, the proposed model increased the accuracy by 6.84%, allowing for more precise predictions of transistor peak temperatures in high-power applications.

RF Characterization of GaAs HBT under Load Mismatch with Reverse Wave Injection Technique.

RF PAs need to be reliable enough to protect them from damage under load mismatch conditions. This paper investigated the characteristics of GaAs heterojunction bipolar transistors (HBTs) under load mismatch conditions using a novel reverse wave injection technique to realize large VSWR ruggedness measurement with the circle centered at 50 Ohm and optimal impedance separately to analyze the device in real applications. With a real-time waveform measurement system, the RF voltage and current waveform information can be acquired, which provide a more-accurate view of what is occurring at the current generator plane of the HBT device. Thereby, the potential failure mechanisms and load impedance can be identified to design the most-suitable PA circuits in communication systems.

An Aging Small-Signal Model for Degradation Prediction of Microwave Heterojunction Bipolar Transistor S-Parameters Based on Prior Knowledge Neural Network.

In this paper, an aging small-signal model for degradation prediction of microwave heterojunction bipolar transistor (HBT) S-parameters based on prior knowledge neural networks (PKNNs) is explored. A dual-extreme learning machine (D-ELM) structure with an adaptive genetic algorithm (AGA) optimization process is used to simulate the fresh S-parameters of InP HBT devices and the degradation of S-parameters after accelerated aging, respectively. In addition to the reliability parametric inputs of the original aging problem, the S-parameter degradation trend obtained from the aging small-signal equivalent circuit is used as additional information to inject into the D-ELM structure. Good agreement was achieved between measured and predicted results of the degradation of S-parameters within a frequency range of 0.1 to 40 GHz.

(Invited) Integration of InP Heterojunction Bipolar Transistors on Silicon Substrates for 6G Networks

The fast expansion of the global datasphere creates a huge demand on the future wireless communication technologies. Although 5G, the 5th generation of the cellular network technology, is still being rolled out, the potential of 6G is already intensively explored. The vision of 6G implies not only massive connectivity and higher data rate (up to 100 Gb/s and more) in ultra-reliable low-latency communication, but machine-to-machine interaction will dominate over those involving humans. AI (artificial intelligence) and machine learning will be omnipresent.6G network will address a frequency spectrum beyond 100 GHz, which provides wider bandwidths and, therefore, potentially simpler modulation schemes and eventually lower power consumption. However, a clear disadvantage of these mm-waves or sub-THz frequencies are the atmospheric absorption and blockage effect by physical obstacles or rain. These challenges must be tackled by a sufficiently high transceiver device density per area together with advanced beam steering and AI empowered networks.The power amplifier (PA) is one of the most critical components of the RF front-end module. Here, InP based heterojunction bipolar transistors (HBT) clearly outperform PAs based on CMOS or SiGe BiCMOS concerning saturated output power, energy efficiency and breakdown voltage. However, the limiting downside of InP HBTs is the missing cost-efficient and scalable fabrication, which hampers its adoption in high-volume 6G applications. In this paper we review various InP HBT fabrication concepts with the aim of lowering the production costs and maintaining high device performance.The best HBT device performance is demonstrated for the lattice-matched deposition on native small-diameter (≤ 150 mm) InP substrates due to perfect III-V crystal quality. Although device fabrication on these wafers cannot profit from the advanced tool park available in 200/300 mm fabs, the main drawbacks are the high cost and brittleness of InP substrates. Realizing InP HBTs on Si substrates allows to benefit from their robustness, low cost, and the access to a mature device fabrication on large-diameter wafers.In wafer reconstitution, numerous diced InP wafer tiles, which already contain the grown HBT layer stack, are bonded to a Si carrier to populate the wafer surface. After planarization, the reconstructed Si wafer can be further fabricated in a CMOS compatible 200/300 mm fab. In transfer printing a comparable approach is followed while only the active device stack is transferred to the Si carrier. Transferring only a thin InP layer to the Si carrier, which serves as a starting surface for the HBT deposition, leads to a so-called engineered substrate. Compared to the previous transfer methods, the III-V device deposition is carried out after bonding. The key advantage of all these heterogenous integration concepts is the access to a CMOS compatible and scalable device fabrication while maintaining the high III-V crystal quality. Nevertheless, the HBT production costs can only be significantly reduced with a certain re-usability of the InP substrates.The monolithic deposition directly on Si substrates would be the most cost-efficient integration approach. Unfortunately, the mismatch in lattice constant and thermal expansion coefficient between Si and III-V materials leads to the formation of relaxation defects, which degrade the HBT device performance. The growth of thick strain relaxation buffers allows to reduce the defect density in the device layers but bears new challenges such as wafer warpage or III-V crack formation.Nano-ridge engineering (NRE) is based on selective area growth (SAG) applying trench-patterned Si wafers. The III-V deposition starts inside very narrow trenches to achieve efficient aspect ratio trapping (ART) of misfit defects. After the trench is filled with III-V material, the growth is continued to engineer a broad and pristine nano-ridge (NR) which holds the device stack. A second oxide pattern prevents sidewall deposition around the NRs during the deposition of the HBT heterolayers.In the first part of this paper, pros, and cons of the most common InP HBT integration scenarios as summarized in figure will be compared in detail. Among all concepts, NRE holds the potential of being the most cost-efficient integration approach due to SAG in line with very limited III-V material deposition. However, the key open question is what NR crystal quality, and hence, device performance can be realized. This question will be addressed in the second part of the paper, reporting about the latest developments at imec. Figure 1

Burn-in effect in InGaP/GaAs HBT with intrinsically or extrinsically carbon doped base layer

InGaP/GaAs heterojunction bipolar transistors (HBTs) with intrinsically or extrinsically carbon doped base layers were grown by metal-organic chemical vapor deposition. Burn-in effect and the influence of thermal annealing at different temperatures on these devices were investigated. Results show that the intrinsically-carbon-doped HBTs demonstrate a higher current gain of 155 and a burn-in value of 24.0%, while the extrinsically-carbon-doped HBTs show a current gain of 92 and a burn-in value of 5.3%. Thermal annealing after exposing the base layer decreases the burn-in value from 24.0% to 5.7% and from 5.3% to 1.3% for intrinsically and extrinsically carbon doped HBTs, respectively, proved to be an effective method to eliminate the burn-in effect of HBT devices by hydrogen out diffusion. However, it also damages the base layer quality, leading to increased base recombination current and decreased current gain.

Parasitic parameters extraction of InP HBT only from S-parameters measured under cut-off and normal bias conditions

An improved parasitic parameters extraction method for InP heterojunction bipolar transistor (HBT) is developed. The difference between this method and previous methods is that all parasitic parameters can be extracted by relying only on the S-parameters measured under the cut-off and normal bias conditions. All the capacitance parameters in the equivalent circuit at the low-frequency cut-off can be extracted by combining the analytical closed formulas and the parameter scanning method. The intrinsic resistance Rbi is obtained indirectly by extracting the extrinsic resistance Re based on the Z-parameter method in the normal bias conditions. By de-embedding the parasitic capacitances, all the values of parasitic inductances and extrinsic resistances are obtained by the direct extraction method under the cut-off condition. The proposed method not only eliminates the critical measurement of the open-collector condition, but also greatly improves the efficiency and accuracy of parameter optimization. For different sizes and bias conditions of InP HBT devices, the excellent agreement between simulated and measured results is verified all over the frequency range of 0.4–50 GHz.

TRANSIT TIME MODEL ANALYSIS THROUGH THE BASIS IN THE CASE OF DRIFT TRANSISTORS HBT

The manufacturing technology for heterojunction bipolar transistor (HBT) is different from the one used for bipolar silicon junction transistor (BJT). The base in case of BJT is manufactured by using diffusion and the diffusion laws determine a Gaussian type of profile in the base. HBT devices are manufactured using molecular epitaxy which gives a contact doping profile. In case of HBT, producing an internal field by using uniform doping is no more possible. This is the reason why was used in the gradation of the molar composition. The Analysis using Octave soft was made for the transit time through the base of the drift HBT transistors type GaAs/AlxGa1-xAs.

A Compact Macromodeling Method for Characterizing Large-signal DC and AC Performance of InP and GaAs HBTs

In this paper, a compact macromodeling method for characterizing the large-signal characteristics of heterojunction bipolar transistors (HBTs) is proposed and successfully applied to describe the DC and AC performance of InP and GaAs HBT devices. Using the Symbolically-defined Device (SDD) technology, an empirical macro circuit preserving the Spice Gummel-Poon (SGP) intrinsic network and a simplified thermal network is established. The empirical current and charge functions are embedded in the SDD macro circuit network module. Compared with other large-signal models, the proposed model description and the relevant parameter extraction are relatively simpler, and at the same time, this method can maintain high fitting accuracy. To assess the validity and the accuracy of the proposed model, the compact large-signal model is constructed for 1 ㎛ InP HBT and 1 ㎛ GaAs HBT. Based on the complete extraction of the model parameters, excellent consistency is obtained between the measured and modeled results.

Monolithic Integration of Nano-Ridge Engineered InGaP/GaAs HBTs on 300 mm Si Substrate.

Nano-ridge engineering (NRE) is a novel method to monolithically integrate III–V devices on a 300 mm Si platform. In this work, NRE is applied to InGaP/GaAs heterojunction bipolar transistors (HBTs), enabling hybrid III-V/CMOS technology for RF applications. The NRE HBT stacks were grown by metal-organic vapor-phase epitaxy on 300 mm Si (001) wafers with a double trench-patterned oxide template, in an industrial deposition chamber. Aspect ratio trapping in the narrow bottom part of a trench results in a threading dislocation density below 106∙cm−2 in the device layers in the wide upper part of that trench. NRE is used to create larger area NRs with a flat (001) surface, suitable for HBT device fabrication. Transmission electron microscopy inspection of the HBT stacks revealed restricted twin formation after the InGaP emitter layer contacts the oxide sidewall. Several structures, with varying InGaP growth conditions, were made, to further study this phenomenon. HBT devices—consisting of several nano-ridges in parallel—were processed for DC and RF characterization. A maximum DC gain of 112 was obtained and a cut-off frequency ft of ~17 GHz was achieved. These results show the potential of NRE III–V devices for hybrid III–V/CMOS technology for emerging RF applications.

A direct extraction method to determine the extrinsic resistances for an InP HBT device based on S-parameter measurement up to 110GHz

A direct extraction method to determine the small-signal equivalent circuit model for III–V compound heterojunction bipolar transistor device is proposed in this paper. The advantage of this method is that the extrinsic resistances can be determined directly from a cut-off S-parameters measurement at the millimetre-wave frequencies (30–110 GHz) based on the T-π transformation method. After de-embedding the extrinsic elements, all intrinsic elements of the π-type model can be obtained utilizing a set of closed-form expressions. Good agreement between modeled and measured data is achieved up to 110 GHz to verify the accuracy.

(Invited) High-Performance GaN Hbts with Regrown Emitters

GaN-based hetero-junction bipolar transistors (HBTs) are suitable for power amplifiers because they have inherent advantages such as high current and power density, high linearity and normally off operation. However, low conductivity in the p-type base layer and plasma-induced dry-etching damage slow down the improvement of GaN HBTs. Although GaN-based HBTs demonstrated large current gain (β) and high current and power density by using p-type InGaN base [1], N2-incorporation dry-etching process, wet repairing and regrown base contact layer [2,3], etching damage also exists, which limits the maximum oscillation frequency (fmax) [4]. This essay reports an AlGaN/GaN heterojunction bipolar transistor (HBT) on sapphire with selective-area regrown (SAG) n-AlGaN emitter by metal-organic chemical vapor deposition (MOCVD). 1-μm n+-GaN, 0.5-μm undoped-GaN and 100-nm p-GaN are grown on sapphire in sequence by MOCVD. Then a 100-nm thick SiO2 mask layer is deposited on the wafer and patterned for SAG emitter. Then the wafer is reloaded to reactor to grow an n-AlGaN emitter layer at 980 ℃ and 50 torr. Hall measurements performed on p-GaN base layer indicate a hole concentration of 9.8×1017 /cm3 and mobility of 14.1 cm2/V.s. The SAG n-AlGaN emitter is 100-nm thick with the Al component of 7%. The electron concentration and mobility of the SAG n-AlGaN layer are 1.6×1018 /cm3 and 290 cm2/V s. Ohmic contact is achieved on the base contact with the calculated sheet resistance Rs of 238 KΩ/sq, and the specific contact resistance ρc of 2×10-3 Ω.cm2. As a result, the fabricated HBTs exhibit high β of 110, which is highest among reported values on GaN-based HBTs on sapphire substrates. The common-emitter I-V characteristics show a high J C of 22 kA/cm2 and power density of 220 kW/cm2 with a low Voffset <1V and Vknee<5V. These voltage are the lowest among reported values on GaN-based HBTs with comparable emitter areas, owing to the realization of base ohmic contact that decreases base resistance. The open-base breakdown voltage is 98 V with the leakage current of 1 μA, as a consequence the breakdown field is about 2.2 MV/cm. we also demonstrated RF performance of GaN HBTs with fT of 4 GHz at the collector voltage of 9 V, although the chip size is large. It is expected that high RF performance can be achieved by down scaling the device layout. These results for GaN HBTs/sapphire show that high performance III-N HBTs can be achieved with regrowth technology. In this talk, we will demonstrate that a large performance improvement can be obtained for RF HBT devices by the use of regrowth emitter. The current gain is increased with the emitter area decreasing. It is favorable for RF HBT devices, which are expected to achieve higher current gain, benefiting from small recombination current. By down scaling the device layout, an RF HBT is expected to be used in PA in the next generation communication.

Mixed-Mode Stress in Silicon–Germanium Heterostructure Bipolar Transistors: Insights From Experiments and Simulations

Recently, a wide class of market segments (e.g., health, material science, security, and communications) is tackled by circuits fabricated in BiCMOS technology, integrating silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) and passives. Currently, the reliability of SiGe HBT devices is a major concern, and much attention is given to self-heating (SH), that limits device performance and regulates their degradation during stress. Moreover, its relevance is supposed to increase with device scaling. In this paper, we explore the reliability issues of SiGe HBTs by combining dedicated experiments and TCAD simulations. We develop and calibrate a TCAD model that is then used to investigate SH effects in both operating and stress conditions. Results show the important role played by the back-end-of-line (BEOL) and by the substrate thermal resistance in dissipating the heat generated by impact ionization. The location at which defects are generated during stress and the microscopic properties of the defects are determined experimentally by means of dedicated noise measurements. Including defects in the TCAD model allows reproducing the degradation observed in stress experiments. Simulations of the SH effects on a stressed device in measurement conditions revealed the presence of a hole hot spot that suggests a possible physical mechanism involved in the degradation slowdown at long stress times reported in the literature.

AlGaN/GaN Heterojunction Bipolar Transistor With Selective-Area Grown Emitter and Improved Base Contact

We report AlGaN/GaN n-p-n heterojunction bipolar transistors (HBTs) on sapphire substrates with selective-area grown AlGaN emitters by metal–organic chemical vapor deposition. Metal–semiconductor contact on the external p-GaN base layer shows ohmic characteristics thanks to the dry-etching-free process of base–emitter junction. As a result, the maximum current gain $\beta $ is around 90 calculated from the Gummel plot of a ${20}\times {20}\,\,\mu \text{m}^{{2}}$ HBT device. Common-emitter ${I}$ – ${V}$ family curves exhibit offset voltage $({V} _{\text {offset}}) V and knee voltage $({V} _{\text {knee}}) V. A high current density $ {J}_{\text C}$ of 8 kA/cm2 and power density of 75 kW/cm2 were obtained. These values are the highest in the reported for GaN-based HBTs on sapphire substrates. The open-base breakdown voltage ( ${BV}_{\text {CEO}}$ ) exceeds 98 V comparable with direct-growth GaN-based HBTs.

An approach to determine cutoff frequency and maximum oscillation frequency of common emitter heterojunction bipolar transistor

AbstractAnalytical expressions for the short‐circuit current gain and unilateral power gain of common emitter heterojunction bipolar transistor (HBT) are presented in this paper. These expressions are derived from a simplified π‐type small signal equivalent circuit model, which takes into account the influence of the extrinsic resistances and base‐collector capacitance distributed nature. Good agreement is obtained between measured and calculated results for both two indium phosphide (InP) HBT devices and a gallium arsenide (GaAs) HBT device over a wide range of bias points.

Design and analysis of the dynamic frequency divider using the BiCMOS–NDR chaos-based circuit

A dynamic frequency divider using a negative-differential-resistance (NDR) circuit combined with an inductor and a capacitor was demonstrated. This NDR circuit was made of Si-based metal-oxide-semiconductor field-effect transistor (MOS) and SiGe-based heterojunction bipolar transistor devices. The operation of this frequency divider circuit was based on the long-period behavior of the nonlinear NDR circuit generating chaos phenomena. This circuit was analyzed by numerical simulation and the results showed that different dividing ratio could be obtained by modulating the input signal frequency using the MATLAB program and the HSPICE program. Some measured results were shown to verify our analyses. This application was designed based on a standard 0.18 μm BiCMOS technique.

InP HBT Technologies for THz Integrated Circuits

Highly scaled indium phosphide (InP) heterojunction bipolar transistor (HBT) technologies have been demonstrated with maximum frequencies of oscillation ( $f_{\max}$ ) of >1 THz and circuit operation has been extended into the lower end of the terahertz (THz) frequency band. InP HBTs offer high radio-frequency (RF) output power density, millivolt (mV) threshold uniformity, and high levels of integration. Integration with multilevel thin-film wiring permits the realization of compact and complex THz monolithic integrated circuits (TMICs). Circuit results reported from InP HBT technologies include: 200-mW power amplifiers at 210 GHz, 670-GHz amplifiers and fundamental oscillators, and fully integrated 600-GHz transmitter circuits. We review the state of the art in THz-capable InP HBT devices and integrated circuit (IC) technologies. Challenges in extending transistor bandwidth and in circuit design at THz frequencies will also be addressed.

Silicon Millimeter-Wave, Terahertz, and High-Speed Fiber-Optic Device and Benchmark Circuit Scaling Through the 2030 ITRS Horizon

This paper reviews the technology requirements of future 100–300-GHz millimeter-wave (mm-wave) systems-on-chip (SOI) for high data rate wireless and sensor applications, as well as for 100–300-GBaud fiber-optic communication systems. Measurements of state-of-the-art silicon metal–oxide–semiconductor field-effect transistors (MOSFETs), SiGe heterojunction bipolar transistors (HBTs), and of a variety of HBT-HBT and MOS-HBT cascodes are presented from dc to 325 GHz. The challenges facing mm-wave MOSFET and SiGe HBT device and benchmark circuit scaling toward 2–3-nm gate length and beyond 2-THz transistor $f{\mathrm {MAX}}$ are discussed for the first time based on technology computer-aided design (TCAD) and atomistic simulations. Finally, simulations of the scaling of the SiGe HBT analog and mixed-signal mm-wave benchmark circuit performance across future technology nodes predict that PAs with 45% power added efficiency (PAE) at 220 GHz, track and hold amplifiers (THAs) with over 140-GHz bandwidth, and transimpedance amplifiers (TIAs) with 250-GHz bandwidth and less than 5-dB noise figure will become feasible by 2030. Comparison of simulations and measurements for representative benchmark circuits such as TIAs, THAs, linear modulator drivers, digital-to-analog converters (DACs), and power amplifiers (PAs), fabricated in advanced SiGe BiCMOS and nanoscale SOI complementary metal–oxide–semiconductor (CMOS) technologies, and operating at 120 Gb/s and above 100 GHz, respectively, are presented to support the credibility of the benchmark circuit scaling exercise.

Impact of Lateral Scaling on Silicon Germanium High Breakdown Power Amplifier Device Performance

Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) in Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technologies have in recent years, emerged as a viable alternative to Gallium Arsenide (GaAs) [1] for commercial development of linear power amplifier (PA) modules for wireless communications. The explosion in WLAN applications at 2.4GHz has provided ample opportunity for SiGe BiCMOS to substantially penetrate the PA market [2]. SiGe HBTs offer several benefits compared to it’s GaAs HBT counterparts including the ability to provide high integration at a reduced cost [3]. The higher thermal conductivity associated with the silicon substrate enables reduced chip areas, smaller packages and provides improvements in chip robustness. Additionally, SiGe BiCMOS integration facilitates improved power densities, on-chip matching and bias chokes, temperature compensated power detector and a CMOS compatible interface [2]. SiGe HBT PA device design limits have traditionally been constrained by the performance tradeoff described by the Johnson limit, which states that the product of the current gain, fT and the DC open-base breakdown voltage, BVceo, should be relatively constant[3]. However, it is now generally accepted that DC emitter-open breakdown voltage, BVcbo is a more useful indicator of device ruggedness for PA applications. This arises since SiGe HBT operation in PA applications have been demonstrated at voltages significantly higher than BVceo, [1,4]. Furthermore, power-gain cut-off frequency, fMAX , has also been cited as relevant a device metric for PAs as fT , [1,3] and several authors have suggested that improvements in fMAX will enhance PA device performance. Typically, improvements in device fMAX are achieved by lateral scaling to accomplish a reduction in the base resistance and collector-base capacitance. Since SiGe HBT device physics do not demand rigid tradeoff between BVcbo and fMAX, , several potential device optimization opportunities exist for PA applications. Technology computer-aided design (TCAD) has been used to optimize the PA design performance relative to the base technology. The TCAD methodology was based on a detailed strategy which entailed developing a process and device model calibration for an existing 0.35um SiGe HBT device that features non-self-aligned emitter-base integration, with a carbon doped SiGe base layer and an implanted extrinsic base region [2]. The model calibration featured a close match of both process and electrical characteristics to the measured data. An important element to matching the electrical characteristics of the device, was simulating key artifacts of the process related to epitaxial growth of the SiGe base layer, which defined the final device topology. The calibration served as the baseline simulation for the optimization study and provided insight into the device performance limitations. The simulations demonstrated the device breakdown, BVcbo, occurs along the extrinsic region of the collector and the base, and is correspondingly set by the thickness of the collector n-epitaxial layer and the vertical diffusion of the extrinsic base into the collector. Several lateral scaling strategies were therefore investigated, which addressed optimization of collector-base capacitance, Ccb and base resistance, Rb for improvements in fMAX and BVcbo. Scaling the lateral dimension of the device resulted in improvements in the performance metrics peak fT , peak Ic and fMAX . Improvements in fT and Ic are explained by the reduced surface field effect, whereby a more uniform field distribution delays base push out effect in the transistor[5]. The AC and DC characteristcs will be reviewed.

A Simple Extraction Method of Thermal Resistance in Multifinger GaAs HBT

A novel extraction method to estimate the thermal resistance ( $R_{\mathrm {th}})$ of a multifinger GaAs heterojunction bipolar transistor (HBT) device is presented based on the simplified Fourier’s law. By calculating the thermal coupling resistance between the fingers on top of the self-heating thermal resistance, the values of $R_{\mathrm {th}}$ of multifinger devices for various dimensions are accurately calculated while maintaining the simplicity of calculation. To verify the idea, the proposed method is compared with the measurement-based method as well as the analytic methods, such as the finite-element method and the solution of 3-D Laplace’s equation. For four-finger HBT devices, the extracted $R_{\mathrm {th}}$ results showed good agreements with the analytic methods within an error of 9% and the measurement-based results with a deviation of 7.4%, thus convincing the usefulness of the proposed method.

A rigorous peeling algorithm for direct parameter extraction procedure of HBT small-signal equivalent circuit

A new direct parameter-extraction technique applied to the small-signal equivalent circuit of heterojunction bipolar transistor (HBT) is presented. The method is based on first determining the parasitic elements and then the intrinsic elements analytically. Concerning the intrinsic parameters, all the elements are extracted using exact closed-form equations derived in terms of S-parameters by reducing the small-signal models to the simplified using peeling algorithm. The validity of the new extraction methodology is demonstrated by applying it to a 1 × 15 µm2 InP HBT device within the frequency range of 0.1---40 GHz.