Heterogeneous System Architecture Research Articles

A review on computational storage devices and near memory computing for high performance applications

The von Neumann bottleneck is imposed due to the explosion of data transfers and emerging data-intensive applications in heterogeneous system architectures. The conventional computation approach of transferring data to CPU is no longer suitable especially with the cost it imposes. Given the increasing storage capacities, moving extensive data volumes between storage and computation cannot scale up. Hence, high-performance data processing mechanisms are needed, which may be achieved by bringing computation closer to data. Gathering insights where data is stored helps deal with energy efficiency, low latency, as well as security. Storage bus bandwidth is also saved when only computation results are delivered to the host memory. Various applications, including database acceleration, machine learning, Artificial Intelligence (AI), offloading (compression/encryption/encoding) and others can perform better and become more scalable if the “move process to data” paradigm is applied. Embedding processing engines inside Solid-State Drives (SSDs), transforming them to Computational Storage Devices (CSDs), provides the needed data processing solution. In this paper, we review the prior art on Near Data Processing (NDP) with focus on In-Storage Computing (ISC), identifying main challenges and potential gaps for future research directions.

Efficient hybrid centralized and blockchain-based authentication architecture for heterogeneous IoT systems

With the rapid increase in the number of Internet of Things (IoT) devices in recent years, massive amounts of sensitive IoT data are being generated and transmitted over the Internet. Despite its growing adoption in various fields, IoT security remains a major challenge requiring further research. IoT authentication is an essential security mechanism for building trust in IoT systems. However, conventional authentication approaches use expensive cryptographic primitives that do not align with the resource-constrained nature of IoT devices. Furthermore, centralized authentication schemes have proven to be inapplicable for cross-domain authentication and do not limit the scalability of IoT networks. Recently, blockchain technology has been applied to building decentralized authentication between IoT devices. Nevertheless, most existing blockchain-based authentication approaches incur high overhead in IoT computation, storage, and energy consumption. Authentication time is another critical issue in real-time IoT systems. When numerous IoT authentication requests are transferred to the blockchain, an additional time delay is imposed, in addition to the high computational cost of the blockchain caused by the consensus mechanism. This study proposes a hybrid centralized and blockchain-based authentication architecture for IoT systems. Edge servers are deployed to provide centralized authentication for associated IoT devices. A blockchain network of centralized edge servers is then established to ensure decentralized authentication and verification of IoT devices that belong to different and heterogeneous IoT systems. Lightweight cryptographic methods are implemented to achieve efficient authentication, in which limiting the consumption of IoT resources is required. The architecture is demonstrated using a local Ethereum blockchain network. The results indicate that the proposed method achieves significant improvements in terms of computation cost, execution time, and power consumption for IoT compared with centralized and blockchain-based authentication schemes. A security analysis proves the ability of our architecture to mitigate attacks and satisfy the IoT security requirements.

CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures

Integrating accelerators onto the same chip with CPUs sharing the last level cache (LLC) is beneficial when CPUs and accelerators frequently exchange data. However, if shared data exceeds LLC capacity, expensive spills to and refetches from DRAM will be incurred, limiting the benefits of such integrated architectures. While this can be avoided through careful software optimizations, such as fine-grain data tiling and accelerator synchronization, this involves significant software changes and programmer effort. In this article, we introduce CASPHAr, an LLC architecture that performs automatic, software- and hardware-transparent fine-grain data staging and synchronization between CPUs and accelerators in hardware. CASPHAr tracks and synchronizes producer and consumer accesses at cache line granularity. As soon as some fraction of shared data is produced and becomes ready in the LLC, the data will be delivered for processing in the waiting consumer. Furthermore, CASPHAr extends existing replacement policies to leverage synchronization information for making better eviction decisions. All combined, CASPHAr reduces data spills due to unnecessarily long lifetimes of shared data in the cache. In addition, fine-grain staging and synchronization inherently achieves system-level pipelining of interdependent kernels that can outperform software optimizations. Results show that CASPHAr can boost performance by up to 23% and achieve energy savings of up to 22% over baseline accelerations.

Optimization of a heterogeneous computing system architecture based on its coordination with a sensors group of a mobile unmanned platform

This article analyses the existing variety of sensors used in robotics and related fields and also proposes the architecture of a heterogeneous computing system designed to analyze data obtained from sensors of a mobile unmanned platform (MUP). A feature of unmanned platforms is the presence of tasks that require a significantly different level of performance of the on-board computing system for processing data from sensors of the corresponding type. Therefore, the adaptation of existing universal computing systems seems to be impractical, compared to the development of a specialized computing system with a heterogeneous architecture. The computing system is designed to solve problems of local navigation, stabilize the position of the MUP and control its movement, as well as control special equipment installed on the MUP. Often, if the goal is to ensure maximum efficiency, expressed in speed, accuracy and reliability, it is necessary to develop specialized devices. The article provides information on sensors of the main types used in robotics and indicates the requirements for the performance of a computing system necessary for processing data from sensors of this type. This, in turn, made it possible to propose a heterogeneous architecture containing processor subsystems focused on processing data from sensors requiring low, medium and high performance according to the considered classification.

Communication-efficient hierarchical federated learning for IoT heterogeneous systems with imbalanced data

Federated Learning (FL) is a distributed learning methodology that allows multiple nodes to cooperatively train a deep learning model, without the need to share their local data. It is a promising solution for telemonitoring systems that demand intensive data collection, for detection, classification, and prediction of future events, from different locations while maintaining a strict privacy constraint. Due to privacy concerns and critical communication bottlenecks, it can become impractical to send the FL updated models to a centralized server. Thus, this paper studies the potential of hierarchical FL in Internet of Things (IoT) heterogeneous systems. In particular, we propose an optimized solution for user assignment and resource allocation over hierarchical FL architecture for IoT heterogeneous systems. This work focuses on a generic class of machine learning models that are trained using gradient-descent-based schemes while considering the practical constraints of non-uniformly distributed data across different users. We evaluate the proposed system using two real-world datasets, and we show that it outperforms state-of-the-art FL solutions. Specifically, our numerical results highlight the effectiveness of our approach and its ability to provide 4–6% increase in the classification accuracy, with respect to hierarchical FL schemes that consider distance-based user assignment. Furthermore, the proposed approach could significantly accelerate FL training and reduce communication overhead by providing 75–85% reduction in the communication rounds between edge nodes and the centralized server, for the same model accuracy.

Emerging architecture for heterogeneous smart cyber-physical systems for industry 5.0

Industrial process automation is becoming more advance due to the new technological revolutions like Industrial Internet of things (IIoT), Machine to Machine Communication (M2M), cloud computing, cognitive computing, artificial intelligence, and big little multicore-based ARM processors for embedded applications. Modern IP-enabled sensors, actuators, and controllers are transforming industrial automation into industry 5.0 compliances to attain full autonomy with minimal human intervention. With these emerging technologies, Smart Cyber-Physical System (SCPS) is the most important part of the fourth industrial revolution, where diffident programmed embedded systems are networked together to perform, computation, communication, control, and actuation. In this paper, we proposed a heterogeneous architecture for SCPS, where different electrical, pneumatic, and hydraulic processes can be integrated to execute hybrid process dynamics. The proposed architecture is enabled to separate all aspects like computation, control, communication, and actuation, of a process dynamic by estimating the process disturbances, sensor delay, actuator delay, and conversion delay. The allotment of computational embedded cores to different physical processes is done through voltage frequency islands (VFI) with high modularity which is different for different processes. All the mapped process dynamics are optimized through Dynamic Voltage and Frequency Scaling (DVFS). The best implementation of the proposed architecture is the upcoming era of industry 5.0 where human intervention is also in a fold in various industries like petroleum, fertilizer, paper, cement, space exploration, and automobile manufacturing.

Real-time range gate control of a satellite laser ranging system based the on heterogeneous processor architecture.

The range gate generator (RGG) is a key device in kilohertz (kHz) satellite laser ranging systems. The RGG at Changchun station is an integrated circuit composed of discrete components. Using this RGG at high repetition rates can result in the loss of data, and the low resolution of internal time can lead to inaccurate data points. In this paper, starting from the principle of noise suppression by range gate control, we propose a method of range gate control with high repetition rates, high accuracy, and strong universality, and we implement a RGG based on the heterogeneous system architecture of a field-programmable gate array plus a digital signal processor. The average of the intervals between the internal time of the embedded RGG and the external standard time is 48.268 ns, and the accuracy of the range gate time is less than 1.5 ns. The test results indicate that the embedded RGG can satisfy the demand for centimeter-level accuracy with satellite laser ranging. Compared with the original RGG at Changchun station, the embedded RGG has significantly improved time resolution, repetition rate of laser ranging, and system upgrade and maintenance. At present, Changchun station is carrying out a short-term stability test on the embedded RGG.

Choice of architecture for heterogeneous information resources integration systems in natural-technical objects complex modeling

The paper presents a methodology of an architecture type multi-criteria choice for a system of integrating heterogeneous data required for complex modeling of natural-technical objects. Suggested methodology is based on using linguistic scales for architectures quality particular indicators, as well as methods of decisions verbal analysis and the experiment planning theory for processing results of peer review in the final architectures quality assessment.

Noise Removal from Remote Sensed Images by NonLocal Means with OpenCL Algorithm

We introduce a multi-platform portable implementation of the NonLocal Means methodology aimed at noise removal from remotely sensed images. It is particularly suited for hyperspectral sensors for which real-time applications are not possible with only CPU based algorithms. In the last decades computational devices have usually been a compound of cross-vendor sets of specifications (heterogeneous system architecture) that bring together integrated central processing (CPUs) and graphics processor (GPUs) units. However, the lack of standardization resulted in most implementations being too specific to a given architecture, eliminating (or making extremely difficult) code re-usability across different platforms. In order to address this issue, we implement a multi option NonLocal Means algorithm developed using the Open Computing Language (OpenCL) applied to Hyperion hyperspectral images. Experimental results demonstrate the dramatic speed-up reached by the algorithm on GPU with respect to conventional serial algorithms on CPU and portability across different platforms. This makes accurate real time denoising of hyperspectral images feasible.

FLA-IoT: Virtualization Enabled Architecture for Heterogeneous Systems in Internet of Things

A flexible architecture is always required when trying to communicate with heterogeneous kind of systems, and IoT is the largest communication network of the history, which is bringing life to everything around us. Currently available three and four layered communication architectures are the popular basic structures to implement IoT. Where three Layers architecture is composed of perception, network and application layers and four layer architecture is composed of perception, network, service, application layer. The problem with existing architectures is that some layers are not well managed and complex in structure and lacks in the interoperability of different kind devices. In this research we present a virtualization enabled architecture Flexible Layered Architecture for Internet of Things (FLA-IoT) to overcome those challenges. FLA-IoT provides a simple structure with well-organized layers and introduces the creation of Virtual Mote (virtual object) from all real-world devices to enable the communication between unlike devices. This results in an indiscriminate communication between different real-world devices with a well-managed layered architecture.

Stochastic Buffering for Bundled SWCNT Interconnects Considering Unidimensional Fabrication Variation

The heterogeneous system architecture which leverages multicore computing paradigm has become increasingly popular. Nevertheless, timing minimization is still a critical design challenge. Buffer insertion for bundled single-walled carbon nanotubes (SWCNTs) is capable of significantly improving circuit timing of signal nets with limited buffer deployment. However, due to the imperfection of fabricating long straight carbon nanotubes, there exist significant variations on the critical CNT geometric parameters such as the diameter and density, which will affect the circuit performance. On the other hand, the prevailing CNT fabrication uses Chemical Vapor Deposition, where the unidimensional spatial correlation manifests strongly. In this work, a unidimensional variation aware stochastic SWCNT interconnects buffering algorithm is developed to handle fabrication variations of CNTs in buffer insertion. To improve its time complexity, a novel importance sampling based timing evaluation technique is proposed considering unidimensional correlations of variations. The simulation results demonstrate that the unidimensional variation aware importance sampling based stochastic SWCNT interconnects buffering algorithm on average saves more than 30 percent buffer area over copper buffering while satisfying timing constraints. In addition, our proposed stochastic algorithm achieves much better performance than the best case design and the worst case design in terms of timing and buffer cost.

LTTng‐HSA: Bringing LTTng tracing to HSA‐based GPU runtimes

SummaryIn this paper, we propose LTTng‐HSA, a set of tools that allow for the collection of a single, unified software graphics processing unit (GPU) trace in ROCr, a Heterogeneous System Architecture (HSA)‐based API and runtime. HSA is a cross‐vendor standard facilitating the programming of heterogeneous systems that include CPUs, GPUs, and possibly other types of devices. Our open‐source solution is generic and easily adaptable to diverse GPU runtimes or APIs. Using Linux Trace Toolkit Next Generation (LTTng), a highly efficient Linux tracer, it collects different types of events over multiple executions of an application and aims to gather all the data into a single trace, offering an easy way to generate GPU‐related traces. Our instrumentation is achieved simply by preloading libraries, without recompiling the target application, which makes it flexible and easy to use. The resulting traces, which include API call stack information, GPU hardware metrics, command queue, and compute kernel profiling, are well adapted for postprocessing and further analysis. Our solution also includes tracing data from the Linux kernel and proposes views for Trace Compass, an interactive trace visualizer.

Entropy-aware ambient IoT analytics on humanized music information fusion

Musical information fusion in the era of Internet is participatory multi-sensor based heterogeneous musical data recognition and computing. Participatory devices enhance the progression of intelligent multimedia data fusion and analytics in the participated edge computing devices in the context of ambient Internet of Things. Sensed data streams coming from multi-sensors encounter the conventional methodologies for data analytics and are further transmitted to emerging big data archetype. The proposed contribution analyses, validates and evaluates a set of qualitative music data collected from wearable sound sensors. The authors present system architecture with three committed layers of participated devices for music fusion in the Internet of Things environment. Besides, an analytical case study on music fusion challenges is discussed along with the elucidation of their unique features in terms of Big data V-Scheme, followed by the demonstration of edge-cloud computing paradigm with deliberate evaluations. In this work, the system requirements in terms of data transmission latency and relevant power dissipation are visualized. The information and proposed system entropy of stochastic source of music data are evaluated in order to measure system efficiency and stability for performing multimedia communication. Quantitative evaluations are studied for comparison of heterogeneous system architectures in terms of system entropy that illustrate significant improvement in music fusion efficiency upon employing the proposed system archetype.

Platform-based service composition for manufacturing: A conceptualization

With the implementation of cyber-physical production systems, a multitude of isolated industrial services utilizing versatile hardware and software components in heterogeneous and rigid system architectures are an obstacle for the consequent extension of holistic automation within production networks. To address this issue, we conceptualize a platform-based system architecture enabling value-adding service bundles based on and extending proven architectural styles. Our proposal also aims on qualifying communication systems to work transboundary in value-adding networks. The presented architecture is applied to a use case in context of maintenance. Our findings provide an adaptive conceptualization for application-specific service composition and integration.

Heterogeneous Computing Utilizing FPGAs

Heterogeneous computing plays an ever-increasing role in power-efficient, high-performance embedded systems for various data processing tasks, such as computer vision. One possibility to accelerate this kind of application is the usage of FPGAs as a co-processor for standard CPUs. Although hardware design is becoming easier by utilizing High-Level-Synthesis tools, the question of interfacing FPGAs and CPUs has yet to be completely solved. The Heterogeneous System Architecture (HSA) Foundation defines and publishes architecture neutral standards for heterogeneous systems and programming models. While compatible CPU, GPU and DSP designs exist, FPGA models have not been defined yet. This paper describes the IP library LibHSA, which greatly simplifies integration of domain specific FPGA acceleration into existing HSA compliant systems. It allows FPGA based accelerators to take immediate advantage of high-level language tool chains. Including user space memory access, low-latency task dispatch and other benefits of the HSA programming model. We will demonstrate LibHSA with a programmable image processor implementation on a Xilinx FPGA. The image processor supports low-level algorithms, e.g. Sobel, Median, Laplace, or Gaussian. Our results show that the LibHSA infrastructure greatly simplifies the effort integrating FPGAs and customized hardware into existing accelerator systems, runtimes and application software.

A runtime controller for openCL applications on heterogeneous system architectures

Nowadays Heterogeneous System Architectures (HSAs) are becoming very attractive in the embedded and mobile markets thanks to the possibility to select the best computational resource among the available compute units to optimize the performance per Watt figure of merit. In this scenario, OpenCL is becoming the standard paradigm for heterogeneous computing supporting the programming of all types of units with a single abstraction level. However, the decision of the resource to use together with its architectural tuning is still left to the programmer; this issue is even more exacerbated when considering the fact that the choice depends also on the actual conditions in which the system is operating. This work aims at proposing a runtime controller, integrated in Linux Operating System (OS), for optimizing the power efficiency of a running OpenCL application deciding the system configuration. Our experimental results over a set of applications from the Polybench suite on the Odroid XU3 board show that our controller is able to obtain a power efficiency of more than 90% of the one achievable via offline profiling.

A Pipeline-Based Ray-Tracing Runtime System for HSA-Compliant Frameworks

Ray-tracing has received great attention over the years due to the high demand for global illumination appliances. Due to its embarrassingly parallel characteristics, the ray-tracing algorithm has been ported to the graphics processing unit (GPU) on heterogeneous systems that run thousands of threads in a single-instruction-multiple-thread fashion. However, the irregularity of ray-tracing causes a performance penalty on the GPU. The control flow divergence and early-termination problems severely degrade the hardware utilization, which makes the GPU computation inefficient while traversing through each iteration of the algorithm. Furthermore, additional overheads caused by data marshalling and load unbalancing negate the benefits of using heterogeneous systems. To tackle these issues, we designed a pipeline-based runtime methodology that leverages the features of heterogeneous system architecture (HSA)-compliant heterogeneous frameworks, such as shared virtual memory and fast kernel dispatching. This method merges the workloads from different iteration stages and dispatches them simultaneously. The merged workload is further assigned to a heterogeneous queue to enhance load balancing and scalability. With the proposed technologies, the performance of ray-tracing is enhanced significantly while effectively increasing the utilization of HSA-compliant heterogeneous systems. Based on the experiment results, the throughput becomes 4.37 times greater than the original setup on average in a single GPU mode and would always yield a greater throughput with a heterogeneous queue on multiple cores.

Enabling PoCL-based runtime frameworks on the HSA for OpenCL 2.0 support

Abstract The heterogeneous system architecture (HSA), announced by the HSA Foundation, is an approach to integrate central processing unit (CPU) and graphics processing unit (GPU) architectures. The open computing language (OpenCL) is a programming framework that can help utilize heterogeneous architectures. The well-known OpenCL framework, currently in version 1.2, provides programming models for heterogeneous computing. The proposed specifications of OpenCL 2.0 can help utilize HSA features, such as shared virtual memory (SVM). In previous work, we helped enable Portable Computing Language (PoCL)-based OpenCL 1.2 runtime frameworks on the HSA. In this paper, we further extend the PoCL-based runtime on the HSA to support OpenCL 2.0 features. In addition, this is the first work, to our best knowledge, to support PoCL-based OpenCL 2.0 features on HSA. Compared with the widely used OpenCL 1.2, OpenCL 2.0 will support SVM, nested parallelism, pipes, and atomic operations. It can further support parallel design patterns such as tree searches, pointer-based programming and nested parallelism models. Note that PoCL is a widely used open source implementation of OpenCL. Our design flow can help academics to enable OpenCL 2.0 flow on the HSA and benefit further from advanced academic research. The experimental results indicate that our framework provides adequate features to support advanced research.

HyWin: Hybrid Wireless NoC with Sandboxed Sub-Networks for CPU/GPU Architectures

Heterogeneous System Architectures (HSA) that integrate cores of different architectures (CPU, GPU, etc.) on single chip are gaining significance for many class of applications to achieve high performance. Networks-on-Chip (NoCs) in HSA are monopolized by high volume GPU traffic, penalizing CPU application performance. In addition, building efficient interfaces between systems of different specifications while achieving optimal performance is a demanding task. Homogeneous NoCs, widely used for many core systems, fall short in meeting these communication requirements. To achieve high performance interconnection in HSA, we propose HyWin topology using mm-wave wireless links. The proposed topology implements sandboxed heterogeneous sub-networks, each designed to match needs of a processing subsystem, which are then interconnected at second level using wireless network. The sandboxed sub-networks avoid conflict of network requirements, while providing optimal performance for their respective subsystems. The long range wireless links provide low latency and low energy inter-subsystem network to provide easy access to memory controllers, lower level caches across the entire system. By implementing proposed topology for CPU/GPU HSA, we show that it improves application performance by 29 percent and reduces latency by 50 percent, while reducing energy consumption by 64.5 percent and area by 17.39 percent as compared to baseline mesh.

A Power-Scalable Three-Dimensional Streaming Playback Mechanism on Heterogeneous System Architectures

In today’s world, mobile device technologies are advancing with each passing day. People use them to watch videos and deal with important business anywhere. Furthermore, the vigorous development of 3-D streaming technology makes possible the 3-D video conferencing, live broadcast, and online gaming, which made people feel like they were standing right in the scene themselves. However, higher qualities of multimedia streaming are demanded more and more, which necessitates that the content decoding capability of handheld devices be also relatively improved. This is the reason why some handheld devices can execute parallel processing and accelerate decoding processing with extra processes, such as central processing unit, digital signal processor, and graphics processing unit. However, power limitation is one of the inherent restrictions to handheld devices that makes providing high efficiency and energy-saving multimedia streaming service an urgent and interesting challenge. Therefore, a power-scalable 3-D streaming playback mechanism is proposed for the heterogeneous system architecture that is able to adjust the processor frequency or voltage to 3-D streaming service dynamically. In this paper, an immediate and accurate dynamic voltage–frequency scaling prediction mechanism with the properties of dependence for 3-D multimedia streaming decoding features is proposed for power-scalable 3-D streaming playback.