Heterodyne Architecture Research Articles

Active element pattern measurement in a hybrid antenna array with heterodyne architecture and its application

AbstractA measurement method of an active element antenna pattern in a hybrid antenna array with heterodyne architecture under a real environment is proposed and applied to the design of an ultralow sidelobe level scanning array. To avoid the phase uncertainty caused by the local oscillator signal in the heterodyne architecture, a phase‐normalized active element pattern (PNAEP) is used to characterize the element antenna patterns of both amplitude and phase. The PNAEP has almost taken account of all the practical factors of an array, such as mutual couplings, various types of element antennas, unequal spacing, or diverse environmental effects. The PNAEP is measured with a 16‐element scanning receiving array with a heterodyne architecture to validate the feasibility of the PNAEP. Based on the PNAEP, the scanning array achieve an ultralow sidelobe level of −33 dB. Applying to various receiving array architectures the PNAEP method is a feasible and universal tool for array synthesis and optimization under real environments.

A 1.25 μJ per Measurement Ultrasound Rangefinder System in 65 nm CMOS for Explorations With a Swarm of Sensor Nodes

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates $0.43~\mu \text{J}$ and ${0.82~\mu \text {J}}$ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and $0.56~\mu \text{W}$ , respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates $1.25~\mu \text {J}$ per measurement, achieving a resolution of 18.7 mm at 0.55 m.

Range-Doppler Map Improvement in FMCW Radar for Small Moving Drone Detection Using the Stationary Point Concentration Technique

Given the rapidly growing drone market, the development of drone detection radars has become highly important to prevent drones from damaging lives and property. Frequency-modulated continuous-wave (FMCW) radars have been frequently used for drone detection. Among the architectures of FMCW radar, a heterodyne architecture that involves different local oscillators and produces beat signals at the IF stage has often been chosen. The FMCW radar, however, has a chronic problem called leakage. In an earlier study, we proposed the stationary point concentration (SPC) technique to improve the signal-to-noise ratio (SNR) of small drones by reducing the increase in noise floor caused by leakage. We demonstrated that the proposed technique increases the SNR of small hovering drones in the 1-D power spectrum. In this article, we newly analyze the practical problems in the heterodyne FMCW radar system. One is the 2-D noise floor increase in the range-Doppler (r-D) map due to the leakage, and the other is unwanted Doppler shifts. Then, we propose an upgraded theory and realization method of the SPC technique for the detection of the small moving drone by improving the r-D map. We prove that the proposed method not only reduces the 2-D noise floor by mitigating the leakage but also removes the unwanted Doppler shifts by the phase calibration. Consequently, we show that the proposed method increases the SNR of the small moving drone and corrects its velocity information at the same time in the r-D map.

A Fully Integrated 150-GHz Transceiver Front-End in 65-nm CMOS

A fully integrated D-band transceiver front-end with on-chip frequency synthesizer is implemented in 65-nm CMOS. The transceiver front-end adopts the dual-conversion sliding-IF heterodyne architecture to relax the design difficulty of the local oscillation (LO) signal generator. The D-band signal is first down-converted via a 100-GHz LO signal and IQ down-converted via a 50-GHz quadrature LO signal in the receiver (RX). While in the transmitter, the modulated signal is generated at 50 GHz and up-converted via a 100-GHz LO signal. The measured transmitter output power is 2.1 dBm at 150 GHz, with >11 GHz 3-dB bandwidth. The measured results also show the cascaded gain of the RX can be programmed from 57.4 dB to 45.6 dB with 3-dB bandwidth of 9.6 GHz to >20 GHz.

A 28 GHz four-channel phased-array transceiver in 65-nm CMOS technology for 5G applications

A 28 GHz fully integrated 4-channel TX/RX 5G beam-forming transceiver is implemented in 65-nm CMOS technology. Each TX/RX channel can be digitally controlled with 5.625° phase step and 2 dB gain step. The transceiver employs a heterodyne architecture with 6 GHz intermediate frequency (IF). The transceiver works in a band of frequencies between 26 GHz and 30 GHz. The up/down-conversion mixers are integrated on the same chip with a shared LO chain. The phased-array power combining/splitting is done using a Wilkinson power combiner/divider. Each channel features 3.4–3.9 dB NF and −5 to −3.5 dBm IIP3 in RX mode, high OP1dB of 14.7 dBm and 18 dB gain in TX mode. The maximum rms amplitude and phase error for each channel is 0.25 dB and 1.5° across gain and phase states, respectively. The RFIC area is 5.29 × 3.4 mm2 including pads and it consumes 240 mW per channel in TX mode, 120 mW per channel in RX mode and 174 mW for the LO chain with a total power of 1.58 W from a 1.2 V supply.

A 1-D Heterodyne Lens-Free Optical Phased Array Camera With Reference Phase Shifting

This paper presents the first integrated silicon photonics optical phased array (OPA) receiver with imaging capabilities. A 32-element 1D OPA with an overall aperture size of 96x50 μm^2 is used to generate an electrically steerable “gazing beam”. The OPA receiver elements couple the incident light to on-chip waveguides which is processed as a phased array receiver. To minimize signal loss and enhance sensitivity, a heterodyne architecture with phase shifters in the local reference path is utilized. The OPA receiver can provide fully programmable angular selectivity with a grating-lobe-free field-of-view of 30° and a gazing beamwidth of 0.74°.

An Ultra-Wideband IF Millimeter-Wave Receiver With a 20 GHz Channel Bandwidth Using Gain-Equalized Transformers

This paper presents a CMOS millimeter-wave (mm-wave) receiver designed to meet the challenges in low-power, ultra-broadband, phased-array systems with a large number of array elements. This receiver employs a high intermediate-frequency (IF) heterodyne architecture to reduce the frequency and power consumption associated with distributing a local oscillator (LO). The receiver operates over a bandwidth of 51–71 GHz, while maintaining 20 GHz of bandwidth along the signal chain of the entire mm-wave front end, through a high-IF stage, and to the baseband output. To maintain a high fractional bandwidth (fBW) throughout the signal chain, this receiver employs multiple gain-equalized transformers . Receiver measurements show an overall flat bandwidth response of 20 GHz, with a total gain of 20 dB, a minimum double-sideband noise figure of 7.8 dB, and an input 1 dB compression power of $- 24 \text{dBm}$ while consuming 115 mW from a 1.1 V supply. The test chip, implemented in a six-metal layer 40 nm CMOS process, occupies an area (including pads) of $1.2 \text{mm}^{2}$ .

High accuracy amplitude and phase measurements based on a double heterodyne architecture

In the digital low level RF (LLRF) system of a circular (particle) accelerator, the RF field signal is usually down converted to a fixed intermediate frequency (IF). The ratio of IF and sampling frequency determines the processing required, and differs in various LLRF systems. It is generally desirable to design a universally compatible architecture for different IFs with no change to the sampling frequency and algorithm. A new RF detection method based on a double heterodyne architecture for wide IF range has been developed, which achieves the high accuracy requirement of modern LLRF. In this paper, the relation of IF and phase error is systematically analyzed for the first time and verified by experiments. The effects of temperature drift for 16 h IF detection are inhibited by the amplitude and phase calibrations.

Single- and Dual-Port 50-100-GHz Integrated Vector Network Analyzers With On-Chip Dielectric Sensors

This work presents a single- and dual-port fully integrated millimeter-wave ultra-broadband vector network analyzer. Both circuits, realized in a commercial 0.35-μm SiGe:C technology with an ft/fmax of 170/250 GHz, cover an octave frequency bandwidth between 50-100 GHz. The presented chips can be configured to measure complex scattering parameters of external devices or determine the permittivity of different materials using an integrated millimeter-wave dielectric sensor. Both devices are based on a heterodyne architecture that achieves a receiver dynamic range of 57-72.5 dB over the complete design frequency range. Two integrated frequency synthesizer modules are included in each chip that enable the generation of the required test and local-oscillator millimeter-wave signals. A measurement 3σ statistical phase error lower than 0.3 ° is achieved. Automated measurement of changes in the dielectric properties of different materials is demonstrated using the proposed systems. The single- and dual-port network analyzer chips have a current consumption of 600 and 700 mA, respectively, drawn from a single 3.3-V supply.

Heterodyne architecture for tunable laser chirped dispersion spectroscopy using optical processing.

Dispersion-based spectroscopic techniques present many desirable features when compared with classical absorption spectroscopy implementations, such as the normalization-free operation and the extended dynamic range. In this Letter, we present a new sensor design based on direct optical processing for heterodyne conversion in tunable laser chirped dispersion spectroscopy that allows sensor implementations using low-speed photodetectors and low-cost FM demodulators. The performance of the new setup has been validated using as a target the ro-vibrational transition of methane at approximately 1650.96 nm.

Design and implementation of a hybrid digital and RF front-end module for 24-GHz intelligent transport system pulse-doppler radar

This article presents a hybrid digital and RF front-end module (FEM) of a 24-GHz pulse-Doppler radar system for intelligent transport system applications. The conventional pulse generators use analog components such as step recovery diode. It is difficult to control the parameters of the pulse. In addition, the heterodyne architecture based transceivers show good performance, but they are very expensive. To overcome these limitations, a digital pulse generator was developed based on field-programmable gate array platform to obtain high degree of freedom in a waveform design. Instead of the heterodyne architecture, a transceiver based on the homodyne architecture was developed. For the first time, hybrid digital FEM based 24-GHz pulse-Doppler radar was developed by combining a digital pulse generator and a homodyne-based transceiver. Experimental results showed the feasibility of using a hybrid digital FEM for a 24-GHz pulse-Doppler radar. The developed hybrid digital FEM contributes to the advancement of the digital radar field. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1631–1638, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27666

NEMS-based heterodyne self-oscillator

We report a novel NEMS-based heterodyne self-oscillator. By using a downmixing detection scheme, the NEMS motion piezoresistive signal at 20MHz is shifted down to few tens of kHz, thus avoiding the negative impact of stray capacitances. This technique allows the NEMS self-oscillator to benefit from its major advantages: a high dynamic range and a high signal to background ratio. However in this form, the signal cannot be directly inserted in a standard oscillator feedback loop since the output signal is neither proportional, nor at the same frequency as the NEMS actuation signal. This paper describes a novel heterodyne architecture so that self-oscillation motion of the NEMS builds up with excellent frequency stability. By providing a high dynamic range and high signal to background ratio, this feedback loop architecture represents an efficient way to track NEMS resonance frequency in real time, as required in sensing applications like mass sensors.

Compressive Spectrum Sensing Using a Bandpass Sampling Architecture

Fast and reliable detection of available channels (i.e., those temporarily unoccupied by primary users) is a fundamental problem in the context of emerging cognitive radio networks, without an adequate solution. The (mean) time to detect idle channels is governed by the front-end bandwidth to be searched for a given resolution bandwidth. Homodyne receiver architectures with a wideband radio-frequency front-end followed by suitable channelization and digital signal processing algorithms, are consistent with speedier detection, but also imply the need for very high speed analog-to-digital converters (ADCs) that are impractical and/or costly. On the other hand, traditional heterodyne receiver architectures consist of analog band-select filtering followed by down-conversion that require much lower rate ADCs, but at the expense of significant scanning operation steps that constitute a roadblock to lowering the scan duration. In summary, neither architecture provides a satisfactory solution to the goal of (near) real-time wideband spectrum sensing. In this work, we propose a new compressive spectrum sensing architecture based on the principle of under-sampling (or bandpass sampling) that provides a middle ground between the above choices, i.e., our approach requires modest ADC sampling rates and yet achieves fast spectrum scanning. Compared to other compressive spectrum sensing architectures, the proposed method does not require a high-speed Nyquist rate analog component. A performance model for the scanning duration is developed based on the mean time to detect all idle channels. Numerical results show that this scheme provides significantly faster idle channel detection than the conventional serial search scheme with a heterodyne architecture.

A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting an 802.15.3c heterodyne transceiver is reported. The PLL can generate 6 equally spaced tones from 43.2 GHz to 51.84 GHz, which is suitable for a heterodyne architecture with F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LO</sub> =(4/5)×F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TRX</sub> . Phase noise is measured directly at the F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LO</sub> frequency and is better than -97.5 dBc/Hz@1 MHz across the entire band. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LO</sub> tone corresponds to the fundamental of the VCO as opposed to a higher harmonic.

Terahertz Imaging Systems With Aperture Synthesis Techniques

This paper presents the research and development of two terahertz imaging systems based on photonic and electronic principles, respectively. As part of this study, a survey of ongoing research in the field of terahertz imaging is provided focusing on security applications. Existing terahertz imaging systems are reviewed in terms of the employed architecture and data processing strategies. Active multichannel measurement method is found to be promising for real-time applications among the various terahertz imaging techniques and is chosen as a basis for the imaging instruments presented in this paper. An active system operation allows for a wide dynamic range, which is important for image quality. The described instruments employ a multichannel high-sensitivity heterodyne architecture and aperture filling techniques, with close to real-time image acquisition time. In the case of the photonic imaging system, mechanical scanning is completely obsolete. We show 2-D images of simulated 3-D image data for both systems. The reconstruction algorithms are suitable for 3-D real-time operation, only limited by mechanical scanning.

Multiband 0.25-$\mu{\hbox {m}}$ CMOS Base Station Chips for Indirect and Direct Conversion Receivers

This paper describes a multiband CMOS chip-set for indirect and direct conversion base station receivers. The chip set consists of a low-noise amplifier (LNA), and a down-converter which includes a passive resistive mixer and a local-oscillator balun. The 0.25-mum CMOS receiver chip set, biased at 3 V, meets normal DCS1800, PCS1900, and Universal Mobile Telecommunication System (UMTS) base station specifications in heterodyne and homodyne architectures. In a heterodyne architecture, an third-order input intercept point (IIP3) higher than -5 was achieved with a noise figure (NF) lower than 4.5 dB for the complete receiver chain in the DCS1800, PCS1900, and UMTS bands. In a homodyne architecture, IIP3 and second-order input intercept point (IIP2) values better than 0 and 40 dBm, respectively, were achieved for the complete receiver chain in all three bands, with an NF of less than 6 dB. A dedicated DCS1800 heterodyne receiver based on this chip-set was developed, meeting and exceeding the specifications, with a NF of 5.8 dB and IIP3 of 0.4 dBm. This is believed to be the first CMOS receiver chip set that meets second and third-generation base station specifications in indirect and direct conversion architectures.

Rf transceiver reference design for third generation W-CDMA cellular handset

A radio frequency transceiver reference design for third generation UTRA/FDD W-CDMA cellular handset is presented in this paper, A number of commercial RFICs are analyzed by considering the heterodyne architecture implementation of the transceiver. Requirements and considerations in the cellular handset radio frequency transceiver design are also discussed. Numerical analysis and measurement results obtained in this work could be used as a reference design for immediate RF transceiver hardware implementation in commercial 3G W-CDMA cellular handsets.

A dual-band RF transceiver for multistandard WLAN applications

A new dual-band RF transceiver is presented for 2.4- and 5.2-GHz multistandard wireless local area networks. The proposed dual-band RF transceiver integrates a concurrent dual-band front-end, a triple-band frequency synthesizer, and a band-sharing in-phase/quadrature modulator/demodulator to maximize component and power reuse. The design is started with the examination of an enhanced dual-band heterodyne architecture and then the optimal circuit partition to satisfy the multistandard requirements. Key dual-band circuits are designed and integrated with other building blocks for experimental demonstration. The measurement shows that eight 5-GHz channels and 13 2.4-GHz channels can be synthesized within 130 /spl mu/s with phase noise less than -98 dBc/Hz at 100-kHz off carrier and spur suppression greater than -65 dBc. The transmitted P/sub 1 dB/ power is 25/20 dBm at 2.4/5.2 GHz, respectively, with the modulation accuracy error-vector magnitude (EVM) values varying from 3.57% to 7.19%. The receiver gain is 20/31 dB at 2.4/5.2 GHz front-end and 70 dB at IF back-end with EVM within 2.32% to 10% from -70- to -17-dBm received power range.

Digital-IF WCDMA handset transmitter IC in 0.25-/spl mu/m SiGe BiCMOS

Implemented in a 0.25-/spl mu/m SiGe BiCMOS process, a highly integrated low-power transmitter IC (TxIC) is developed for wideband code-division multiple-access handset applications. Based on a digital-IF heterodyne architecture, it eliminates the external IF surface acoustic wave filter by adopting a meticulous frequency plan and a special-purpose second-order-hold D/A conversion scheme. The TxIC features a low-power high-speed D/A converter designed to drive a dominantly capacitive load. For the upconversion mixer and the RF amplifier, adaptive biases are designed to minimize the quiescent power consumption and to provide current boost only when needed. The TxIC achieves <1% EVM. It consumes 180 mW (3-V supply) for the maximum output power of +5 dBm and reduces to 120 mW during power backoff.

Highly polarization-sensitive thick gratings for a holographic Stokesmeter

A holographic Stokesmeter has the potential to be useful in high-speed polarization imaging applications. Highly polarization-sensitive gratings are an important component in a robust holographic Stokesmeter. We demonstrate a set of individual holographic gratings in a thick substrate displaying a high contrast in diffraction efficiency as a function of the polarization of the read beam. We confirm that the observed dependence is consistent with the coupled-wave analysis of such gratings. In addition, we performed a numerical analysis of the noise tolerance of such a Stokesmeter, and suggest a heterodyne architecture to further enhance signal-to-noise ratio.