Gate HEMT Research Articles

Charge Density Based Small Signal Modeling for InSb/AlInSb Asymmetric Double Gate Silicon Substrate HEMT for High Frequency Applications

This paper proposes the Asymmetric Double Gate Silicon Substrate HEMT (ADG-Si-HEMT) to study the carrier concentration and intrinsic small signal parameters of the InSb/AlInSb silicon wafer DG-HEMT device. The HEMTs work as a three-port system and the device is named Asymmetric Double Gate HEMT when the top and bottom gates are biased with different gate voltages. The position of quasi-Fermi energy levels (Ef) is used to investigate the modulation of back-channel charge density caused by the front gate voltage. Also, the small signal model is obtained for a various parameters such as cut off frequency, gate to source capacitance and transconductance. To enhance device operation, the effects of the following factors are being investigated delta doping, drain current for various top and bottom gate voltages. The transconductance 2390 Sm/mm for Vfg = 0.2 V and cut off frequency around 197 GHz for Vbg = 0.3 are obtained. The analytical results are compared to the results of the Sentaurus 3-D TCAD simulation. Because of the variation in threshold voltage and modifying carrier density in dual channels, the asymmetric biassing approach has a wide range of mixed applications.

The GaAs/AlGaAs-Based Extended Gate HEMT Cardiac Troponin-I Biosensor: Design, Mechanism and Clinical Detection

Herein, we designed several structures of GaAs/AlGaAs extended gate high electron mobility transistors (EG-HEMT) for cTnI detection, in order to explore the mechanism of bio-detection, the limit of detection (LOD) as well as the application in clinical detection. The experiment carried out that 50y structure of EG-HEMT biosensor, whose extended electrode is 50 times as large as the gate, has highest biological regulation ability ( δ). Meanwhile, the concentration range of cTnI detection using 50y EG-HEMT biosensor is about 100 fg ml <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> to 10 μg ml <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , which is much broader than that of Unicel Dxl800 (usually be used in clinical detection). Furthermore, due to the influence of parasitic resistance and other factors, δ increases with the increase of y, but the rising rate of δ decreases at the same time. By comparing the detecting results of clinical samples, 30y EG-HEMT is the best in the detection of cTnI concentration with a relative error of 6%. In a higher concentration range, it is more accurate than that of the Unicel Dxl800, breaking through its limit.

Decoupling of Forward and Reverse Turn-on Threshold Voltages in Schottky-Type p-GaN Gate HEMTs

In a p-channel field-effect-transistor ( p-FET) bridge HEMT device recently realized on a commercial p-GaN/AlGaN/GaN-on-Si power HEMT epi-wafer, it is revealed that the device's reverse-conduction turn-on voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RT</sub> ) can be effectively decoupled from the forward threshold voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) of Schottky-type p-GaN gate HEMTs. Unlike the conventional Schottky-type p-GaN gate HEMTs, of which V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RT</sub> is closely linked to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> , the p-FET-bridge HEMT enables separate designs of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RT</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> so that low-loss reverse conduction and high threshold voltage can be simultaneously realized. In addition, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RT</sub> can be further reduced by engineering the AlGaN barrier layer, which will also benefit a lower channel sheet resistance without lowering V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> .

Observation and characterization of impact ionization-induced OFF-state breakdown in Schottky-type p-GaN gate HEMTs

In this work, the impact ionization-induced OFF-state breakdown is revealed and systematically investigated in 100 V Schottky-type p-GaN gate high-electron-mobility transistors. Impact ionization is found to occur in the peak electric-field region at the source-terminated field-plate edge and is initiated by electrons injected from the source-side two-dimensional electron gas channel through the buffer layer. Hot electrons generated from impact ionization, when being captured by surface traps, could lead to redistribution and peak value reduction of electric-field. Consequently, the sudden rise in the OFF-state leakage current by impact ionization could be self-clamped temporally to avoid catastrophic rupture of the device. The impact ionization is further verified by the increase in dynamic OFF-state leakage current and a negative shift in threshold voltage, both of which result from positively charged holes (generated from impact ionization) drifting toward the gated channel.

Characterization of Dynamic Threshold Voltage in Schottky-Type p-GaN Gate HEMT Under High-Frequency Switching

The dynamics of the intrinsic threshold voltage ( ${V}_{{\text {TH}}}{)}$ shift in 650-V Schottky-type p-GaN gate HEMT under high-frequency switching is investigated by a bootstrap voltage clamping circuit in which the GaN HEMT serves as the key bootstrapping device. This new testing setup covers a wide range of OFF-state drain bias ( ${V}_{{\text {DSQ}}}{)}$ up to 400V, a short OFF-to-ON (or stress-to-sense) delay ( ${T}_{{\text {delay}}}{)}$ of 60ns, and a high switching frequency ( ${f}_{{\text {sw}}}{)}$ up to 2MHz. The dynamic ${V}_{{\text {TH}}}$ ’s dependences on ${V}_{{\text {DSQ}}}$ and ${f}_{{\text {sw}}}$ are characterized by this testing setup. A higher VDSQ (up to 400V) results in a larger dynamic ${V}_{{\text {TH}}}$ shift ( $\Delta {V}_{{\text {TH}}}{)}$ . The $\Delta {V}_{{\text {TH}}}$ exhibits a gradually increasing trend under the continuous high-frequency switching mode. In addition, after continuous switching operation for $200\mu \text{s}$ , the maximum $\Delta {V}_{{\text {TH}}}$ shows no ${f}_{{\text {sw}}}$ dependence with a wide range of frequency from 50kHz to 2MHz.

Integration of GaN analog building blocks on p-GaN wafers for GaN ICs

We demonstrate the key module of comparators in GaN ICs, based on resistor-transistor logic (RTL) on E-mode wafers in this work. The fundamental inverters in the comparator consist of a p-GaN gate HEMT and a 2DEG resistor as the load. The function of the RTL comparators is finally verified by a undervoltage lockout (UVLO) circuit. The compatibility of this circuit with the current p-GaN technology paves the way for integrating logic ICs together with the power devices.

GaN power IC design using the MIT virtual source GaNFET compact model with gate leakage and V T instability effect

This work presents the MIT virtual source GaNFET model for GaN integrated circuit (IC) design, which is adapted to model the threshold voltage (V T) instability and p-GaN gate leakage. Because of the lack of GaN pFETs, the source follower topology is often implemented in GaN ICs, suffering from an instable V T drop from rail to gate. With the adapted model, the simulation successfully reproduced the evolution of the output waveforms of a monolithically integrated GaN driver circuit under switching stress. Moreover, the gate voltage redistribution of the power p-GaN gate HEMTs controlled by the integrated GaN driver is evidently proved to strongly depend on the gate leakage. If neglecting the V T shift and gate leakage, the design could induce some malfunction.

Investigating the Current Collapse Mechanisms of p-GaN Gate HEMTs by Different Passivation Dielectrics

In this letter, the dynamic R on degradation mechanisms of the p-GaN gate HEMTs induced by off -state stress are investigated with different passivation dielectrics AlON and SiN. The degradation mechanisms are twofold, including V TH shift and surface trapping in the gate-to-drain access region, whose impacts are successfully distinguished. Surface trapping by SiN passivation is evidently proved to be the dominant factor that can almost induce a full current collapse. The V TH positive shift diminishes the drain current by shrinking the overdrive V GS, which however, can be compensated by a higher V GS overdrive in applications. SiN passivation can effectively suppress the positive bias temperature instability effect, probably by passivating the p-GaN fast traps with hydrogen during passivation. Last, the transient measurements unveil that both the surface trapping and V TH shift have a very slow recovery process.

Performance Analysis of Normally-on Dual Gate Algan/Gan Hemt

This paper presents the novel normally-on dual gate (DG) AlGaN/GaN high electron mobility transistor. At high frequency, the dual gate structure gives superlative immunity over short channel effects. Multiple 2DEG channel regions in dual gate AlGaN/GaN HEMT improves the transport characteristics, charge control and gives better linearity. The high carrier mobility and electron saturation velocity contribute to the high switching frequency of DG HEMT. The drain characteristics of single gate HEMT and dual gate HEMT are compared and DG HEMT outstands in drain current. The various analog and linearity parameters are investigated for DG HEMT. The performance analysis provides better transconductance, capacitance, cut off frequency, subthreshold slope and on-resistance simulations represents the potential of DG HEMT. The DG HEMT provides 1100 mA/mm ION, 550 mS/mm transconductance and 11 GHz cutoff frequency at Vgs = 2 V. The high drain current, better transconductance and cutoff frequency results in better sensitivity of device.

Simulation Study of an Ultralow Switching Loss p-GaN Gate HEMT With Dynamic Charge Storage Mechanism

In this article, a dynamic charge storage mechanism is proposed for designing the p-GaN gate dynamic charge storage high-electron-mobility transistor (DCS-HEMT) with ultralow switching loss. The device features a p-doped DCS layer in AlGaN buffer. When the DCS-HEMT is turning off, the net negative charges in the DCS layer significantly contribute to the depletion of 2-D-electron-gas (2DEG) channel, leading to low turn-off loss (${E} _{OFF}$ ). During turn-on process, reduction of the negative charges amount could accelerate the formation of electrons at the 2DEG channel, which results in low turn-on loss (${E} _{ON}$ ). Verified by the calibrated simulation, total switching loss (${E} _{\text {SW}} \boldsymbol = {E}_{OFF} +{E}_{ON}$ ) of the designed DCS-HEMT is 61% lower than that of the conventional p-GaN gate HEMT (C-HEMT). The improved performance makes the DCS-HEMT a competitive candidate for low switching loss power applications.

Gate leakage current sensing for in situ temperature monitoring of p-GaN gate HEMTs

In this paper, an effective, yet simple, methodology for the temperature monitoring of voltage-driven p-GaN HEMTs based on gate leakage current sensing is presented. The proposed solution has been verified by SPICE electrothermal simulations and experiments on commercial devices within and out of safe operating area (SOA). Moreover, the monitoring circuit can be effectively adopted for commercially available normally-off p-GaN HEMTs with no need of modifying the recommended gate driver circuit.

Accurate Temperature Estimation for Each Gate of GaN HEMT With n-Gate Fingers

An analytical approach based on the thermoelectrical analogy to calculate the maximum channel temperature of multifinger AlGaN/GaN HEMT transistor is presented. The model is capable of predicting the maximum channel temperature, including the impact of the nonlinearity of thermal conductivity for every single gate with excellent accuracy. The model remains invariant under device scaling up and down and gives an accurate estimation for any number of gate fingers. Furthermore, the temperature field fluctuation due to the interaction between gates and variation in the number of gate fingers can be easily identified by the model. The validity of the proposed approach has been testified by comparing the results with those from infrared spectroscopy and numerical simulations for different AlGaN/GaN HEMT transistors with a different number of gates. The significance of models is justified by its ability to evaluate the temperature of any gate finger with high accuracy. Such an ability is particularly highly important while optimizing the structure layout and cooling system for high-power AlGaN/GaN HEMT transistors. The model can serve as a powerful tool for power devices and microwave IC designers and can be easily incorporated into SPICE empirical or physical-based models.

Surface-Potential-Based Compact Model for the Gate Current of p-GaN Gate HEMTs

The gate leakage current of p-GaN gate HEMTs is modeled based on surface potential calculations. The model accurately describes the bias and temperature dependence of the gate leakage. Thermionic emission is the main mechanism of the gate current in forward bias operation while hopping transport component is the main mechanism of gate current in reverse bias operation. This newly developed gate current model was implemented in Verilog-A. A good agreement between the simulations and experimental data demonstrates the accuracy of the model.

Characterization and analysis of low-temperature time-to-failure behavior in forward-biased Schottky-type p-GaN gate HEMTs

The low-temperature gate reliability of Schottky-type p-GaN gate AlGaN/GaN heterojunction field-effect transistors under forward gate voltage stress is investigated. Both temperature-accelerated and voltage-accelerated time-dependent gate breakdown stress experiments are performed. The p-GaN gate exhibits a shorter time-to-failure at a lower temperature. It is found that the time-to-failure at “use conditions” predicted by acceleration tests at high gate bias stress could be overestimated at low temperatures. Such a discrepancy stems from the distinct dominant gate leakage mechanisms at high/low gate bias stress conditions. The dominant physical mechanism of the low-temperature gate leakage current is identified to be Poole–Frenkel emission at low gate bias and Fowler–Nordheim tunneling at high bias. From the physical model, a more accurate lifetime projection can be obtained for given use conditions.

Identification of Trap States in p-GaN Layer of a p-GaN/AlGaN/GaN Power HEMT Structure by Deep-Level Transient Spectroscopy

In this work, the deep-level transient spectroscopy (DLTS) is conducted to investigate the gate stack of the ${p}$ -GaN gate HEMT with Schottky gate contact. A metal/ ${p}$ -GaN/AlGaN/GaN heterojunction capacitor is prepared for the study. The DLTS characterization captures the transient capacitance change in the stack, from which the capacitance of the metal/ ${p}$ -GaN Schottky junction can be extracted. By proper selection of the rate window, the impacts of the hole insufficiency effect are avoided during trap states evaluation. Thus, the information of deep energy levels in the ${p}$ -GaN layer is revealed, which consists of an electron trap state with activation energy of 0.85 eV and a hole trap state with activation energy of 0.49 eV. The identification of these trap states in the ${p}$ -GaN layer provides a physical foundation for understanding the threshold voltage instability in Schottky-type ${p}$ -GaN gate power HEMTs.

E-Mode p-n Junction/AlGaN/GaN (PNJ) HEMTs

In this work, we demonstrate a GaN-based $\textit {p-n}$ junction gate (PNJ) HEMT featuring an ${n}$ -GaN/ ${p}$ -GaN/AlGaN/GaN gate stack. Compared to the more conventional ${p}$ -GaN gate HEMT with a Schottky junction between the gate metal and ${p}$ -GaN layer, the $\textit {p-n}$ junction can withstand higher reverse bias at the same peak electric-field as the depletion region extends to both the ${n}$ -side and ${p}$ -side, while exhibiting lower leakage current. The PNJ-HEMT shows a positive threshold voltage ( ${V}_{\text {TH}}$ ) of 1.78 V, a small gate leakage $(\sim 10^{-3}$ mA/mm @ ${V}_{\text {GS}} = {10}\,\, \text {V}$ ). In particular, a large forward gate breakdown voltage of 19.35 V at 25 °C and 19.70 V at 200 °C was achieved with the PNJ-gate HEMT.

Observation of Dynamic V TH of p-GaN Gate HEMTs by Fast Sweeping Characterization

In this work, fast sweeping characterization with an extremely short relaxation time was used to probe the ${V}_{\text {TH}}$ instability of p-GaN gate HEMTs. As the ${I}_{\text {D}}$ - ${V}_{\text {G}}$ sweeping time deceases from 5 ms to $5~\mu \text{s}$ , the ${V}_{\text {TH}}$ dramatically degenerates from 3.13 V to 1.76 V, meanwhile the hysteresis deteriorates from 22.6 mV to 1.37 V. Positive bias temperature instability (PBTI) measurement by fast sweeping shows the ${V}_{\text {TH}}$ features a very fast shifting process but a slower recovering process. D-mode HEMTs counterpart without Mg contamination demonstrates a negligible ${V}_{\text {TH}}$ shift and hysteresis, proving the ${V}_{\text {TH}}$ instability is probably due to the ionization of acceptor-like traps in the p-GaN depletion region. Finally, the ${V}_{\text {TH}}$ instability is verified by a GaN circuit under switching stress. The ${V}_{\text {TH}}$ instability under different sweeping speed uncovers the fact that the high ${V}_{\text {TH}}$ by conventionally slow DC measurements is probably artificial. The DC ${V}_{\text {TH}}$ should be high enough to avoid HEMT faulty turn-on.

Gate Leakage Suppression and Breakdown Voltage Enhancement in p-GaN HEMTs Using Metal/Graphene Gates

In this work, single-layer intrinsic and fluorinated graphene were investigated as gate insertion layers in normally-OFF p-GaN gate HEMTs, which wraps around the bottom of the gate forming Ti/graphene/p-GaN at the bottom and Ti/graphene/ SiNx on the two sides. Compared to the Au/Ti/p-GaN HEMTs without graphene, the insertion of graphene can increase the ION/IOFF ratios by a factor of 50, increase the VTH by 0.30 V and reduce the off-state gate leakage by 50 times. Additionally, this novel gate structure has better thermal stability. After thermal annealing at 350 {\deg}C, gate breakdown voltage holds at 12.1 V, which is first reported for Schottky gate p-GaN HEMTs. This is considered to be a result of the 0.24 eV increase in Schottky barrier height and the better quality of the Ti/graphene/p-GaN and Ti/graphene/SiNx interfaces. This approach is very effective in improving the Ion/Iff ratio and gate BV of normally-OFF GaN HEMTs.

Asymmetric Bipolar Injection in a Schottky-Metal/${p}$ -GaN/AlGaN/GaN Device Under Forward Bias

In this letter, we investigated the electroluminescence (EL) spectra and photovoltage spectrum of a Schottky-metal/p-GaN/AlGaN/GaN diode with a semitransparent anode electrode. By analyzing the bias-dependence of the EL spectra of the diode as well as the gate stress bias-/time-dependences of the threshold voltage shift of a p-GaN gate HEMT, the electron/hole injection sequence, electron trapping, hole-assisted de-trapping, and optical pumping processes in the p-GaN gate region are identified. The band diagrams of the Schottky-metal/p-GaN/AlGaN/GaN heterostructure under different forward bias voltages are proposed.

Frequency- and Temperature-Dependent Gate Reliability of Schottky-Type ${p}$ -GaN Gate HEMTs

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage ( I–V ) characteristics and threshold voltage ( ${V}_{\text {TH}}$ ) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier.