HBT Performance Research Articles

Simulation and analysis of the single event transient characteristics of SiGe HBT at low-temperature environment

This study investigates the temperature dependence of single event transient (SET) effects in silicon germanium heterojunction bipolar transistors (SiGe HBTs). Using Silvaco TCAD simulations, we analyze the influence of linear energy transfer (LET), emitter bias voltage, and striking angle across a temperature range from 100 K to 300 K. The results reveal that temperature significantly affects emitter pulse current and charge collection induced by heavy ions. Higher temperatures increase charge collection, while lower temperatures correspond to higher emitter current and shorter pulse width. The study also observes an increase in bandgap energy (from 1.12 eV to 1.16 eV) and electrostatic potential (from 1.19 V to 1.25 V) with decreasing temperature. The study highlights the crucial role of temperature in SiGe HBT performance under radiation threats and emphasizes drift and diffusion mechanisms as dominant for charge collection.

Perspectives on How the "Sige, Ge, & Related Compounds: Materials, Processing, and Devices" Field Has Changed over the Last 20 Years

The field of electronic devices and materials has seen major changes over the last ~20 years. The SiGe, Ge, & Related Compounds: Material Processing, and Devices symposium has documented much of this change. In 2004 the meeting grew out of a desire for the ECS to have a special ongoing symposium on SiGe & Ge as a materials system with increasing importance in silicon semiconductor technology. In 2008 the symposium was expanded to include Ge and Related compounds including SiC and III-Vs on Silicon to recognize the important work in these areas. In 2010 the symposium was expanded to include work in nano-wires, nano-membranes, and light emitting structures with SiGe and/or Ge. In 2012 the symposium explored finfet devices and expanded to include the area of GeSn. In 2014 the symposium explored the use SiGe and related compounds in more complex and advanced structures. In 2016 the conference had a theme around SOI and the FDSOI technology in particular. In 2018 the themes were the ever expanding device structures and role epitaxy has played in it.Each year the plenary talks were selected to give a view of the industry and the conference. These talks give us insight into the symposium and how the field has changed over time.In 2004 the first symposium “SiGe 1: Materials, Processing, and Devices” focused on the SiGe HBT transistor performance and SiGe epitaxial technology. But CMOS scaling was also presented. These trends were reflected in the plenary talks were given by John Cressler on “Using SiGe HBTs for Mixed-Signal Circuits and Systems: Opportunities and Challenges” and Judy Hoyt on “Enhanced Mobility CMOS.” This was the first symposium and we set the conference organization with multiple topical committees and published the first proceedings.In 2006 the “SiGe and Ge 2” symposium continued the themes of SiGe and Ge Epitaxy, SiGe HBT, CMOS scalling, and added silicon photonics. The Plenary talks were given by Dimitris Antoniadis on “Channel Material Innovations for Continuing the Historical MOSFET Performance Increase with Scaling” and Cary Gunn on “CMOS Photonics for High Speed Interconnects.”In 2008 the “SiGe, Ge, & Related Compounds 3” symposium changed in composition bringing IIIV and other compounds into the symposium. The Plenary papers were by Krishna Saraswat on “Germanium for High-Performance MOSFETS and Optical Interconnects,” and Wiebe B. de Boer on “Si and SiGe Epitaxy in Perspective.” Krishna focused on the role of Ge in modern devices and Wiebe focused on the history of SiGe epitaxy at ASM.In 2010 the “SiGe, Ge, & Related Compounds 4” greatly expanded topics while maintaining the core of SiGe HBT and CMOS scaling. The plenary papers were given by K. Kuhn on “Past, Present, and Future: SiGe and CMOS Transistor Scaling” and L. Kimmerling on “Scaling Energy and Form Factor with Germanium Microphotonics.” The conference emphasis continued on SiGe epitaxy, CMOS scaling, and HBT performance with a new optoelectronics focus area.In 2012 the “SiGe, Ge, & Related Compounds 5” focused on the finfet and GeSn. The plenary papers were given by E. Nowak “Advanced CMOS scaling and FinFET Technology” and C. Hu on “FinFET and UTB – How to make very short channel MOSFETs.” There were 4 sessions containing papers with GeSn.In 2014 the “SiGe, Ge, & Related Compounds 6” returned to CMOS scaling and the SiGe HBT. The plenary papers were given by K. Uchida and T. Takahashi on “Extending the FETs: Challenges and Opportunities for New Materials and Structures” and L. Zimmermann (IHP) on “High-Performance Photonic BiCMOS – Next Generation More-than-Moore Technology for the Large Bandwidth Era.”In 2016 the “SiGe, Ge, & Related Compounds 7” focused on FDSOI. The plenary papers were given by Bruce Doris “FDSOI Past, Present and Future” and Carlos Mazure and S. Cristoloveanu “ FD-SOI: The History from Early Transistors to Today.”In 2018 the “SiGe, Ge, & Related Compounds 8” focused on CMOS scaling and SiGe as an enabling material. The plenary papers were given by Maszara, Witold on “Contemporary and Future Logic Devices” and by Tsu-Jae Liu on “ Silicon-Germanium: Enabler of Moore's Law.”In 2020 the “SiGe, Ge, & Related Compounds 9” symposium focused on III-Vs and Silicon Photonic Sensors. The plenary papers were given by N. Collaert on “The revival of compound semiconductors and how they will change the world in the 5G/6G era,” and Ben Miller on “Creating the Interface Universe between the Universe and Data with Integrated Photonic Sensors."Highlights from these plenary talks and symposium topics will be presented.

High Performance SiGe HBT Performance Variability Learning by Utilizing Neural Networks and Technology Computer Aided Design

Process sensitivity and variation, such as layer thicknesses, etch dimensions and doping levels are all process parameters that should be well understood when assessing their impact on end of process wafer quality and device performance. Improvements in uniformity of electrical device performance is often not taken into major consideration until a certain maturity level of a technology is reached. In this work, use of technology computer aided design (TCAD) and process compact models (PCM) developed from neural networks demonstrate their utility in process- parameter variation understanding in earlier stages of technology development. A TCAD simulation was built and calibrated to match key electrical performance metrics of an experimental high performance SiGe HBT in 130nm BiCMOS technology, which was the device of focus in this study. Figure 1 includes a TCAD cross section of the device1. Neural net techniques, a machine-learning methodology, the development and deployment of which has grown significantly over the last three decades, is used to expand the scope of TCAD to process variability2-3.The aforementioned calibrated TCAD deck was used to generate training data for the neural network process compact model in place of hardware data. Key process features, as listed in table 1 were a few of the process conditions that were varied from nominal values to characterize the variation in resulting electrical performance. Figure 2 includes a 1D schematic view of the epitaxial layers of the HBT, highlighting some of the process features varied in simulation. The neural network was trained using a data analysis suite using three hidden layers with 16 neurons each to get a best fit to the training data input and output values.The foundation of this approach was a TCAD simulation calibrated to match performance of the nominal HBT device of focus. Key AC and Gummel performance parameters had good agreement with hardware data as illustrated in Figure 3a and b. Thousands of individual TCAD simulations with combinations of varied process feature values were then executed to generate neural network training data in lieu of hardware data- utilizing reported standard deviations of each process parameter. The trends and sensitivity of this data was then reflected in the process compact model, which would provide results for large-scale calculation and analysis. Beta was the electrical parameter of focus in this study, where its changes in process variation (mean and standard deviation) were predicted by the trained PCM. The agreement with hardware electrical parameter Beta with respect to Boron dose in Figure 4 demonstrates how use of calibrated TCAD as a basis can empower prediction of large-scale hardware results without the extent of hardware expense. Use of this tool can be extended to simulate and analyze larger populations than what would be feasible for hardware (in several thousands) to predict the effect of process input changes on uniformity of electrical parameters. Figure 5 demonstrates how the changes in standard deviation of Beta can be predicted as a function of Boron dose variation-through generation of large simulated populations by the PCM.The resulting work on a state-of-the-art SiGe BiCMOS technology demonstrates how specific simulation tools, like TCAD-trained process compact models can be leveraged for enhanced process understanding and improvement. The data generated from these tools can supplement or replace hardware and corresponding data, saving in development costs and associated hours in manpower. They can also enable earlier and more agile decision-making about key production metrics throughout the technology development process. Calibrated TCAD infrastructure, coupled with neural-net technology have potential to fulfill pivotal roles through the timelines of technology development, rather than just being utilized when a technology is mature.

High Performance SiGe HBT Performance Variability Learning by Utilizing Neural Networks and Technology Computer Aided Design

Improvements in uniformity of electrical device performance is often not taken into major consideration until a certain maturity level of a technology is reached. In this work, use of technology computer aided design (TCAD) and process compact models (PCM) developed from neural networks demonstrate their utility in process-parameter variation understanding in earlier stages of technology development. A third generation High Performance Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT) was modelled and simulated as the device of focus in this study.

TCAD Calibration of High-Speed Si/SiGe HBTs in 55-nm BiCMOS

We present and discuss in this paper the challenges and solutions to calibrate the TCAD of high-speed DPSA-SEG Si/SiGe HBTs in 55-nm BiCMOS (B55) [1]. Both fabrication process and physical device calibration are addressed using the Sprocess and Sdevice modules of Synopsys®. A careful calibration of the fabrication process in 2D-TCAD is mandatory to simulate accurately the SiGe HBT performance. The first step is to reproduce precisely the device geometry captured with TEM pictures (see Fig. 1). Additional TEM analyses performed during the fabrication may also be required to fit perfectly the final transistor. Secondly, the vertical doping profile is calibrated both from SIMS (for As, Ge and B) and EDX (for As and Ge) measurements. EDX measurements in the transistor are increasingly important to capture the variation of the 1D doping profiles with the emitter width (cf. Fig. 2). In order to reproduce this effect, the injection of defects during the SiGe:C epitaxy has been implemented in TCAD simulation. In fact, the injection of interstitials and vacancies, which depends on the silicon area exposed during the growth, influences directly the Ge diffusion of the 2D doping profile. EDX measurements are also helpful to calibrate the lateral diffusions for the 2D doping profile. Even when these vertical profiles are well calibrated, the simulation of f MAX, R BX and C BC for DPSA-SEG architecture is still challenging due to the complexity of the base link formation, which includes the faceting at the edge of SiGe:C intrinsic base and the shallow trench isolation (STI), the boron diffusion through polycrystalline / monocrystalline interface, and hidden defects. Therefore the base link formation is simplified by skipping the faceting effect and the boron diffusion through the base link interface is analyzed through inspection of R BX, C BC and f MAX i.e. by a reverse engineering approach [2]. Resulting (f T, f MAX) performance presented in Fig. 3 match the measurements for the calibrated electrical model (see below). It will be shown in the extended paper that the impact of SiGe:C epitaxy growth temperature on the base thickness is well simulated. Considering now the electrical/physical device calibration, the following physical models are used in the B55 TCAD deck: - HD parameters [3] - Bandgap (BG) of SiGe structure and bandgap narrowing (BGN) [4] - Energy and relaxation time, mobility [5] - Intrinsic carrier densities, saturation velocity [6] - Default SRH, surface SRH and Auger models from Synopsys TCAD [7] - Default Lackner model for impact ionization from Synopsys TCAD [7]. The calibration of these models for each technology node is mandatory to match the electrical measurements. A sensitivity analysis approach has been used to adjust some model parameters in order to figure out which physical model has the largest impact on the different electrical performances. The resulting map of the impacts of the different physical models, which will be presented in the extended paper, provides precious information for TCAD calibration of current and future SiGe HBTs technology at STMicroelectronics. In conclusion, obtained 2D-TCAD electrical results fit well I B, I C, f T, f MAX and BV CEOmeasurements. The accuracy of TCAD simulation will be discussed in more detail in the extended paper. References P. Chevalier et al, IEDM Tech. Dig., pp. 77-79, (2014)T. Rosenbaum, O.Saxod, V. T. Vu, D. Celi, P.Chevalier, M. Schröter and C. Maneux, Proc. IEEE BCTM, 64-67, (2015).G. Wedel and M. Schröter, Proc. IEEE BCTM, 237-244, (2010).D. B. M. Klaassen, J. W. Slotboom, H. C. De Graaff, Solid-state Electronics, 125-129 (1992)M. Michaillat, Ph.D thesis, Université Paris-Sud 11, (2010)G. Sasso, N. Rinaldi, G. Matz, C. Jungemann, Proc. IEEE SISPAD, 279-282, (2010) Sdevice documentation from Synopsis. Figure 1

0.8/2.2-GHz Programmable Active Bandpass Filters in InP/Si BiCMOS Technology

Programmable active bandpass filters (BPFs) have been designed in a chip-scale heterogeneous integration technology, which intimately integrates InP HBTs on a deep scaled CMOS technology. Therefore, the active BPF can leverage both high performance of InP HBT and high density and programmability of CMOS. Two BPF prototypes, consisting of a programmable gain amplifier (PGA), a fifth- or third-order BPF core, and a buffer, have been designed and fabricated. The BPF center frequency can be switched from 0.8 to 2.2 GHz with 150-MHz passband and delivers > 55-dB out-of-band (OOB) rejection for the fifth-order one. Four gain steps: 0, 6, 12, and 16 dB, are enabled by the front PGA to trade off noise and linearity performances. Due to the > 300-GHz f T of InP HBTs, the BPF cores can leverage active-RC architecture for high linearity owing to the close-loop implementation. The fifth-order BPF prototype occupies a 1.5 × 1.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area together with pads and draws 106/121 mA from a 3.3-V power supply for 0.8/2.2-GHz bands, respectively, which demonstrates OOB output third-order intercept points (OIP3s) of 22.69/21.25 dBm for 0.8/2.2-GHz bands at the high gain mode. The measurement results suggest the fifth-order BPF core achieves 36.69/35.25-dBm OOB OIP3s. In addition, the designed third-order programmable BPF has been successfully used as a technology yield vehicle to assist the BiCMOS technology development.

A 32 nm NPN SOI HBT with Programmable Power Gain and 839 GHzV ftBVCEOProduct

The performance of npn SiGe HBT on thin film SOI is investigated at 32 ㎚ technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 ㎚ FDSOI technology having 10 ㎚ film thickness and 30 ㎚ BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V VCE has very high ftBVCEO product (839 ㎓V). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 ㏈) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 ㎚ SOI CMOS (usually voltage gain is in the range of 10-20 ㏈).

A Technique to Improve the Performance of an NPN HBT on Thin-Film SOI

The performance of an npn SiGe HBT on thin-film silicon on insulator (SOI) is investigated using 2-D numerical simulation. A technique of using N+ buried layer has been presented to improve the performance of an SiGe HBT on thin-film SOI. The tradeoff in the performance of HBT has been observed and the results are compared to the standard SOI HBT. The HBT offers better βV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> product at high collector currents. A 341 GHzV of f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> product can be obtained by using this technique. The scalability of film thickness is applied and the enhancement in the speed is observed. The self-heating performance of the proposed HBT is studied and the BOX thickness has been scaled to improve the thermal performance. The maximum lattice temperature is obtained. The proposed HBT is suitable for RF applications and can be used in addition to the existing 130 nm SOI CMOS technology for better performance.

Understanding the Effects of Epitaxy Artifacts on SiGe HBT Performance through Detailed Process/Device Simulation

Faceting at the periphery of the shallow trench isolation during SiGe epitaxial base growth and its influence on SiGe HBT collector-base capacitance are investigated utilizing Technology Computer Aided Design techniques. The simulations suggest peripheral diffusion of boron from the extrinsic base into the intrinsic device may be attributed to depletion of germanium and carbon on the faceted plane that drives the boron diffusion and contributes to the collector-base capacitance, Ccb. Increases in the angle of the facet relative to the {110} plane are shown to reduce Ccb. Moreover, a significant reduction in Ccb was observed with no faceting, suggesting that moving the facet away from the active silicon region was desirable for reducing this key parasitic capacitance. These results serve to highlight the role that faceting plays in extrinsic device parasitic capacitances and identifies a focus area for scaling the device capacitance.

Understanding the Effects of Epitaxy Artifacts on SiGe HBT Performance through Detailed Process/Device Simulation

not Available.

Relative Analysis of Speed and Noise Performance of SiGe HBT Between Experimental and Simulated Model

Speed and Noise performance of SiGe HBTs in terms of the cut off frequency and the noise figure is investigated by ATLAS software. Noisy transistors disgrace the performance of mobile wireless receivers and put off amplifiers and oscillators from meeting the rigorous requirements forced on them while working at frequencies in the GHz range. Small noise improvements at the device level can have a large blow on overall system presentation. In this paper, a model is projected for speed and noise analysis of SiGe HBTs that is implemented in software ATLAS from SILVACO international and analyzed all the way through a thorough method. The results of experimental and simulated model has been compared and contrasted.

Considerations of dopant-dependent bandgap narrowing for accurate device simulation in abrupt HBTs

Heavy doping of the base in HBTs brings about a bandgap narrowing (BGN) effect, which modifies the intrinsic carrier density and disturbs the band offset, and thus leads to the change of the currents. Based on a thermionic-field-diffusion model that is used to the analyze the performance of an abrupt HBT with a heavy-doped base, the conclusion is made that, although the BGN effect makes the currents obviously change due to the modification of the intrinsic carrier density, the band offsets disturbed by the BGN effect should also be taken into account in the analysis of the electrical characteristics of abrupt HBTs. In addition, the BGN effect changes the bias voltage for the onset of Kirk effects.

An Evaluation of Transistor-Layout RHBD Techniques for SEE Mitigation in SiGe HBTs

We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from the sub-collector to substrate junction. The inclusion of the n-ring affects neither the DC nor AC performance of the SiGe HBT and does not compromise its inherent multi-Mrad TID tolerance. The effects of ion strike location and angle of incidence, as well as n-ring placement, area, and bias on charge collection are investigated experimentally using a 36 MeV O2 microbeam. The results indicate that charge shunting through the n-ring can result in up to a 90% reduction in collector collected charge for strikes outside the DT and a 18% reduction for strikes to the emitter center. 3-D transient strike simulations using NanoTCAD are used to verify the experimental observations, as well as shed insight into the underlying physical mechanisms. Circuit implications for this RHBD technique are discussed and recommendations made.

Investigation of the impact of band offset perturbations on the performance of abrupt HBT with heavily doped base

Heavy impurity doping leads to bandgap narrowing (BGN) and this causes perturbations to the value of the band offsets at the hetero-interface. As a result, the form and height of energy barriers in abrupt HBT is disturbed, which changes the value of the current flowing through its interfaces. The analysis is based on the thermionic field-diffusion model which combines the drift-diffusion transport in the bulk of the transistor with the thermionic emission and tunneling at the base-emitter interface. The calculations reveal a more important role to the transport of carriers played by the modification of the built-in potential than that of the range of barrier energies available for tunneling because the impact of the built-in potential on the current is exponential. Therefore, it is important for a better description of the currents to use an accurate dopant-dependent BGN distribution model between bands.

Integration of Photonic Detectors in Standard SiGe HBT BiCMOS

The currently emerging optical data storage technologies of Blu-Ray Disk, respectively High Density Digital Versatile Disk (HDDVD), have opened a new field of activity for photodetectors preferentially integrated in a SiGe heterojunction transistor (HBT) BiCMOS process platform. Besides the advantages this process offers for analog signal processing we show how HBT process modules can be used to integrate fast, high-responsivity photodetectors sensitive to blue, red and near-infrared light of wavelengths 405, 660 and 785nm, respectively. The tradeoffs made for tuning HBT performance are discussed with respect to their impact on photodiode performance. The integration of the photodetector can be carried out with layout changes only not altering any other process step making it therefore an easy-to-do and free- of-extra-cost extension of the HBT BiCMOS base process.

Wet etching for improved GaN‐based HBT performance

Photoenhanced wet etching of GaN in a peroxydisulfate aqueous solution has been used in npn HBT device fabrication. The wet etch acts as a selective etch for n-type layers, where the p-type layer acts as an etch stop. This allows the use of thinner base layers in an npn structure. No counter electrode or electrical connection to the wafer is required with the approach. We present experimental results on the fabrication of BJTs and HBTs using this self-aligned wet etching. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Suppression of the burn-in effect in InGaP/GaAs heterojunction bipolar transistors by constant period of voltage stress

Two significantly abrupt increases of dc current gain (β) at the opposite extremes of base-emitter voltages (Vbe) linked by a relatively slight increase of β in the range of 1.25⩽Vbe⩽1.75 V are found in InGaP/GaAs heterojunction bipolar transistors (HBT’s). It has been proved that the burn-in effect directly causes the second abrupt increase of β occurring at Vbe&amp;gt;1.75 V instead of elsewhere. In addition, choosing Vbe&amp;gt;1.75 V, a higher base-emitter voltage results in a faster increase rate with improvement in current gain transient. Based on these observations, a constant period of voltage stress (CPVS) with Vbe=2.0 V and Vce=3.0 V for 5 min with a specific choice of Vbe&amp;gt;1.75 V (the voltage range corresponding to the second abrupt increase of β) is thus applied to promote the electrical performance of HBT’s. After applying a CPVS, the burn-in effect is substantially suppressed without showing any second abrupt increase of current gain. Although the current measured under both reverse and forward biases is greatly reduced for the base-emitter junction, a CPVS slightly degrades the electrical properties of a base-collector junction. Also, it has been proved that bulk recombination, rather than the surface recombination current, the base contact recombination, or the space-charge recombination, is the dominant base current component causing the burn-in effect. The electrical improvement of the base-emitter junction is due to the annihilation of H-related traps in the base region after a CPVS. Once H− ions form, we propose that these ions are too fast to drift toward the base-collector junction under the reverse bias of the base-collector voltage. After migration through the extrinsic base region, H− ions are supposed to be trapped near the base-collector space region, which results in the degradation of the base-collector junction after a CPVS.

2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI

We report a novel BiCMOS compatible lateral SiC N-emitter, SiGe P-base Schottky metal-collector NPM HBT on SOI. The proposed lateral NPM HBT performance has been evaluated in detail using 2-dimensional device simulation by comparing it with the equivalent NPN HBT and homojunction silicon NPM BJT structures. Based on our simulation results, it is observed that while both the lateral NPM and NPN HBTs exhibit high current gain, high cut-off frequency compared to the homojunction NPN BJT, the lateral NPM HBT has the additional benefit of suppressed Kirk effect and excellent transient response over its counterpart lateral NPN HBT. The improved performance of the proposed NPM HBT is discussed in detail and a CMOS compatible process is suggested for its fabrication.

Effects of neutron irradiation on SiGe HBT and Si BJT devices

The change of electrical performance of SiGc HBT and Si BJT is studied after irradiation with 1.3×1013 and 1.0×1014 reactor fast neutrons cm−2. Ic and β decrease, while Ib increases generally with an increasing neutron irradiation fluence for SiGe HBT. For Si BJT, Ic increases at low Vbe bias, decreases at high Vbe bias; Ib increases; and β decreases much more than a SiGe HBT at the same fluence. It is shown that a SiGe HBT has much better anti-radiation performance than a Si BJT. The mechanism of performance changes induced by irradiation is discussed.

Extrinsic base optimization for high-performance RF SiGe heterojunction bipolar transistors

A comprehensive study on the effect of extrinsic base optimization on the RF performance of an advanced SiGe HBT is presented. An optimized extrinsic poly base with its interface to the epi-base passivated by boron ions is demonstrated to enhance the f/sub max/ and the current gain almost two times and to reduce the low-frequency 1/f noise ten times and noise figure (NF) 0.5 dB, achieving f/sub max/ of 45 GHz, 1/f noise corner frequency of 700 Hz at I/sub B/=1.0 /spl mu/A, NF/spl les/1.0 dB at 900 MHz. Early voltage V/sub A/ of /spl ges/200 V is achieved, while maintaining a BV/sub CEO/ of /spl ges/8.0 V.