Harmonic Rejection Technique Research Articles

A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS

This work presents a wideband digital polar transmitter (DPTX) with an integrated capacitor-digital-to-analog converter (C-DAC)-based digital-to-phase converter (DPC). A normalized CORDIC algorithm is introduced to convert the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> baseband signals to a constant envelope to overcome the PM bandwidth expansion issue and avoid the amplitude modulation (AM)–phase modulation (PM) nonlinearity. In the DPC, the switched-capacitor DAC topology is employed for good linearity, and the eight-phase cell-reused technique is proposed to reduce the power consumption and increase the phase amplitude. Besides, the harmonic rejection technique is introduced to remove the third-/fifth-order and higher order local oscillator (LO) harmonics to maintain phase linearity. A broadband switched-transformer digital power amplifier (DPA) is adopted in this proposed DPTX for 0–18-dB deep power back-off efficiency enhancement. Implemented in 40nm CMOS, the DPTX is powered by only one 1.1-V supply and occupies a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.4 \times 1.4$ </tex-math></inline-formula> mm2 die area. The DPC achieves the maximum integral nonlinearity (INL)/differential nonlinearity (DNL) of ±1°/±0.8° and 12.7-mW power consumption at 1.5 GHz. The DPTX realizes wideband frequency coverage of 1.2–2.5 GHz with only 0.7-dB power variations. The DPTX achieves 20.1-dBm peak output power with 23.7% system efficiency at 1.5 GHz. With a 10-MHz 64-quadrature amplitude modulation (QAM) LTE signal, the DPTX achieves 15.0 dBm average output power, 15.2% system efficiency, and an error vector magnitude (EVM) of −28.6 dB at 1.5 GHz.

A New Analog-based LO Harmonic Rejection Technique with Tunable Notch Frequency

An effective technique for mixer LO harmonic rejection in a SAW-less wideband receiver front-end is proposed. The proposed technique provides a tunable notch that can be placed at any frequency like mixer LO harmonics, to avoid the aliasing in baseband after mixing. An analog LC notch is used in a cascode transconductor, and it can reject one of the 3rd or 5th harmonics. This notch frequency is tunable using the bond wire inductors or fixed Gyrator-C active inductor, and a capacitor array, without any significant Power/Area overhead on overall system. Since the accurate value of inductance is not clear, a calibration circuit is proposed to tune this LC notch. This tuning phase runs in forground, and consumes very low additional power. This technique is used in a wideband receiver front-end. Post-layout simulation in 130nm CMOS results in an average 3rd harmonic rejection ratio of 36 dB. The overall circuit consums 34mW power and a has a noise figure of 3.4dB at 1GHz frequency.

A Wideband Linear &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$I/Q$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Interleaving DDRM

This paper presents a wideband linear direct-digital RF modulator (DDRM) in 40-nm CMOS technology. An innovative $I/Q$ -interleaving RF digital-to-analog converter (DAC) is proposed to enable the combination of in-phase ( $I$ ) and quadrature ( $Q$ ) signals in a more digital fashion, thereby improving the linearity performance at large bandwidths. The DDRM also features an advanced second-order hold digital interpolation filter to suppress the sampling spectral replicas in the presence of large bandwidth signals. Moreover, the harmonic rejection technique in the context of RF DAC operation is adopted and implemented. The $2 \times 9$ -bit DDRM core occupies 0.21 mm2 and consumes 110 and 146 mW at 1 and 3 GHz, respectively, with the peak power of +9.2 dBm. The error vector magnitude (EVM) and adjacent channel power ratio (ACPR) at 3 GHz for a 57-MHz 64-QAM signal are better than −30 and −45 dB, respectively, and ACPR remains as low as −44 dBc up to a wide bandwidth of 113 MHz.

K band class‐C MESFET based frequency quadrupler with highly selective SIW bandpass filter for inter satellite communication

ABSTRACTThis article presents the single stage active frequency quadrupler design for generating a tone in the K band (23.5 GHz) frequency range using GaAs MESFET device. Harmonics current generation characteristics of GaAs MESFET (NE900000) is modeled and analyzed in reference with gate voltage. Based on this, its optimum operating class‐C is decided for its application as a frequency quadrupler. Using this model and introducing resonator (Idler) based harmonic rejection techniques, a narrowband −0.310 dBm output power ×4 frequency multiplier from C‐band to K‐band implemented using 0.5 μm GaAs MESFET. As the device operated in class‐C operating condition, it produces harmonics content due to clipping of output signal. At the output of the proposed multiplier design, a highly selective surface integrated waveguide (SIW) based bandpass filter (with Q is better than 120) is attached, which provides excellent rejection of fundamental component (&gt;90 dBc) and other harmonics assuring minimum rejection of 30 dBc. The proposed design consumes 60 mW power and provides ∼−7 dB conversion gain with input power having 7 dBm. Feasibility and layout geometry of the proposed design has been evaluated and simulated on the substrate RT‐Duroid5880 using Agilent ADS software. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:767–776, 2016

A CMOS LNA Using a Harmonic Rejection Technique to Enhance Its Linearity

In this study, we design a differential low-noise amplifier (LNA) using a 0.18- μm RF CMOS process. To improve its linearity, we propose a harmonic rejection technique using RC feedback at the gain stage. The third harmonic component of the drain node of the common-gate transistor is fed back to the source node of the common-gate transistor to restrict the generation of the third harmonic component at the output of the LNA. To verify the feasibility of the proposed technique for a linear amplifier, we designed a typical LNA and the proposed LNA in an identical process and with the same design parameters apart from the feedback loop of the proposed LNA. The measured improvement of the input-referred P1 dB of the proposed LNA is approximately 3 dB compared to that of the typical LNA. From these measured results, we successfully prove the feasibility of the proposed linearization technique.

Tunable wideband SAW-less receiver front-end in 65 nm CMOS

A surface acoustic wave-less receiver front-end for GSM, TD-LTE and TD-SCDMA standards featuring a novel low noise amplifier (LNA) architecture and harmonic rejection technique is presented. The tw...

Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS

A wideband direct-conversion receiver front-end featuring a new harmonic rejection technique is demonstrated in 65-nm CMOS. The circuit consists of a two-stage low-noise amplifier, the first stage with capacitive feedback, a harmonic rejection mixer using 25% and 50% duty cycle local oscillator signals, and a third-order channel-select filter with configurable bandwidth. The receiver front-end is intended for surface-acoustic-wave-less cellular applications, and its performance was measured at 900- and 1800-MHz bands. The average harmonic rejection over GSM and LTE channel bandwidths is between 60 and 70 dB. Peak harmonic rejection exceeds 80 dB. The noise figures (NFs) are 3.3 and 3.9 dB for the complete receiver front-end in low band and high band, respectively, with an S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> below -15 dB from 500 MHz to 2.5 GHz. The 1-dB received signal compression points with a blocker present at 20/80 MHz offset for low/high band are 0 and +2 dBm, respectively. The NF with 0-dBm blocker is 13 dB. For low band, the in-band IIP3 and IIP2 are -14.8 and > 49 dBm, respectively, and, for high band, -18.2 and > 44 dBm. The circuit worst case consumes 80 mW of power.

Analysis and design of an X-band-to-W-band CMOS active multiplier with improved harmonic rejection

Third-harmonic current generation in a CMOS transistor is modeled and analyzed including the effects of large-signal clipping and high-frequency roll-off for the application of millimeter-wave (mm-wave) frequency multipliers. Using the model and introducing harmonic rejection techniques, a wideband 8.5-dBm output-power x9 frequency multiplier from X-band to W-band implemented using a 65-nm CMOS process is designed and characterized. Six transformer coupled differential stages are used, two tripler stages, a Ka-band amplifier, and a three-stage W-band power amplifier (PA). The circuit reaches a saturated output power of 8.5 dBm at 91.8 GHz with a 12.2% bandwidth from 88 to 99.5 GHz. Excellent suppression of unwanted harmonics is achieved with better than 31 dBc across all bandwidth. The core design occupies only 390 μm × 675 μm and consumes 438 mW from a 1.2-/2.4-V supply.

A 4.8-mW 4-GHz CMOS Class-B-Like Down-Converter for Harmonic Mixing Rejection

In a wideband receiver, higher frequency channels may be converted to the frequency of a desired signal by a harmonic mixing mechanism. To alleviate this issue, this paper proposes a topology, called the classBlike converter, to achieve high harmonic mixing rejection in frequency translation without any filtering. The converter is based on a linear commutation with a sinusoidal local oscillator for a small harmonic mixing, while its gain and noise performances are comparable to that of a switching-type converter. Most important, the circuitry of the proposed converter is simple and can be incorporated with other harmonic rejection techniques. The circuit is implemented with a 0.18-μm 1.8-V CMOS technology and the power consumption is 4.8 mW. Measurement results indicate that the third- to ninth-order harmonic rejections are more than 45 dB in average within a 4-GHz frequency range. A polyphase prototype with the proposed converter achieves higher than 70-dB third-order harmonic rejection even under a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> phase and 2% gain mismatch.

Harmonic Signal Rejection Schemes of Polyphase Downconverters

The harmonic signal rejection capability and the rejection schemes of polyphase downconverters are discussed. An analysis of a simple model of a polyphase downconverter shows that n -phase converter can reject up to (n-2)th harmonic signal, and that (n-1)th harmonic signal aliases into the desired signal. It means that the harmonic rejection is not exclusive ability of downconverters with large number of phases, and conventional downconverters with fewer phases have the ability. An example is a differential amplifier type downconverter (n=2), which has the ability of even harmonic signal rejection as common-mode signal. In this paper, the common-mode concept is extended to polyphase circuits. It is named “partial common mode,” because it does not have to be common for all node but is common for a part of nodes. The partial common-mode rejection is effective for harmonic rejection. There is the other type of harmonic rejection techniques for polyphase downconverters, i.e., signal weighting-and-summing type. Comparison between the harmonic rejection with weighting-and-summing circuit and that with the common-mode rejection circuit is discussed, too. Due to its simple structure, a 6-phase downconverter with partial common-mode rejection is attractive for practical wideband receivers.