Virtual Hardware Research Articles

Virtualization for high-performance computing

The specific demands of high-performance computing (HPC) often mismatch the assumptions and algorithms provided by legacy operating systems (OS) for common workload mixes. While feature- and application-rich OSes allow for flexible and low-cost hardware configurations, rapid development, and flexible testing and debugging, the mismatch comes at the cost of --- oftentimes significant --- performance degradation for HPC applications.The ubiquitous availability of virtualization support in all relevant hardware architectures enables new programming and execution models for HPC applications without loosing the comfort and support of existing OS and application environments. In this paper we discuss the trends, motivations, and issues in hardware virtualization with emphasis on their value in HPC environments.

Power, Knowledge and Virtuous Organizations: Virtuous College and Virtuous War

This essay will explore the links between power, knowledge, and the discourse of technological virtue in two cases of organizational innovation: the Land Grant College movement of the 1850s and the Revolution in Military Affairs (RMA) of the 1990s. Both movements can be seen as responses to ontological or spiritual rifts that opened between how we live and how we recognize goodness in ourselves. In the case of Land Grant Colleges, there was a realization that God's gift of an abundant continent upon which to faithfully labor and prosper was being despoiled by labor and prosperity. Scientific agriculture was intended to restore Americans to virtue. The Revolution in Military Affairs likewise might be seen as an attempt to maintain images of virtue under difficult conditions. James Der Derian characterizes virtuous war as a neural network which links virtual technologies, military hardware, entertainment, global surveillance, and information with the ethical imperative to inflict virtuous violence from a distance with minimal American casualties. This essay will explore the question of how public administration might respond to the discourse of virtuous power/knowledge.

Methodologies for the use of VMware to boot cloned/mounted subject hard disk images

This paper represents part of the work that was submitted for the RMCS Shrivenham/Cranfield University MSc in Forensic Computing in March 2005. An investigation into the restoration of forensically acquired digital data to virtual hardware was undertaken. The objective of the investigation was to devise a methodology by which a subject operating system could be booted in a virtual environment. This would enable the investigator to experience the subject system in a controlled environment where file system changes could be discarded and the ‘original’ clone preserved for future, repeatable usage. During the research and experimentation stages of this project, the following software was utilised: • Encase 3.22g was the primary forensic imaging tool. • Mount Image Pro 1.05 was used to mount the forensic image files as a physical disk. • Symantec Ghost 2003 was used to clone the physical disk to a new virtual disk. • VMware 4.5.2 build-8848 was the virtual machine software used. The underlying architecture of VMware is Intel based. • Microsoft Windows XP was used as the host examination system. During the research phase of this project, the host examination machines utilised both Intel and VIA (AMD processor) architectures.

The virtual test lab

Systems companies today face increasingly complex and expensive testing challenges that require innovative solutions. One approach to address the problem uses full-system simulation with virtual hardware early on and throughout the development process. Recent technological advances in virtualization now satisfy the demands of software development, enabling the construction of a software model of the complete system that can run on the developer's desktop PC. Virtualization is so accurate it can run the fabled golden code - the actual binary that ships in the final product. A virtual test laboratory can simulate not only the system being tested but also the other systems it interacts with.

Software Distributed Shared Memory: a VIA-based implementation and comparison of sequential consistency with home-based lazy release consistency

A Distributed Shared Memory (DSM) system provides a distributed application with a shared virtual address space. This article proposes a design for implementing the DSM communication layer on top of the Virtual Interface Architecture (VIA), an industry standard for user-level networking protocols on high-speed clusters. User-level communication protocols operate in user mode, thus removing the operating system kernel's overhead from the critical communication pass, and significantly diminishing communication overhead as a result. We analyze VIA's facilities and limitations in order to ascertain which implementation trade-offs can be best applied to our development of an efficient communication substrate optimized for DSM requirements. We then implement a multithreaded version of the Home-based Lazy Release Consistency (HLRC) protocol on top of this substrate. In addition, we compare the performance of this HLRC protocol with that of the Sequential Consistency (SC) protocol in which a MultiView (MV) memory mapping technique was used. This technique enables a fine-grained access to shared memory, while still relying on the virtual memory hardware to track memory accesses. We perform an ‘apple-to-apple’ comparison on the same testbed environment and benchmark suite, and investigate the effectiveness and scalability of both protocols. Copyright © 2005 John Wiley & Sons, Ltd.

Seamless mobile computing on fixed infrastructure

The term mobile computing typically evokes images of a laptop, handheld, or wearable computer. However, the plummeting cost of hardware suggests that pervasive computing infrastructure could minimize the need to carry such devices in the near future. Personal computing will be available anywhere on demand, like light at the flip of a switch. Only when a user starts to use a computer will it acquire unique customization and state. When the user finishes using the computer, this customization and state will disappear from it. Thus, a user could travel hands-free yet be confident of making productive use of slivers of free time anywhere. For this to be a compelling vision from a user's viewpoint, the customization and state acquisition process must be accurate and nearly instantaneous. For it to be a viable business model, the management and system administration costs of pervasive deployments of machines must be low. Internet Suspend/Resume is a thick-client approach to mobility in which hardware virtualization and file caching are the keys to rapid personalization of anonymous hardware for transient use.

An innovative software architecture to improve information flow from CAM to CNC

Abstract Over the years, machine tool evolution has allowed faster equipment, using new configurations, to manufacture parts that were almost impossible to machine in the past. Despite this tremendous evolution in machine and control technologies, the metalworking industry is still using the old ISO 6983 G-Codes programming interface to control the motion of these machines. This programming interface is not the most flexible or most appropriate for use by new open-architecture machine controllers and object-oriented high-level machining interfaces such as ISO 14649 (STEP-NC). This work proposes an innovative language, the ‘Base Numerical Control Language (BNCL),’ which is based on a low-level simple instruction set-like approach. The architecture is designed around two concepts: the BNCL virtual machine, which acts as a virtual microprocessor, and the BNCL virtual hardware, which is an abstraction of the machine tool. The language is characterised by its simplicity and flexibility, two qualities that are critical in a market in which the capabilities and performance of machines are constantly improving. The proposed architectural concepts are validated through various computer simulation and physical tests, including performance throughput, trajectory driving, and CNC controller extension capabilities.

Functionally partitioned module-based programmable architecture for wireless base-band processing

A specialised reconfigurable architecture is targeted at wireless base-band processing. It is built to cater for multiple wireless standards. It has lower power consumption than the processor-based solution. It can be scaled to run in parallel for processing multiple channels. Test resources are embedded on the architecture and testing strategies are included.This architecture is functionally partitioned according to the common operations found in wireless standards, such as CRC error correction, convolution and interleaving. These modules are linked via Virtual Wire Hardware modules and route-through switch matrices. Data can be processed in any order through this interconnect structure. Virtual Wire ensures the same flexibility as normal interconnects, but the area occupied and the number of switches needed is reduced.The testing algorithm scans all possible paths within the interconnection network exhaustively and searches for faults in the processing modules. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules.This paper compares various base-band processing solutions. It describes the proposed platform and its implementation. It outlines the test resources and algorithm. It concludes with the mapping of Bluetooth and GSM base-band onto the platform.

Accelerated Co-Simulation of Hardware-Software System Based on Configurable Hardware Accelertor and Selective Simulation

The paper presents new approach to hardware-software co-simulation. It offers extretnely high speed of simulation. Presented solution combines hardware emulation technique with selective hardware simulation. This two methods allow to build precisely tailored hardware accelerated co-simulation system. Systenl allows for full debug of HDL described hardware and software that works together with real part of a design. Software can interact with virtual (HDL described) part of a design. We have introduced an acceleration technique based on selective simulation of virtual hardware. Developed technique maintains simulation time dependencies between virtual hardware and software that allows to keep the same simulation time in hardware and software part of design while reducing computation power required for HDL simulation.

Necessary Tools

This article reviews that the rate of discovery obtained from an experiment or a computational model is enhanced and accelerated by using parallel computing techniques, visualization algorithms, and advanced visualization hardware. The National Institute of Standards and Technology (NIST) in Gaithersburg, MD, team believe that high-performance computing speeds discovery within the sciences. It defines advanced computing methods as those technologies that possess capabilities beyond current state-of-the-art desktop computing. Visualization tools, for example, now extend beyond the three-dimensional computer-aided design model viewable on a desktop computer to include virtual reality software and hardware. A cave automatic virtual environment, called a CAVE, features four walls onto which an image is projected in 3D so that engineers feel they are standing in front of an object. Researchers at Iowa State and NIST’s engineers both say the future of technology won't happen without advanced computing methods, including visualization, virtual reality, and parallel computing.

Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead

The concept of using a microcontroller coupled to re-programmable FPGAs is being used at the heart of Run-Time Reconfigurable (RTR) systems. This paper presents the development of an RTR system for DSP and telecommunication applications. It differs from other systems, in that it treats reconfiguration time as a key design parameter by employing "design for reconfiguration" where partial reconfiguration is identified in the design of the circuit architecture. Reductions of up to 75% in the implementation time of multiplication, division and square root circuits have been achieved using the Xilinx XC6200 FPGA family. A special hardware/software interface called the Virtual Hardware Handler, has also been developed to support the design approach. It vastly simplifies the reconfiguration operation, reducing it to a simple process of passing pointers and data. The approach has been implemented on a windows-based RTR system.

Pipeline Reconfigurable FPGAs

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using the technique of pipeline reconfiguration. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis on PipeRench predicts that it will outperform commercial FPGAs and DSPs in both overall performance and in performance normalized for silicon area over a broad range of problem sizes.

Online frequency domain system identification based on a virtual instrument

System identification is an inherently iterative process. Yet, limited attempts have been made so far to implement the whole identification loop in a single device. This paper discusses the difficulties of the task and presents a solution based on a Matlab toolbox and a set of virtual instruments. During the identification session, the obtained models may call for refinement or validation by new experiments. Using this integrated software-hardware tool, these subsequent experiments can be accomplished online with the identification procedure. As a demonstration, the modeling of a hairdryer is described. The universal applicability of this solution is believed to be guaranteed by the modular architecture of virtual instrumentation and the general definition of the software interface developed. The interface allows combining Matlab-based identification packages with virtual instruments or pure hardware interfaced to Matlab.

IMECO: A Reconfigurable FPGA-based Image Enhancement Co-Processor Framework

In this paper, we present a way to improve the computational speed of image contrast enhancement using low-cost FPGA-based hardware primarily targeted to X-ray images. In particular, we consider an enhancement method that consists of filtering followed by histogram modification. Filtering is done via the high boost filter (HBF) which is based on unsharp masking, and the histogram modification which is based on global histogram equalization (GHE). An image enhancement co-processor, IMECO, concept is proposed that enables efficient hardware implementation of enhancement procedures and hardware/software co-design to achieve high-performance low-cost solutions. The co-processor runs on an FPGA prototyping ISA-bus board. At this stage it consists of two hardware functional units that implement HBF and GHE and can be downloaded onto the board sequentially or reside on the board at the same time. These units represent an embryo of virtual hardware units that form a library of image enhancement algorithms. These algorithms can be easily integrated into software templates. In our trials with chest X-ray images, performance improvement over software-only implementations is more than two orders of magnitude, thus providing real-time or near-real-time image enhancement as required in target applications.

Synchronization and communication in the T3E multiprocessor

This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have learned from the T3D project (the predecessor to the T3E) and the rationale behind changes made for the T3E. We include performance measurements for various aspects of communication and synchronization.The T3E augments the memory interface of the DEC 21164 microprocessor with a large set of explicitly-managed, external registers (E-registers). E-registers are used as the source or target for all remote communication. They provide a highly pipelined interface to global memory that allows dozens of requests per processor to be outstanding. Through E-registers, the T3E provides a rich set of atomic memory operations and a flexible, user-level messaging facility. The T3E also provides a set of virtual hardware barrier/eureka networks that can be arbitrarily embedded into the 3D torus interconnect.

Synchronization and communication in the T3E multiprocessor

This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have learned from the T3D project (the predecessor to the T3E) and the rationale behind changes made for the T3E. We include performance measurements for various aspects of communication and synchronization.The T3E augments the memory interface of the DEC 21164 microprocessor with a large set of explicitly-managed, external registers (E-registers). E-registers are used as the source or target for all remote communication. They provide a highly pipelined interface to global memory that allows dozens of requests per processor to be outstanding. Through E-registers, the T3E provides a rich set of atomic memory operations and a flexible, user-level messaging facility. The T3E also provides a set of virtual hardware barrier/eureka networks that can be arbitrarily embedded into the 3D torus interconnect.

WASMII: An MPLD with data-driven control on a virtual hardware

Through the use of an extended field programmable gate array (FPGA) technology, a large digital circuit can be realized on a relatively small amount of real hardware. Several configuration RAM modules are provided inside the FPGA chip, and the configuration of the gate array can be rapidly changed by replacing the active module. Data for configuration are transferred from an off-chip backup RAM to an unused configuration RAM module. A novel computation mechanism called the WASMII, which executes a target dataflow graph directly, can be proposed on the basis of this “virtual hardware.” A WASMII chip consists of the FPGA for virtual hardware and an additional mechanism to replace configuration RAM modules in a data-driven manner. Configuration data are preloaded in the order assigned in advance by a static scheduling preprocessor. By connecting a number of WASMII chips, a highly parallel system can be easily constructed.

Japanese activities in virtual reality

Most virtual reality hardware in Japan has been imported from the US, and the large-scale applications have focused on games, where Sega Enterprises and Nintendo remain the market leaders. In addition to its successful home video and arcade machines businesses, Sega is moving aggressively into the amusement-park ride market. Outside these markets, Matsushita plans to release three commercial products in spring 1994. One is an immersive system for product showrooms to help Japanese home owners visualize new kitchens before ordering them. Another is a massage chair that uses VR images and sound to help relax users. The third is an exercise bicycle that lets the user cycle through a 3D virtual world while exercising. Many Japanese companies are interested in VR technology as a problem-solving tool. They are making progress in its use in equipment operation. They also realize that the ability to operate devices intuitively by ordinary gesture-like motions can be exploited in many practical fields. This ability could make human-machine interfaces easier, even if these interfaces fall short of outright VR. This article reviews a few recent industry and academic research projects. The current worldwide recession has flattened the overall rate of growth in Japanese research and development spending. Nevertheless, Japan reportedly has approximately 20 major VR research projects, mostly emphasizing communication. Japanese emphases on long-term planning and on targeting development toward specific products are their strengths in this emerging technology. >

Modifying VM hardware to reduce address pin requirements

This paper presents a simple modification of a computing system’s virtual memory hardware that can sharply reduce the number of pins required to transmit address information between a single chip processor and off-chip memory. By partitioning the virtual memory system’s translation lookaside buffer so that the virtual page numbers are stored in a cache on the processor chip and corresponding real page numbers are stored in a set of registers at the memory, it becomes possible to transmit a small index from the processor to memory instead of the page nmnber itself. Trace driven simulations indicate that this technique can significantly reduce the number of pins required to transmit address information between processor and memory. Because this technique makes use of existing virtual memory hardware, it can eliminate address pins without significantly changing computing system design, cost, or performance.

VMOE: A Virtual Machine Operating Environment for the Computer Systems Curriculum

A major challenge for computer science educators is to acquaint students with not only the properties of the major components of computer systems, but also with the interactions among these components. Real systems are too complex to serve as examples for these investigations and example systems which have been introduced in the past do not provide the flexibility to deal adequately with the component interactions. The Virtual Machine Operating Environment (VMOE) is an example system, comprised of a virtual hardware environment and a specially designed programming language, which provides a basis for environments in which students can investigate component interactions in a variety of courses. This environment can help focus the attention of faculty and students on the often neglected subject of component interactions.