IMECO: A Reconfigurable FPGA-based Image Enhancement Co-Processor Framework

Abstract

In this paper, we present a way to improve the computational speed of image contrast enhancement using low-cost FPGA-based hardware primarily targeted to X-ray images. In particular, we consider an enhancement method that consists of filtering followed by histogram modification. Filtering is done via the high boost filter (HBF) which is based on unsharp masking, and the histogram modification which is based on global histogram equalization (GHE). An image enhancement co-processor, IMECO, concept is proposed that enables efficient hardware implementation of enhancement procedures and hardware/software co-design to achieve high-performance low-cost solutions. The co-processor runs on an FPGA prototyping ISA-bus board. At this stage it consists of two hardware functional units that implement HBF and GHE and can be downloaded onto the board sequentially or reside on the board at the same time. These units represent an embryo of virtual hardware units that form a library of image enhancement algorithms. These algorithms can be easily integrated into software templates. In our trials with chest X-ray images, performance improvement over software-only implementations is more than two orders of magnitude, thus providing real-time or near-real-time image enhancement as required in target applications.