IMECO: a reconfigurable FPGA-based image enhancement co-processor framework

Abstract

This paper presents a way to improve the computational speed of image contrast enhancement using low-cost FPGA-based hardware primarily targeted to X-ray images. The enhancement method considered here consists of filtering via the high boost filter (HBF), followed by histogram modification using histogram equalisation (HE). An image enhancement co-processor (IMECO) concept is proposed that enables efficient hardware implementation of enhancement procedures and hardware/software co-design to achieve high-performance, low-cost solutions. The co-processor runs on an FPGA prototyping ISA-bus board. It consists of two hardware functional units that implement HBF and HE and can be downloaded onto the board sequentially or reside on the board at the same time. These units represent an embryo of virtual hardware units that form a library of image enhancement algorithms. In trials with chest X-ray images performance improvement over software-only implementations was more than two orders of magnitude, thus providing real-time or near real-time enhancement.