Hardware Vendors Research Articles

Cloud Workload Characterization

This paper describes various computer system workloads and relates them to their underlying resource utilization. Specifically, the paper concentrates on Cloud workload characterization based upon issues, capabilities, and technologies surrounding the categories from the multiple points of view of the various players involved in Cloud Computing. The relationship is established between the categories and key limiting underlying technologies, and the dynamic and measurable low-level metrics and measurements that are used to detect and reduce resource contention, and identify category changes during run-time. Research questions are posed on dynamic low-level measurements and a usage case example with high performance computing (HPC) clusters. The Cloud workload categories can provide a basis for common communication for various viewpoints from players, including facility managers, Cloud IT or service providers, Cloud users, consumers, IT managers, and hardware vendors. This common communication tool will facilitate better service-level agreements (SLAs), capital purchase decisions, and future computer architecture design-decisions.

A STEP-NC Compatible on-Machine Measurement System with Automated Correlation of Inspection Data

On-machine measurement (OMM) is an important part of closed-loop manufacturing (CLM) system. How to achieve real-time measurement operation and measurement result integration claimed by CLM is a major issue that concerns software and hardware vendors. This paper proposed a STEP-NC compatible on-machine measurement system that was compatible with interoperable data model. In the beginning, information model of the system was proposed referring to current data model standards supporting closed-loop manufacturing. After that, a hierarchical process planning approach was present to plan the OMM process. Object-oriented macro programs were utilized to post process the planned inspection information and ensure the correct measuring result correlation. Besides, inspection items and measurement points were uniformly and uniquely identified to ensure the accurate and reliable associations of measurement results with the design model. At last, a STEP-NC compatible on-machine measurement prototype system was developed based on CATIA, and the validity and practicality of the proposed on-machine measurement system was demonstrated with an aeronautic test part.

Focus on semiconductors and software

Focus on semiconductors and software

Robust architectural support for transactional memory in the power architecture

On the twentieth anniversary of the original publication [10], following ten years of intense activity in the research literature, hardware support for transactional memory (TM) has finally become a commercial reality, with HTM-enabled chips currently or soon-to-be available from many hardware vendors. In this paper we describe architectural support for TM added to a future version of the Power ISA™. Two imperatives drove the development: the desire to complement our weakly-consistent memory model with a more friendly interface to simplify the development and porting of multithreaded applications, and the need for robustness beyond that of some early implementations. In the process of commercializing the feature, we had to resolve some previously unexplored interactions between TM and existing features of the ISA, for example translation shootdown, interrupt handling, atomic read-modify-write primitives, and our weakly consistent memory model. We describe these interactions, the overall architecture, and discuss the motivation and rationale for our choices of architectural semantics, beyond what is typically found in reference manuals.

A New EEG Artifact Specific to Digital Acquisition

To increase awareness in electroencephalographers of a new digital-specific artifact that could be falsely interpreted as epileptiform. Several examples of this artifact were discovered in clinical EEG recording. Examples of the clinical recording are presented using custom software to highlight the artifact. The underlying digital data were examined with standard hexadecimal editing software to verify the exact binary duplication error. The artifact appears as repetitions of very brief intervals (50 milliseconds). In channels in which the signal has a large excursion (sharp slope) over this time frame, the repetition of a 50-millisecond interval could appear similar to polyspikes. In one instance, such a misinterpretation led to a technologist instructing a patient to remain in the clinic because of an "abnormality." Artifacts that mislead the electroencephalographer are serious problems that can lead to erroneous affirmative diagnoses. The transition to digital acquisition brings the potential for new digital-specific errors. This report describes one such new digital artifact, discusses a conjecture for the stage of hardware where the artifact arises, suggests strategies for electroencephalographers to identify this artifact, and provides recommendations to clinical hardware vendors to avoid this error.

KVM vs. LXC: Comparing Performance and Isolation of Hardware-assisted Virtual Routers

Concerns have been raised about the performance of PC-based virtual routers as they do packet processing in software. Furthermore, it becomes challenging to maintain isolation among virtual routers due to resource contention in a shared environment. Hardware vendors recognize this issue and PC hardware with virtualization support (SR-IOV and Intel-VTd) has been introduced in recent years. In this paper, we investigate how such hardware features can be integrated with two different virtualization technologies (LXC and KVM) to enhance performance and isolation of virtual routers on shared environments. We compare LXC and KVM and our results indicate that KVM in combination with hardware support can provide better trade-offs between performance and isolation. We notice that KVM has slightly lower throughput, but has superior isolation properties by providing more explicit control of CPU resources. We demonstrate that KVM allows defining a CPU share for a virtual router, something that is difficult to achieve in LXC, where packet forwarding is done in a kernel shared by all virtual routers.

Energy Management Techniques in Modern Mobile Handsets

Managing energy efficiently is paramount in modern smartphones. The diverse range of wireless interfaces and sensors, and the increasing popularity of power-hungry applications that take advantage of these resources can reduce the battery life of mobile handhelds to few hours of operation. The research community, and operating system and hardware vendors found interesting optimisations and techniques to extend the battery life of mobile phones. However, the state of the art of lithium-ion batteries clearly indicates that energy efficiency must be achieved both at the hardware and software level. In this survey, we will cover the software solutions that can be found in the research literature between 1999 and May 2011 at six different levels: energy-aware operating systems, efficient resource management, the impact of users' interaction patterns with mobile devices and applications, wireless interfaces and sensors management, and finally the benefits of integrating mobile devices with cloud computing services.

Parallel Implementation of 1-D Complex FFT Using Multithreading and Multi-Core Systems

 Abstract—Now-a-days most desktop PCs have multiprocessing technology such as Hyper-Threading (HT), Dual-Core, and Quad-Core processors. Technological developments in microprocessor design have enabled hardware vendors to put multiple cores on a single socket. The main idea is to build software applications that can fully exploit the capabilities of a multi-core system using multithreading approach for faster performance. The aim of this paper is to show the performance enhancement in terms of execution time using multiple threads. This involves executing sequential software application followed by multithreaded software application on Intel based multi-core systems. 1-D complex Fast Fourier Transform (FFT) function has been taken from an open source library, called FFTw, as an example to prove the concept. Finally results show the decrease in execution time with increase in FFT sizes for a multithreaded software application on a multi-core system.

A Strategy to Move Taiwan's IT Industry From Commodity Hardware Manufacturing to Competitive Cloud Solutions

Taiwan has been a worldwide leader in computer hardware manufacturing for many years. Cloud computing, a major paradigm shift for the IT industry, threatens that leadership position. Cloud computing drives the value chain increasingly toward systems software and services. It has a major negative impact on the already marginal profit picture that threatens Taiwan's hardware manufacturing industry, and the Taiwan economy as a whole. The Institute for Information Industry (III) has devised a strategy and technology called cloud appliances for enterprises (CAFE) to address the effects of this technology shift. CAFE is a major initiative to help traditional Taiwanese OEM/ODM vendors transform themselves from primarily being commodity hardware providers into highly profitable, full-function cloud systems business that can reach worldwide markets. The III develops key system software components (CAFE technology components) that can be integrated with partners' hardware and other technology to create appliances that deliver cloud infrastructure and services enabling enterprises to establish private clouds (thus the name CAFE). Appliances that offer user-ready services and applications, provide significantly higher value to customers, support higher prices than hardware alone, and thereby increase the profit margin of Taiwanese IT vendors. Key Taiwan hardware vendors that have already adapted the CAFE strategy include ASUS, Delta Electronics, GIGABYTE, In Win, and Promise Technology. They are developing, integrating, and shipping cloud appliances that incorporate CAFE technology components, as well as their own technology. The CAFE strategy has turned the cloud computing challenge into a golden opportunity, moving the IT industry of Taiwan toward the next horizon. Video-Summary and Testimonials http://www.youtube.com/watch?v=p4jqeuAwF00&feature=youtu.be.

Probability-based static wear-leveling algorithm for block and hybrid-mapping NAND flash memory

Owing to its desirable characteristics, flash memory has become attractive to different hardware vendors as a primary choice for data storage. However, because of a limited number of block-erase lifecycles, it has become mandatory to redesign the existing approaches to maximize the flash memory lifetime. Wear-leveling is a mechanism that helps to evenly distribute erase operations to all blocks and enhance lifetime. This research proposes probability-based static wear-leveling. Based on the Markov Chain theory, the future state depends on the present state. Mapping is implemented according to the present visit probability of each logical block in the next state. In each state, the wear-leveling distribution is computed using the standard deviation to determine whether it exceeds the threshold. If it does exceed the threshold, wear-leveling is maintained throughout all blocks in the flash memory by swapping the hot blocks with cold blocks. Using real system-based traces, we have proved that our proposal outperforms the existing design in terms of wear-leveling.

ICEFormat—the image cytometry experiment format

ICEFormat—the image cytometry experiment format

MO‐F‐217BCD‐01: Assessment of Image Quality in the New CT

The emergence of fully volumetric CT imaging systems and statistical / iterative reconstruction methods present an immediate need for rigorous methods of image quality assessment. Major themes arising in the widespread utilization of such technologies include: 1.) the reduction of radiation dose in a manner that maintains imaging performance with respect to the imaging task; 2.) the need for quantitative standards in image quality assessment appropriate to various vendor hardware and reconstruction systems; 3.) imaging performance metrics that provide meaningful descriptors of fully 3D spatial resolution and noise characteristics; 4.) the dependence of these metrics on acquisition technique, reconstruction parameters, and their applicability (or lack thereof) to novel reconstruction methods that may defy conventional metrics founded in assumptions of linearity and shift invariance; and 5.) methods for physical measurement (e.g., phantoms) and theoretical analysis of image quality for these new and emerging CT technologies and their implications for dose reduction.Learning Objectives:1. Understand the methods and metrics of image quality assessment for fully volumetric (cone‐beam) CT imaging using 3D filtered backprojection, including analysis of the 3D NPS, NEQ, and detectability index.2. Understand the limitations and assumptions of such metrics with respect to linearity, stationarity, and novel reconstruction techniques.3. Gain an understanding of how rigorous assessment of imaging performance can guide technique optimization, dose reduction, and the development of new CT technologies and applications.4. Understand the factors of image quality assessment in nonlinear statistical / model‐based 3D reconstruction techniques, including PSF and covariance estimation in nonstationary systems.5. Gain perspective on image quality assessment standards, including methods for dose and image quality measurement on different vendor platforms and the implications for dose reduction.

SU-E-I-104: Detector Lag Testing for Digital Radiography.

Signal lag is an inherent property of the digital detectors used for radiography. The extent and impact of signal lag can vary. In this exhibit we aim to:'¢ provide context for detector lag testing as a matter of acceptance testing for detectors used in digital radiography (DR)'¢ provide example lag data from various DR systems. Lag measurement and analysis techniques have been published but without the expected results that are useful for benchmarking.'¢bring greater awareness and understanding to the impact of detector lag for the performance of digital detectors and the appearance of image ghosting in clinical images. A standardized method was used for the quantification of lag similar to that described in the IPEM report 32 part vii [1]. Six different vended detector options were measured and compared. Lag images were visually compared and lag measurement values were normalized using the measured signal transfer properties of each system. The results are shown as normalized with exposure. The results show a wide variety of lag responses, even for the same physical detector hardware but different vendor implementations. The ultimate test for detector lag performance is whether residual 'ghost' images appear in clinical images. Some vendor systems are more prone to the appearance of lag than others. We attempt to quantify system properties at acceptance testing that can enable discriminationbetween systems which have poor or superior lag properties. A suggested easurement analysis technique which normalizes data to be linear with exposure does not appear to adequately assess the likelihood for the clinical appearance of lag. [1] Mackenzie A et al. Measurement of the Performance Characteristics of Diagnostic X-Ray Systems: Digital Imaging Systems. Institute of Physics in Medicine 2009 (IPEM Report 32, part vii). 2010.

Looking back on the language and hardware revolutions

This paper reports and analyzes measured chip power and performance on five process technology generations executing 61 diverse benchmarks with a rigorous methodology. We measure representative Intel IA32 processors with technologies ranging from 130nm to 32nm while they execute sequential and parallel benchmarks written in native and managed languages. During this period, hardware and software changed substantially: (1) hardware vendors delivered chip multiprocessors instead of uniprocessors, and independently (2) software developers increasingly chose managed languages instead of native languages. This quantitative data reveals the extent of some known and previously unobserved hardware and software trends. Two themes emerge.

GPU parallel computing: Programming language, debugging tools and data structures

With many cores driven by high memory bandwidth, today’s graphics processing unit (GPU) has involved into an absolute computing workhorse. More and more scientists, researchers and software developers are using GPUs to accelerate their algorithms and applications. Developing complex programs and software on the GPU, however, is still far from easy with existing tools provided by hardware vendors. This article introduces our recent research efforts to make GPU software development much easier. Specifically, we designed BSGP, a high-level programming language for generalpurpose computation on the GPU. A BSGP program looks much the same as a sequential C program, and is thus easy to read, write and maintain. Its performance on the GPU is guaranteed by a well-designed compiler that converts the program to native GPU code. We also developed an effective debugging system for BSGP programs based on the GPU interrupt, a unique feature of BSGP that allows calling CPU functions from inside GPU code. Moreover, using BSGP, we developed GPU algorithms for constructing several widely-used spatial hierarchies for high-performance graphics applications.

FCS 3.1 Implementation Guidance

The Flow Cytometry Standard (FCS) format was developed back in 1984. Since then, FCS became the standard file format supported by all flow cytometry software and hardware vendors. Over the years, updates were incorporated to adapt to technological advancements in both flow cytometry and computing technologies. However, flexibility in how data may be stored in FCS has led to implementation difficulties for instrument vendors and third party software developers. In this technical note, we are providing implementation guidance and examples related to FCS 3.1, the latest version of the standard. By publishing this text, we intend to prevent potential compatibility issues that could be faced when implementing the FCS spillover and preferred display keywords that have arisen during discussions among some implementers.

Dimensional metrology interoperability and standardization in manufacturing systems

Dimensional metrology is an important part of any manufacturing system. It consists of distinct components and requires a large, diverse, and interconnected knowledge base. How to pass information seamlessly with minimal cost and minimal data loss between different components of a dimensional metrology system is a major issue that concerns software and hardware vendors, standards developers, and customers. This paper focuses on the four main elements of a dimensional metrology system: product definition, measurement process plan definition, measurement process execution, and analysis and reporting of quality data. The activities and software modules that are involved in these elements are discussed. Key issues that cause interoperability problems are identified. These issues are discussed as they relate to the current situation in dimensional metrology standards development. The STEP (ISO 10303) standards are the product of an international effort to achieve interoperability for manufacturing systems. Extending STEP is an appropriate way to solve the interoperability problem within dimensional metrology systems. Further development of STEP standards is proposed so that Geometric Dimensioning and Tolerancing (GD&T) information already available in STEP can be linked with manufacturing feature information, measurement technology, and measurement results. The proposed STEP data model is an attempt to provide a standard that will support automatic measurement process plan generation for in-process on-machine measurement. Some case studies are under way to test the model.

Looking back on the language and hardware revolutions

This paper reports and analyzes measured chip power and performance on five process technology generations executing 61 diverse benchmarks with a rigorous methodology. We measure representative Intel IA32 processors with technologies ranging from 130nm to 32nm while they execute sequential and parallel benchmarks written in native and managed languages. During this period, hardware and software changed substantially: (1) hardware vendors delivered chip multiprocessors instead of uniprocessors, and independently (2) software developers increasingly chose managed languages instead of native languages. This quantitative data reveals the extent of some known and previously unobserved hardware and software trends. Two themes emerge. (I) Workload: The power, performance, and energy trends of native workloads do not approximate managed workloads. For example, (a) the SPEC CPU2006 native benchmarks on the i7 (45) and i5 (32) draw significantly less power than managed or scalable native benchmarks; and (b) managed runtimes exploit parallelism even when running single-threaded applications. The results recommend architects always include native and managed workloads when designing and evaluating energy efficient hardware. (II) Architecture: Clock scaling, microarchitecture, simultaneous multithreading, and chip multiprocessors each elicit a huge variety of power, performance, and energy responses. This variety and the difficulty of obtaining power measurements recommends exposing on-chip power meters and when possible structure specific power meters for cores, caches, and other structures. Just as hardware event counters provide a quantitative grounding for performance innovations, power meters are necessary for optimizing energy.

Looking back on the language and hardware revolutions

This paper reports and analyzes measured chip power and performance on five process technology generations executing 61 diverse benchmarks with a rigorous methodology. We measure representative Intel IA32 processors with technologies ranging from 130nm to 32nm while they execute sequential and parallel benchmarks written in native and managed languages. During this period, hardware and software changed substantially: (1) hardware vendors delivered chip multiprocessors instead of uniprocessors, and independently (2) software developers increasingly chose managed languages instead of native languages. This quantitative data reveals the extent of some known and previously unobserved hardware and software trends. Two themes emerge. (I) Workload: The power, performance, and energy trends of native workloads do not approximate managed workloads. For example, (a) the SPEC CPU2006 native benchmarks on the i7 (45) and i5 (32) draw significantly less power than managed or scalable native benchmarks; and (b) managed runtimes exploit parallelism even when running single-threaded applications. The results recommend architects always include native and managed workloads when designing and evaluating energy efficient hardware. (II) Architecture: Clock scaling, microarchitecture, simultaneous multithreading, and chip multiprocessors each elicit a huge variety of power, performance, and energy responses. This variety and the difficulty of obtaining power measurements recommends exposing on-chip power meters and when possible structure specific power meters for cores, caches, and other structures. Just as hardware event counters provide a quantitative grounding for performance innovations, power meters are necessary for optimizing energy.

How's the parallel computing revolution going?

Two trends changed the computing landscape over the past decade: (1) hardware vendors started delivering chip multiprocessors (CMPs) instead of uniprocessors, and (2) software developers increasingly chose managed languages instead of native languages. Unfortunately, the former change is disrupting the virtuous-cycle between performance improvements and software innovation. Establishing a new parallel performance virtuous cycle for managed languages will require scalable applications executing on scalable Virtual Machine (VM) services, since the VM schedules, monitors, compiles, optimizes, garbage collects, and executes together with the application. This talk describes current progress, opportunities, and challenges for scalable VM services. The parallel computing revolution urgently needs more innovations.