Hardware Trojan attacks have emerged as a major security issue for hardware at different level of abstractions, which relate to malicious tampering of a hardware during design or fabrication process. In this paper, a new low overhead and high speed design for trust methodology for increasing both full activation and side channel sensitivity of Trojan is proposed. The main idea is that the increase in transition probability of individual nets does not necessarily increase the transition probability of the succeeding nets of the circuit. Accordingly, the rules and conflicts of the propagation of maximum transition probability for individual gates have been presented to ensure that a full transition path is constructed between each low transition probability net and primary inputs of the circuit. The results show that the proposed methodology achieves superior efficiency in Trojan full activation by more than $4 \times $ through logic testing approach besides higher sensitivity averagely around $20 {\times }$ for power-based side channel analysis compared to existing methods.