Hardware Synthesis Research Articles

Synthesis of hardware and software for adaptive discrete high-order control systems based on a model of the desired transient process with a guaranteed degree of stability

In this work, analytical expressions for the connection between optimization criteria andsettings parameters of the adaptive PI-PID controller with variable parameters of the object andadaptive filter have been removed. A method for synthesizing a model of discrete controllersbased on given dynamic characteristics has been developed. A method has been developed forsynthesizing a model of a discrete PID controller based on given dynamic characteristics basedon the criterion of the transient process of a guaranteed level of stability. 3 figures, 0 tables, 32formulas, 19 bibliographic sources..Analytical expressions have been removed to link the optimization criteria andadjustment parameters of the adaptive PI-PID controller with the variable parameters of theobject and adaptive filter.A method for synthesizing a model of discrete controllers from specified dynamiccharacteristics has been developed. The average warehouse of output pulses at the output of anonlinear channel, which is formed at the output of such a regulator and is seen as an inertialinduced uninterrupted part, changes according to the law, which is designated as a reversetransmission the function of the lanyard of the new molded filter model at the collar of the non-linear element.A method has been developed for synthesizing a model of a discrete PID controller fromspecified dynamic characteristics based on the criterion of the required transient process of aguaranteed stability level.The modeling showed that while the parameters of the object and the adaptive filter willchange during the ASC operation, then, obviously, the optimal parameters for adjusting theadaptive PID controller will immediately change.

A Hardware Realization Framework for Fuzzy Inference System Optimization

Fuzzy inference systems (FISs) are a key focus for decision-making in embedded systems due to their effectiveness in managing uncertainty and non-linearity. This study demonstrates that optimizing FIS hardware enhances performance, efficiency, and capabilities, improving user experience, heightened productivity, and cost savings. We propose an ultra-low power FIS hardware framework to address power constraints in embedded systems. This framework supports optimizations for conventional arithmetic and Most Significant Digit First (MSDF) computing, ensuring compatibility with MSDF-based sensors. Within the MSDF-computing FIS, fuzzification, inference, and defuzzification processes occur on serially incoming data bits. To illustrate the framework’s efficiency, we implemented it using MATLAB, Chisel3, and Vivado, starting from high-level FIS descriptions and progressing to hardware synthesis. A Scala library in Chisel3 was developed to connect these tools seamlessly, facilitating design space exploration at the arithmetic level. We applied the framework by realizing an FIS for autonomous mobile robot navigation in unknown environments. The synthesis results highlight the superiority of our designs over the MATLAB HDL code generator, achieving a 43% higher clock frequency, and 46% and 67% lower resource and power consumption, respectively.

FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler

The exponential performance growth guaranteed by Moore’s law has started to taper in recent years. At the same time, emerging applications like image processing demand heavy computational performance. These factors inevitably lead to the emergence of domain-specific accelerators (DSA) to fill the performance void left by conventional architectures. FPGAs are rapidly evolving towards becoming an alternative to custom ASICs for designing DSAs because of their low power consumption and a higher degree of parallelism. DSA design on FPGAs requires careful calibration of the FPGA compute and memory resources towards achieving optimal throughput. Hardware Descriptive Languages (HDL) like Verilog have been traditionally used to design FPGA hardware. HDLs are not geared towards any domain, and the user has to put in much effort to describe the hardware at the register transfer level. Domain Specific Languages (DSLs) and compilers have been recently used to weave together handwritten HDLs templates targeting a specific domain. Recent efforts have designed DSAs with image-processing DSLs targeting FPGAs. Image computations in the DSL are lowered to pre-existing templates or lower-level languages like HLS-C. This approach requires expensive FPGA re-flashing for every new workload. In contrast to this fixed-function hardware approach, overlays are gaining traction. Overlays are DSAs resembling a processor, which is synthesized and flashed on the FPGA once but is flexible enough to process a broad class of computations through soft reconfiguration. Less work has been reported in the context of image processing overlays. Image processing algorithms vary in size and shape, ranging from simple blurring operations to complex pyramid systems. The primary challenge in designing an image-processing overlay is maintaining flexibility in mapping different algorithms. This paper proposes a DSL-based overlay accelerator called FlowPix for image processing applications. The DSL programs are expressed as pipelines, with each stage representing a computational step in the overall algorithm. We implement 15 image-processing benchmarks using FlowPix on a Virtex-7-690t FPGA. The benchmarks range from simple blur operations to complex pipelines like Lucas-Kande optical flow. We compare FlowPix against existing DSL-to-FPGA frameworks like Hetero-Halide and Vitis Vision library that generate fixed-function hardware. On most benchmarks, we see up to 25% degradation in latency with approximately a 1.7x to 2x increase in the FPGA LUT consumption. Our ability to execute any benchmark without incurring the high costs of hardware synthesis, place-and-route, and FPGA re-flashing justifies the slight performance loss and increased resource consumption that we experience. FlowPix achieves an average frame rate of 170 FPS on HD frames of 1920 × 1080 pixels in the implemented benchmarks.

Проєктування апаратного декомпресора

The common lossless compression algorithms were analyzed, and the LZW algorithm was selected for the hardware implementation. To express parallelism, this algorithm is represented as a cyclo-dynamic dataflow (CDDF). A hardware synthesis method for designing pipelined datapath is proposed, which optimizes CDDF considering the features of the FPGA primitives and maps it to hardware using VHDL language description. Using this method, an LZW de¬compressor is developed, which exhibits a high performance-to-hardware cost ratio. The de¬com¬¬¬pressor can be utilized in communication channels and other application-specific systems for data loading from memory, generating graphical stencils, and more.

Clinical Assessment of Dosha Predominance in Shalya Karma Using an Electronic Device Nadi Tarangini

Shalya Karma i.e., operative procedures for fistula-in-ano, fissure-in-ano, haemorrhoids, appendicitis, cholelithiasis, different hernias etc is nowadays very commonly adopted in which surgeons are highly concerned about the recurrences and complications which highly affects the patient’s quality of life. Ayurveda places a lot of stress on feeling the pulse at the radial artery in order to evaluate the Doshas, but it does not restrict the pulse location to just the radial artery and instead makes it plain that the pulse can be felt from eight different places. The radial artery can be used to learn about the Vata, Pitta, and Kapha doshas. Nadi Pariksha uses completely all the basic subjects described in Ayurveda. All spheres of medical science is not remained untouched from Nadi Pariksha. Cause-effect /Karya-karan or Nidan-vyadhi relationship can be finely diagnosed with Nadi Pariksha. Therefore, treatment becomes very unique and specific. Whether treatment is of body or mind, it becomes very clear with Nadi Pariksha. In Ayurveda, post-operative Tridosha specific Nadi Pariksha can be considered a more rationale plan for better outcomes in overcoming the recurrences and gaining a lead over modern surgical complications after Shalya Karma. Nadi Tarangini is a tool to detect and analyze information about our inner health. Nadi Tarangini, the pioneer of the modern Nadi Pariksha system, is a perfect synthesis of hardware and intelligent software powered by artificial intelligence.

Fuzzy Hardware Tool: An Adaptable Tool to Facilitate the Implementation of Fuzzy Inference Systems in Hardware

A Fuzzy Inference System (FIS) is a system that represents human reasoning based on fuzzy if-then rules to extract valid results from imprecise or uncertain information. These systems have been applied to various engineering fields, such as control and image recognition, and have encouraged the search for development tools that provide facilities for the design, simulation, and implementation of FISs. Most of the available software tools for the design of FISs have been developed by the scientific community, and very few are commercial tools. According to the state of the technology, the fuzzy systems implemented in hardware have shown higher performance than software implementations. For this reason, different strategies for automatic hardware synthesis of FISs have been proposed in the literature. The available tools for FIS implementation, including MATLAB, Simulink, and Xfuzzy environment, require advanced hardware knowledge, and it is necessary to synthesize and implement the program on FPGA each time a change is made to the code. This paper presents a novel approach for the implementation of fuzzy systems on hardware devices that enables the direct implementation of FISs through a graphical user interface. The VHDL code is pre-synthesized and integrated with the interface, allowing users to experiment with different input parameters, such as membership functions and fuzzy rules, without resynthesizing the code on an FPGA. To verify the effectiveness of the proposed approach, experiments were conducted on two similar System-on-Chip (SoC) devices, VEEK-MT and VEEK-MT2. The results showed that the proposed solution represents a significant advancement in the study of fuzzy systems on hardware devices, providing a flexible and user-friendly approach to their design and implementation.

Sixer: A low-overhead, fully-distributed test scheme with guaranteed delivery of packets in networks-on-chip

The guaranteed delivery of application packets from source to destination in a network-on-chip (NoC) is increasingly becoming an essential design issue. Channel faults may cause a significant amount of packet loss and subsequently degrade the system’s performance. In particular, open-channel defects threaten the loss of reliability, yield, and service quality. Hence, their detection and localization during the system’s runtime are highly needed. However, coexistent short-channel faults might mitigate the threats to a certain extent. This paper presents a low-cost test method that detects open-channel faults to preserve the connectivity between a source and destination pair in NoCs. The procedure is extended to address the channel’s self-repairing mode by covering the short-channel defects via fault masking. Further, a fully distributed test-scheduling technique named “Sixer” is presented to reduce the test cost and make the scheme scalable with NoCs. Experimental results show hardware synthesis incurs nearly 6.72% and 21.85% area overhead while single and multiple channel-fault models are assumed, respectively. The test method takes 8 and 38 clocks for the same fault models. Also, fault simulation shows full and (nearly 95%) fault coverage for these models. Online evaluation of the “Sixer” reveals various performance metrics. A detailed comparison study shows the proposed scheme improves hardware area and test-time overhead up to 66.12% and 97%, respectively. Simultaneously, performance overhead is improved by 43.78%, 54.75%, and 62.97% concerning packet loss, latency, and energy consumption, respectively.

ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The processor is implemented specifically for the target application, which allows the hardware customization in terms of instruction set architecture, data word length, memory size, and parallelism. This work describes an EDA tool for the semi-automatic development of ASIPs named ASIPAMPIUM. The strategy is to provide a set of integrated tools to interpret and generate a customized hardware for a given target application, including compilation, simulation, and hardware synthesis. From the C code description of the application, the tool returns a synthesizable hardware description of the processor. The proposed methodology is based on the adaptation of a new customizable microprocessor called PAMPIUM, which can be optimized in terms of silicon area, power consumption, or processing performance according to the target application. The ASIPAMPIUM tool provides a series of simulated data to the designer in order to identify optimization strategies in both software and hardware domains. We show the results for the implementation of an FFT algorithm using the proposed methodology, which achieved best results in terms of silicon area and energy consumption compared to other works described in the literature for both FPGA and silicon implementation. Moreover, measurement results of the implementation in silicon of a dedicated ASIP for interfacing with six sensors in real-time, including three I2C, an SPI, and an RS-232 interfaces, demonstrate the complete design flow, from the C code program to physical implementation and characterization. Aside from providing a short design time, the ASIPAMPIUM tool also affords a simple and intuitive design flow, allowing the designer to deal with different design trade-offs and objectives.

АПАРАТНА РЕАЛІЗАЦІЯ АВТОМАТИЗОВАНОЇ СИСТЕМИ ЗБОРУ ІНФОРМАЦІЇ З ЕЛЕКТРИЧНОЇ ПІДСТАНЦІЇ 35/10 КВ

Purpose. Increasing connectivity and, as a result, reducing the time of receiving telemetry information on the distribution network section by means of the development of a hardware complex for monitoring and information transmission. Methodology. The research was carried out on the basis of system and elemental-structural approaches with elements of simulation modeling, programming and analytical calculations. Results. The results of the work are applied. Within the framework of the conducted research of the subject area, it has been suggested to use information and communication technologies to increase the level of operational response to emergency situations during the operation of electric transformer step-down substations. The parameters of the short-circuit current protection system have been calculated for the substation, based on the values of which a protection device with communication interface buses has been selected, which allow applying the approach of the Internet of Things, the Industrial Internet of Things, and the Internet of Energy for the subsequent construction of an automated information system. Hardware synthesis, selected means of automation and the given schemes allow further implementation of a full-fledged system of monitoring and control of the transformer substation. Scientific novelty. The concept of a universal system of information collection and transmission for distribution power systems has been proposed at the level of technical implementation. Practical significance. The paper offers a hardware data collection and transmission system that can be used in power systems for connection and telemetry of relay protection devices.

ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters

This paper proposes ReAdapt–a reconfigurable datapath architecture for scaling the energy-quality trade-off of adaptive filtering at runtime. The ReAdapt can dynamically select four adaptive filtering algorithms for gradating complexity levels during runtime by reconfiguring the processing flow in its datapath and by blocking the switching activity (e.g., reducing the CMOS dynamic power) of unused modules with data-gating. The ReAdapt proposal can scale the energy-quality trade-off by choosing the following four different levels of filter algorithms complexity: 1) least mean square (LMS); 2) partial update normalized LMS (PU-NLMS); 3) set-membership normalized LMS (SM-NLMS); 4) normalized LMS (NLMS). The ReAdapt architecture reuses common modules of each adaptive filter, resulting in a compact VLSI hardware implementation. The ReAdapt architecture operation is implemented in a case-study for interference mitigation for electroencephalogram (EEG) signal processing. The hardware synthesis results show an increase of 6.80 times in throughput and at least a reduction of 2.84 times in energy per operation compared with the state-of-the-art adaptive filters. This paper also investigates the benefits of dynamically reconfiguring the four ReAdapt operating modes at runtime for different levels of signal-to-noise ratio (SNR) for the processed signals. We also demonstrate that dynamically reconfiguring the ReAdapt operating modes during runtime results in an optimal energy-quality trade-off which is advantageous over the conventional single static mode.

Information technology of IT-infrastructure management architecture elements

The development of the System Architecture of the IT-infrastructure focused on the use of modern Data Centers is considered. At the same time, it is envisaged to create components that describe: general approaches to building a system architecture; IT-services – information technologies that solve the task of providing IT-services; logical model of IT-infrastructure. Formulated logic of IT-infrastructure construction: IT-infrastructure architectures define a set of services. IT-services are provided to three groups of clients. IT-services and clients are connected by 5 implementation scenarios. The integration of IT-services is determined by 5 architectures. As IT-services, we understand information technologies aimed at maintaining the following elements in a technically good state: network devices, computing equipment, data storage devices, automatic software deployment services, network services, perimeter protection services, directory services, file and print services, data management services, business application services, IT-management services, archiving and recovery services, certificate management services, integration services. Architectures define the fundamental principles of building IT-services and their relationship. Also, requirements for the creation of IT-services are formed on the basis of the architecture. One of the most important architectures is architecture of IT-infrastructure management. The architecture of the management system ensures the necessary level of IT-services of the Data Center due to the organization of three components – personnel, processes, technologies. The tasks of the architecture are: use of processes and information technologies to identify and minimize failures of IT-services; ensuring a high degree of integration of information technologies; ensuring response to changes in system parameters and performance of service functions in real time. As an example, the management function of the IT-service “network administration” (monitoring and control of configuration management services, coordination of changes, remote management and debugging) is considered. The algorithmic synthesis of programs and devices network management is considered, which consists in the construction of a functional scheme of control devices in two stages – abstract and structural synthesis, and all the steps of its solution and subsequent hardware synthesis are determined.

An FPGA Library Based Design of Variable CNN Weight Compression using Resizable K-Means Clustering

Convolutional Neural Networks (CNN) is a popular tool used for image recognition. In CNN architecture, a set of weights undergo a series of updating while the training process for image recognition is ongoing. These weight values can be quite a lot in memory consumption. One way to reduce memory consumption is to use a form of weight compression through weight sharing. To do this, one can quantize the weights using K-Means clustering. To use the K means Clustering algorithm, one can manually try different values of K and then choose the best value that can save the CNN memory usage and at the same time will not deteriorate the recognition ability of the CNN. The method of trying different values of K to search for the best compression rate, can be time consuming for the user. In this paper, using XILINX Virtex FPGA library, a proposed hardware model design for a CNN integrated to a resizable Kmeans Clustering Model is presented. The hardware model design highlights the elimination of the manual search for best value of K. A synthesizable hardware model for the control and data path of the integration is proposed. A Hardware Model algorithm for an automated search for the best value of K in steps of 10, is presented. The proposed integration will allow the system to work by itself, to auto search for the best compression ratio after the CNN has finished training.

SpecHLS: Speculative Accelerator Design Using High-Level Synthesis

Custom hardware accelerators usage is shifting toward new application domains such as graph analytics and unstructured text analysis. These applications expose complex control-flow which is challenging to map to hardware, especially when operating from a C/C++ description using high-level synthesis toolchains. Several approaches relying on speculative execution have been proposed to overcome those limitations, but they often fail to handle the multiple interacting speculations required for realistic use-cases. This article proposes a fully automated hardware synthesis flow based on a source-to-source compiler that identifies and explores intricate speculation configurations to generate speculative hardware accelerators.

High-precision time synchronization chip design for industrial sensor and actuator network

Mission-critical (MC) sensor and actuator networks (SANs) are being applied widely for multiaxis motion control of robotic manipulators , particularly for performing MC tasks in smart manufacturing. One of the most challenging tasks in MC-SANs is the development of a precision time synchronization (PTS) protocol. A conventional precision time system uses the IEEE 1588 v2 standard [1] ; however, in MC-SANs, many factors need to be considered when designing an IoT computing system, such as robustness, cost-effectiveness, interoperability and scalability. This study proposes a high-precision time synchronization protocol based on Modbus sensors and actuator networks for an industrial fieldbus network. The PTS protocol design and hardware synthesis are conducted with a consistent and systematic design methodology. GRAFCET is used to model the individual functional modules and hierarchical behavior of the system. The behavior of each module is represented as a sequential–concurrent hybrid discrete event system . We apply high-level synthesis rules to design PTS hardware for a complex PTS system based on the VHSIC hardware description language (VHDL). The PTS hardware module has an embedded PTS algorithm with a proportional error correction model, and the time synchronization accuracy of the precision time protocol (PTP) chip is up to 42 ns. Experimental results demonstrate that our high-performance PTS controller chip can satisfy the requirements of multiaxis motion control and that it is more efficient than other protocols and products designed for similar industrial manufacturing applications.

An Investigation on Spiking Neural Networks Based on the Izhikevich Neuronal Model: Spiking Processing and Hardware Approach

The main required organ of the biological system is the Central Nervous System (CNS), which can influence the other basic organs in the human body. The basic elements of this important organ are neurons, synapses, and glias (such as astrocytes, which are the highest percentage of glias in the human brain). Investigating, modeling, simulation, and hardware implementation (realization) of different parts of the CNS are important in case of achieving a comprehensive neuronal system that is capable of emulating all aspects of the real nervous system. This paper uses a basic neuron model called the Izhikevich neuronal model to achieve a high copy of the primary nervous block, which is capable of regenerating the behaviors of the human brain. The proposed approach can regenerate all aspects of the Izhikevich neuron in high similarity degree and performances. The new model is based on Look-Up Table (LUT) modeling of the mathematical neuromorphic systems, which can be realized in a high degree of correlation with the original model. The proposed procedure is considered in three cases: 100 points LUT modeling, 1000 points LUT modeling, and 10,000 points LUT modeling. Indeed, by removing the high-cost functions in the original model, the presented model can be implemented in a low-error, high-speed, and low-area resources state in comparison with the original system. To test and validate the proposed final hardware, a digital FPGA board (Xilinx Virtex-II FPGA board) is used. Digital hardware synthesis illustrates that our presented approach can follow the Izhikevich neuron in a high-speed state (more than the original model), increase efficiency, and also reduce overhead costs. Implementation results show the overall saving of 84.30% in FPGA and also the higher frequency of the proposed model of about 264 MHz, which is significantly higher than the original model, 28 MHz.

The Proposition of Three Approaching Ways to Implement Tan-sigmoid Activation Function in FPGA

Hyperbolic tangents and Sigmoid are commonly used for Artificial Neural Networks as activation functions. The complex equation of the activation function is one of the most difficult to be implemented in hardware because containing division and exponential, which gives non-linear behavior. The challenge is building a tan-sigmoid function in hardware with efficient performance. Therefore, this work will focus on implementing the activation function in FPGA. To overcome this challenge, a different approach was proposed in this paper, efficient hardware-implemented for tan-sigmoid in terms of the number of slices occupied and the resources utilization are designed. In this work, three approaches are proposed: tan-sigmoid using the log approximation method, tan-sigmoid using segmentation method, and tan-sigmoid using the polynomial method. These approaches are efficiently implemented in the Xilinx Spartan-3A xc3s700a-4fg484 platform. Hardware synthesis and FPGA implementations illustrate that the proposed tan-sigmoid only takes up to 1% of logic resources in the first and second proposed approaches. While, 4% showed in the third proposed approach, with the best efficiency and significantly confirmed the lowest implementation costs than the traditional approach.

A framework for designing power-efficient inference accelerators in tree-based learning applications

Machine Learning techniques (ML) are being widely adopted in embedded devices due to their efficiency and flexibility. However, the strict power limitations in such devices, combined with the variable resource requirements of ML models, require further understanding of how model complexity affects power and performance. This paper proposes a framework that facilitates the design space exploration of dedicated decision trees (DT) and random forests (RF) accelerators by enabling a joint assessment of power dissipation and prediction accuracy. The proposed framework translates tree-based structures to hardware description languages (HDL). The HDL modules are submitted to logic and physically-aware hardware synthesis flows, allowing a detailed power-performance analysis of VLSI DTs and RFs. Using four data sets of embedded applications as case studies, we found that quantizing the input features leads to accuracy gains of up to 6.3% compared with the precise versions. We also show that using shallower trees may lead to small prediction loss with significant reductions in power, which is favorable for power-constrained applications. Our translator achieves better results in terms of energy/inference w.r.t. prior related works under comparison, one of which employed standard methods for hardware translation such as High-Level Synthesis. The proposed solution presents a power reduction of 10 times or more for the same inference throughput reported in prior works.

End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators

Edge systems are required to autonomously make real-time decisions based on large quantities of input data under strict power, performance, area, and other constraints. Meeting these constraints is only possible by specializing systems through hardware accelerators purposefully built for machine learning and data analysis algorithms. However, data science evolves at a quick pace, and manual design of custom accelerators has high non-recurrent engineering costs: general solutions are needed to automatically and rapidly transition from the formulation of a new algorithm to the deployment of a dedicated hardware implementation. Our solution is the SOftware Defined Architectures (SODA) Synthesizer, an end-to-end, multi-level, modular, extensible compiler toolchain providing a direct path from machine learning tools to hardware. The SODA Synthesizer frontend is based on the multilevel intermediate representation (MLIR) framework; it ingests pre-trained machine learning models, identifies kernels suited for acceleration, performs high-level optimizations, and prepares them for hardware synthesis. In the backend, SODA leverages state-of-the-art high-level synthesis techniques to generate highly efficient accelerators, targeting both field programmable devices (FPGAs) and application-specific circuits (ASICs). In this paper, we describe how the SODA Synthesizer can also assemble the generated accelerators (based on the finite state machine with datapath model) in a custom system driven by a distributed controller, building a coarse-grained dataflow architecture that does not require a host processor to orchestrate parallel execution of multiple accelerators. We show the effectiveness of our approach by automatically generating ASIC accelerators for layers of popular deep neural networks (DNNs). Our high-level optimizations result in up to 74x speedup on isolated accelerators for individual DNN layers, and our dynamically scheduled architecture yields an additional 3x performance improvement when combining accelerators to handle streaming inputs.

ПРОГРАМНО-АПАРАТНЕ ЗАБЕЗПЕЧЕННЯ КОМП’ЮТЕРНО-ІНТЕГРОВАНОЇ СИСТЕМИ КОНТРОЛЮ І КЕРУВАННЯ ВОЛОГІСТЮ ТЕПЛИЧНОГО ҐРУНТУ НА БАЗІ НЕЧІТКОЇ ЛОГІКИ

Relevance. Irrigation of the greenhouse soil plays an important role in the cultivation of greenhouses plants. Given the significant number of existing systems and methods on monitoring and irrigation of soil in the world, there are almost no systems that are based on fuzzy logic taking into account the growing season plants factor. Consequently, an urgent scientific task arises on developing of the monitoring a method of the greenhouse soil moisture content taking into account the types and periods of the greenhouse crops growing season. Purpose. Development of the method and implementation of the system prototype on monitoring and control of the greenhouse soils moisture content based on the fuzzy logic rules taking into account the types and periods of plants vegetation. Methodology. In course of the research, the following methods have been used: analysis and systematization of well-known scientific and applied results, experimental tests of computer-integrated equipment, synthesis and testing of hardware and software computer models on systems automation, comparative analysis of the modeling and experimental tests results. Results. The main scientific and applied results include: the algorithm and model for assessing plant parameters from the growing season, the mathematical model of the soil moisture dynamics, the fuzzy rules base for moisture control taking into account the types and periods of the agricultural crops, an experimental full-scale model of the computer-integrated system. Scientific novelty. The method of the computer-integrated monitoring and control of the greenhouse soils moisture content based on fuzzy logic has been developed, which, unlike the known ones, takes into account the influence of types and periods of growing crops, which allows precision control of relative humidity in real time. Practical significance. The mathematical model of the soils moisture dynamics, the structural diagram and algorithm of the system’s operation, the fuzzy logic rules base, the program code of the system and experimental model of the system have been obtained. All of these results can be scaled and modified depending on plant types, soil type and volume, planted surface area and fuel pump capacity. Figures 15, tables 7, references 22.

DB4HLS: A Database of High-Level Synthesis Design Space Explorations

High-level synthesis (HLS) frameworks allow to easily specify a large number of variants of the same hardware design by only acting on optimization directives. Nonetheless, the hardware synthesis of implementations for all possible combinations of directive values is impractical even for simple designs. Addressing this shortcoming, many HLS design space exploration (DSE) strategies have been proposed to devise directive settings leading to high-quality implementations while limiting the number of synthesis runs. All these works require considerable efforts to validate the proposed strategies and/or to build the knowledge base employed to tune abstract models, as both tasks mandate the syntheses of large collections of implementations. Currently, such data gathering is performed <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ad hoc</i> : 1) leading to a lack of standardization, hampering comparisons between DSE alternatives; and 2) posing a very high burden to researchers willing to develop novel DSE strategies. Against this backdrop, we here introduce DB4HLS, a database of exhaustive HLS explorations comprising more than 100 000 design points collected over four years equivalent of synthesis time. The open structure of DB4HLS allows the incremental integration of new DSEs, which can be easily defined with a dedicated domain-specific language. We think that of our database, available at <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><uri>https://www.db4hls.inf.usi.ch/</uri></monospace> , will be a valuable tool for the research community investigating automated strategies for the optimization of HLS-based hardware designs.