Hardware Synthesis Research Articles

Analysis of “SystemC” design flow for FPGA implementation

High level language termed as SystemC language is recently gaining popularity in VLSI industries especially in Hardware-Software co-design. Using SystemC, Hardware IPs can be modeled at system level which helps to reduce the time to market for SOCs. In most applications SystemC is utilized to verify functionality of the design. However there has been relatively less work done on the synthesis of equivalent hardware from SystemC. In this paper, Finite Impulse Response Filter and Greatest Common divisor are designed as examples in SystemC language and their corresponding synthesis flow from SystemC to FPGA is proposed. The proposed method of synthesis would be time saving than the conventional design and synthesis using HDL in RTL perspective.

A Holistic Approach Towards Intelligent Hotspot Prevention in Network-on-Chip-Based Multicores

Traffic hotspots, a severe form of network congestion, can be caused unexpectedly in a network-on-chip (NoC) due to the immanent spatio-temporal unevenness of application traffic. Hotspots reduce the NoC's effective throughput, where in the worst-case scenario, network traffic flows can be frozen indefinitely. To alleviate this problematic phenomenon several adaptive routing algorithms employ online load-balancing schemes, aiming to reduce the possibility of hotspots arising. Since most are not explicitly hotspotagnostic, they cannot completely prevent hotspot formation(s) as their reactive capability to hotspots is merely passive. This paper presents a pro-active Hotspot-Preventive Routing Algorithm (HPRA) which uses the advance knowledge gained from network embedded artificial neural network-based (ANN) hotspot predictors to guide packet routing in mitigating any unforeseen near-future hotspot occurrences. First, these ANN-based predictors are trained offline and during multicore operation they gather online statistical data to predict about-to-be-formed hotspots, promptly informing HPRA to take appropriate hotspot-preventive action(s). Next, in a holistic approach, additional ANN training is performed with data acquired after HPRA interferes, so as to further improve hotspot prediction accuracy; hence, the ANN mechanism does not only predict hotspots, but is also aware of changes that HPRA imposes upon the interconnect infrastructure. Evaluation results, including utilizing real application traffic traces gathered from parallelized workload executions onto a chip multiprocessor architecture, show that HPRA can improve network throughput up to 81 percent when compared with prior-art. Hardware synthesis results affirm the HPRA mechanism's moderate overhead requisites.

A processor for IoT applications: An assessment of design space and trade-offs

Contemporary embedded systems require low-power solutions while still keeping a minimum performance level, and this is even more acute in the Internet of Things (IoT) domain, with its vast design space. This work proposes a configurable RISC processor associated to a design flow that includes a hardware synthesis flow and a software toolchain. This design flow is useful to explore design space and trade-offs of processor cores for IoT applications, by enabling multiple hardware configurations with variable degrees of complexity, while maintaining compatibility with the chosen instruction set architecture, which is itself configurable. Results rely on example designs targeting a 65 nm technology and post-mapped hardware simulations of two benchmarks sets, the CoreMark and Mälardalen suites. These results indicate that substantial power savings can be obtained by tailoring the architecture to a given application class, while reducing hardware complexity and maintaining performance figures. Findings show that the proposed processor provides an interesting resource to target low-end and middle-sized IoT applications, while demonstrating that reducing hardware complexity usually leads to the best trade-off between performance and power.

On hardware synthesis and implementation of PLC programs in FPGAs

Many processes require controllers with an instant response (e.g. motor control, CNC machines). A high-performance PLC can be constructed with use of programmable logic devices. A lack of custom synthesis tools disables the use of standard languages widely accepted by automation designers. The paper presents the systematic process of a PLC program synthesis to hardware structure. An input PLC program is given according to the IEC61131-3 standard. The synthesis process has been developed for implementation of a program described with the LD and SFC languages. The essential idea of synthesis process is obtaining a massively parallel operating hardware structure that significantly reduces response processing time. The PLC program is translated into originally developed dedicated graph structure that enables a wide range of optimizations. In the next step, it is mapped into a hardware structure. In order to reduce resource requirements, a strategy with resource sharing is shown, which is an original extension of general mapping concepts. Modern FPGAs are equipped with arithmetic cores dedicated for signal processing, inspiring the development of the original DSP48 block mapping strategy. It attempts to utilize all features of the block in the pipelined calculation model. The considerations are summarized with the implementation result compared against standard PLC implementation, a mutual comparison of general hardware mapping, and with the use of DSP48 units.

Performance Analysis of OFDM Synchronization Using Customized Floating Point for Low Complexity

Orthogonal frequency-division multiplexing (OFDM) is a multi carrier modulation scheme mainly used for digital communications. The performance of OFDM system heavily depends on the synchronization scheme used. In most cases, the accuracy level of synchronization will be worsened by the error caused in fixed point arithmetic involved. In this paper, we analyze the impact of the fixed point arithmetic on the performance of the coarse timing and frequency synchronization. Here with an analytical approach through numerical simulations bit length of IEEE 754 standard single precision format is optimized according to the required degree of accuracy for low complexity. Also, a complete precision level requirement for FFT computations with all possible modulation types is obtained. The proposed precision model is compared with IEEE standard single precision model and its efficiency in OFDM synchronization process is proved through MATLAB simulations. Finally, the complexity reduction of proposed precision model in both addition and subtraction is proved against single precision format using hardware synthesis. Here we proved that more than 50% complexity reduction is achieved as compared to standard precision models without compromising quality. The quality retention of proposed model is proved in both timing and frequency synchronization process.

Design of LMS Adaptive Radar Detector for Non-homogeneous Interferences

ABSTRACTThe recent years have seen an unprecedented increase in the demand for superior performance of radar signal processor. The main challenge in a radar system is to maintain the probability of a false alarm rate constant even under an uncertain time-varying clutter environment. The objective of this paper is to develop a method for enhanced clutter/interference suppression by redesigning the radar detector in such a way to emphasize the target response and de-emphasize the clutter response. To achieve this, we have proposed a hardware architecture that implements least mean square algorithm-based adaptive filter along with a constant false alarm rate (CFAR) technique for the purpose of better detection of target under a non-homogeneous clutter environment. An adaptive design of the CFAR-filter technique has been used to improve probability of detection by increasing signal-to-noise ratio. The efficacy of the proposed architecture is corroborated with MATLAB simulations and hardware synthesis.

Hierarchical Structure-Based Fast Mode Decision for H.265/HEVC

The mode decision strategy adopted in the High Efficiency Video Coding test model increases the complexity drastically. In this paper, we present a course of low-complexity fast mode decision algorithms. First, the depth information of the colocated block from a previous frame is used to predict the size of current block. Next, for a certain sized block, the inter-prediction residual is analyzed to determine whether to terminate the mode decision process or to skip unnecessary modes and split the block into smaller sizes. After inter-prediction, a hardware-oriented low-complexity fast intra-mode decision algorithm is proposed. A fast discrete cross difference is adopted to detect the dominant direction of the block. In addition, four simple but efficient early termination strategies are proposed to terminate the rate-distortion optimization process properly. The simulation results show that these proposed algorithms reduce the encoding time by 54.0%-68.4% without incurring any noticeable performance degradation. Hardware synthesis results demonstrate that the proposed fast intra-mode decision algorithm can be easily implemented on a hardware platform with fewer resources consumed.

A Digital Realization of Astrocyte and Neural Glial Interactions.

The implementation of biological neural networks is a key objective of the neuromorphic research field. Astrocytes are the largest cell population in the brain. With the discovery of calcium wave propagation through astrocyte networks, now it is more evident that neuronal networks alone may not explain functionality of the strongest natural computer, the brain. Models of cortical function must now account for astrocyte activities as well as their relationships with neurons in encoding and manipulation of sensory information. From an engineering viewpoint, astrocytes provide feedback to both presynaptic and postsynaptic neurons to regulate their signaling behaviors. This paper presents a modified neural glial interaction model that allows a convenient digital implementation. This model can reproduce relevant biological astrocyte behaviors, which provide appropriate feedback control in regulating neuronal activities in the central nervous system (CNS). Accordingly, we investigate the feasibility of a digital implementation for a single astrocyte constructed by connecting a two coupled FitzHugh Nagumo (FHN) neuron model to an implementation of the proposed astrocyte model using neuron-astrocyte interactions. Hardware synthesis, physical implementation on FPGA, and theoretical analysis confirm that the proposed neuron astrocyte model, with significantly low hardware cost, can mimic biological behavior such as the regulation of postsynaptic neuron activity and the synaptic transmission mechanisms.

ARTL-Based Hardware Synthesis to Non-Heterogeneous Standard Cell ASIC Technologies

ARTL-Based Hardware Synthesis to Non-Heterogeneous Standard Cell ASIC Technologies

Function approximation by hardware spiking neural network

Spiking neural networks (SNN) represent a special class of artificial neural networks, where neu-ron models communicate by sequences of spikes. SNNs are often referred to as the third generation of neural networks that highly inspired from natural computing in the brain and recent advances in neuroscience. In this paper we implement biologically-inspired, hardware-realizable SNN architecture using integrate-and-fire units, which is capable of approximating a real-valued function. Based on the results of MATLAB simulations, hardware synthesis and FPGA implementation, it is demonstrated that the implemented hardware can approximate linear and nonlinear functions with low minimum relative error. This framework may represent a fundamental computational unit for the development of artificial SNN, opening new perspectives in pattern recognition tasks.

Digital multiplierless implementation of the biological FitzHugh–Nagumo model

High-accuracy implementation of biological neural networks (NN) is a task with high computational overheads, especially in the case of large-scale realizations of neuromorphic algorithms. This paper presents a set of piecewise linear FitzHugh–Nagumo (FHN) models, which can reproduce different behaviors, similar to the biological neuron. This paper presents a set of equations as a model to describe the mechanisms of a single neuron, which are implementable on digital platforms. Simulation results show that the model can reproduce different behaviors of the neuron. The proposed models are investigated, in terms of digital implementation feasibility and computational overhead, targeting low-cost hardware realization. Hardware synthesis and physical implementations on FPGA show that the proposed models can produce a range of neuron behaviors with higher performance and lower implementation costs compared to the original model.

A Hopf Resonator for 2-D Artificial Cochlea: Piecewise Linear Model and Digital Implementation

The mammalian auditory system is able to process sounds over an extraordinarily large dynamic range, which makes it possible to extract information from very small changes both in sound amplitude and frequency. Evidently, response of the cochlea is essentially nonlinear, where it operates within Hopf bifurcation boundaries to maximize tuning and amplification. This paper presents a set of piecewise linear (PWL) and multiplierless piecewise linear (MLPWL1 and MLPWL2) active cochlear models, which mimic a range of behaviors, similar to the biological cochlea. These proposed models show similar dynamical characteristics of the Hopf equation for the active nonlinear artificial cochlea. Accordingly, a compact model structure is proposed upon which a 2-D cochlea is developed. The proposed models are investigated, in terms of their digital realization and hardware cost, targeting large scale implementation. Hardware synthesis and physical implementation on a FPGA show that the proposed models can reproduce precise active cochlea behaviors with higher performance and considerably lower computational costs in comparison with the original model. Results indicate that the MLPWL1 model has a lower computational overhead, precision, and hardware cost, while the PWL model has a higher precision and dynamically tracks the original model. On the other hand, the MLPWL2 model outperforms the others in terms of accuracy, dynamical tracking of the original model and implementation cost. The gain variations of the original, PWL, MLPWL1, and MLPWL2 models are 230, 100, 105, and 230 dB, respectively. The mean normalized root mean square errors (NRMSEs) of the PWL, MLPWL1, and MLPWL2 models are 0.11%, 11.97%, and 0.34%, respectively, as compared to the original cochlear model.

Multiplier-less digital implementation of neuron–astrocyte signalling on FPGA

Experimental observations have shown that astrocytes are active partner in neural information processing which are mainly carried out by neurons. In this research, we investigate this issue and provide a computationally efficient digital circuit for neuron–astrocyte interactions. The firing dynamics of the neuron is described by Izhikevich model (spiking and bursting activities) and the calcium dynamics of a single astrocyte explained by a proposed model adapted from a functional model introduced by Postnov and colleagues. The new linear model makes it possible to design an efficient multiplier-less hardware architecture for digital implementation of neuron–astrocyte interaction on field-programmable gate array (FPGA). Using the proposed neuron–astrocyte circuit and based on the results of MATLAB simulation, hardware synthesis and FPGA implementation, it is demonstrated that the proposed digital astrocyte is able to change the neuron spiking frequency through bidirectional signaling. This circuit may represent a fundamental computational unit for the development of artificial neuron–astrocyte networks, opening new perspectives in pattern recognition tasks.

A bio-inspired stimulator to desynchronize epileptic cortical population models: A digital implementation framework

Pathophysiologic neural synchronization is a hallmark of several neurological disorders such as epilepsy. In addition, based on established neurophysiologic findings, astrocytes dynamically regulate the synaptic transmission and have key roles in stabilizing neural synchronization. Therefore, in the present study, based on the dynamic model of astrocyte, a digital bio-inspired stimulator is proposed to avoid the hyper-synchronous seizure-like activities in a cortical population model. The complete digital circuit of the close loop system that is the bio-inspired stimulator and the cortical population model are implemented in hardware on the ZedBoard development kit. Based on the results of MATLAB simulations, hardware synthesis and FPGA implementation, it is demonstrated that the digital bio-inspired stimulator can effectively prevent the occurrence of spontaneous paroxysmal episodes with a demand-controlled characteristic. In this way, the designed digital stimulator successfully maintains the normal ongoing activity.

A digital implementation of neuron–astrocyte interaction for neuromorphic applications

Recent neurophysiologic findings have shown that astrocytes play important roles in information processing and modulation of neuronal activity. Motivated by these findings, in the present research, a digital neuromorphic circuit to study neuron–astrocyte interaction is proposed. In this digital circuit, the firing dynamics of the neuron is described by Izhikevich model and the calcium dynamics of a single astrocyte is explained by a functional model introduced by Postnov and colleagues. For digital implementation of the neuron–astrocyte signaling, Single Constant Multiply (SCM) technique and several linear approximations are used for efficient low-cost hardware implementation on digital platforms. Using the proposed neuron–astrocyte circuit and based on the results of MATLAB simulations, hardware synthesis and FPGA implementation, it is demonstrated that the proposed digital astrocyte is able to change the firing patterns of the neuron through bidirectional communication. Utilizing the proposed digital circuit, it will be illustrated that information processing in synaptic clefts is strongly regulated by astrocyte. Moreover, our results suggest that the digital circuit of neuron–astrocyte crosstalk produces diverse neural responses and therefore enhances the information processing capabilities of the neuromorphic circuits. This is suitable for applications in reconfigurable neuromorphic devices which implement biologically brain circuits.

Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution

This paper presents a low-complexity algorithm and the corresponding hardware based on the coordinated polynomial solutions for solving line spectrum pairs (LSPs). To improve the computation of LSPs, the enhanced Tschirnhaus transform (ETT) is proposed to accelerate the coordinated polynomial solution. The proposed ETT can replace fractional multiplication with addition and shift operations, so unnecessary operations are avoided. To further simplify the hardware of the ETT, three designs are presented: the preprocessing block (PPB), the iterative root-finding block (IRFB), and the closed-form solution block (CFSB). The PPB provides a design with less gate counts that can effectively transform LPCs into general-form polynomials. Such polynomials can be further decomposed into roots using the proposed IRFB based on the Birge-Vieta method. A pipeline-recursive framework is implemented in the IRFB to save calculations. To improve hardware utilization, this paper also analyzes the coefficients relationship of the ETT by introducing the data dependency graph to design the proposed functional blocks in CFSB. The experimental results show that the proposed hardware achieves a 40-fold improvement in throughput and reduces 1.16% of gate counts at the hardware synthesis level; the chip area is 1.29 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The precision analysis indicates the average log spectral distance is 0.310. Moreover, the ETT in the proposed hardware only requires 29.9% of multiplication compared with the original one. Such results reveal that the proposed work is superior to the baseline work, thereby demonstrating the effectiveness of the proposed design.

Digital implementation of a biological astrocyte model and its application.

This paper presents a modified astrocyte model that allows a convenient digital implementation. This model is aimed at reproducing relevant biological astrocyte behaviors, which provide appropriate feedback control in regulating neuronal activities in the central nervous system. Accordingly, we investigate the feasibility of a digital implementation for a single astrocyte and a biological neuronal network model constructed by connecting two limit-cycle Hopf oscillators to an implementation of the proposed astrocyte model using oscillator-astrocyte interactions with weak coupling. Hardware synthesis, physical implementation on field-programmable gate array, and theoretical analysis confirm that the proposed astrocyte model, with considerably low hardware overhead, can mimic biological astrocyte model behaviors, resulting in desynchronization of the two coupled limit-cycle oscillators.

Обзор методов извлечения моделей из HDL-описаний

In this paper a survey of existing methods of model extraction from hardware system descriptions written in Hardware Description Languages (like Verilog and VHDL) is presented. There are many tasks in hardware and software design where models are applied. The most actual tasks that are mentioned in this paper are: code optimization, logical synthesis optimization, model abstraction, and functional verification. The model categories that are mostly described here are flow or dependency graph models and automata models. As for flow graphs or dependency graphs, the methods of program slices extraction are described in details. Program slices can be characterized as suitable enough for directed test generation. Almost all the described automata models are finite state machine models and extended finite state machine models and so methods of such models extraction are the most popular for logical synthesis optimization and for functional test generation. The tests that can be generated from automata models shows high coverage of the target description. The key problems of existing model extraction methods are: the complexity of an application to industrial hardware descriptions (because of their complex structure), lack of automation (sometimes the hardware designer’s knowledge is needed), the absence of open-source implementations. Also it is an actual task to create extendible frameworks for integration of different model extraction and analysis methods. Such framework can help in development of effective hybrid methods for hardware synthesis and verification.

Separable Beamforming For 3-D Medical Ultrasound Imaging

Three-dimensional ultrasound imaging is a promising medical imaging technology because of its ease of use and improved accuracy in diagnosis. However, its high computational complexity and resulting high power consumption has precluded its use in hand-held applications. In this paper, we present a separable beamforming method that greatly reduces computational complexity. Our method is based on decomposing the delay term in a way that minimizes the root-mean-square error caused by the decomposition. We analyze tradeoffs between the approximation error caused by the decomposition and computational complexity. Then, we present enhancements to the Sonic Millip3De hardware accelerator for ultrasound beamforming to implement separable beamforming. Using hardware synthesis targeting standard cells in 45 nm, we show that the proposed method allows us to boost the Sonic Millip3De frame rate from 1-2 Hz to 32 Hz while maintaining power consumption at 15 W. We validate image quality of our method using cyst phantom simulations in Field II. Our evaluation demonstrates that the proposed separable beamforming method can produce 3-D images with high quality that are comparable to those generated by non-separable beamforming.

Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC

In this paper, a course of low complexity Fast Mode Decision (FMD) algorithms as well as the corresponding hardware architecture is presented. Firstly, the depth information of co-located block from previous frame is used to predict the size of current block. Then, for a certain sized block, the inter prediction residual is analyzed to determine whether to terminate current check or to skip some unnecessary modes and split to smaller size. Finally, the corresponding hardware architecture is proposed based on state machine mechanism. Simulation results show that these proposed algorithms reduce the encoding time by 40.8∼ 70.3%, without incurring any noticeable performance degradation. Hardware synthesis results demonstrate that the proposed architecture achieves a max frequency of about 193 MHz.