Hardware-software Co-verification Research Articles

A rigorous approach to microprocessor verification using UVM

In today's fast-paced technology industry, microprocessors play an increasingly important role in a wide range of applications. However, verifying the correctness of complex microprocessor designs remains a significant challenge. To address this issue, a rigorous approach to microprocessor verification using the Universal Verification Methodology (UVM) is proposed. UVM provides a standardised and scalable approach to verifying digital designs, including microprocessors, and has been widely adopted in the industry. This research proposes a UVM-based verification framework for microprocessors that can identify and eliminate design errors early in the development cycle. The proposed approach covers functional verification, performance verification, and hardware-software co-verification. The effectiveness of the proposed approach is evaluated through a case study of a commercial microprocessor design, where the UVM-based verification framework successfully detected and resolved several design bugs. The results demonstrate the potential of the proposed rigorous approach to microprocessor verification using UVM to enhance the quality and reliability of microprocessor designs.

2L-3W: 2-Level 3-Way Hardware–Software Co-verification for the Mapping of Convolutional Neural Network (CNN) onto FPGA Boards

2L-3W: 2-Level 3-Way Hardware–Software Co-verification for the Mapping of Convolutional Neural Network (CNN) onto FPGA Boards

Design and efficient verification of network attached system on chip devices

Over the past, Ethernet has become a ubiquitous communication medium penetrating all kinds of application domains like industrial automation, where it easily outranked legacy fieldbus communication systems used so far. As a consequence, modern distributed embedded systems are beginning to rely on Ethernet as a shared communication medium. More often than not stringent target application constraints necessitate integrating the required functionality into a single chip as opposed to using commercial of the shelf components and modules. Although modern ASIC and FPGA technologies allow integrating fairly complex digital logic into comparatively small areas of Silicon, computing resources of embedded CPUs remain limited. If such a device is attached to a heavily loaded 1 G or even 10 G network environment, packet processing has to be implemented primarily in hardware to avoid overloading the CPU or even worse rendering the device unable to perform a given task, for example to respond to a request in a given time frame. Several packet filters with deep packet inspection capabilities operating independently from each other are required as well as dedicated hardware blocks capable of generating packets on their own without any interference of the CPU. Designing and especially efficiently verifying such SoC devices remains challenging. The design and architecture optimization process for a typical Ethernet-based building block of offload engines is presented together with a highly automated hardware-software co-verification approach. The paper concludes describing the design challenges, the architecture, and the implementation results of a single chip high performance IEEE1588-2008 clock synchronization node.

Hardware/Software Co-Verification: Models and Methods

An efficient hardware-software co-verification methodology is essential in the design of systems on boards (SOB) and systems on chips (SOC). The increasing complexity of hardware and software makes the challenge of their integration more difficult than ever. This paper addresses the correctness verification of mixed hardware-software systems prior to IC fabrication. It presents the requirements of an efficient verification methodology, the multilevel co-verification approach, and a wide set of co-verification models based on different techniques like co-simulation, in circuit emulation, and hardware emulation. For each model, we present its advantages, its restrictions, and its implementation techniques. Then we study the factors that drive the co-simulation performance and we show how to fairly estimate this performance for different configurations.