Design and efficient verification of network attached system on chip devices

Abstract

Over the past, Ethernet has become a ubiquitous communication medium penetrating all kinds of application domains like industrial automation, where it easily outranked legacy fieldbus communication systems used so far. As a consequence, modern distributed embedded systems are beginning to rely on Ethernet as a shared communication medium. More often than not stringent target application constraints necessitate integrating the required functionality into a single chip as opposed to using commercial of the shelf components and modules. Although modern ASIC and FPGA technologies allow integrating fairly complex digital logic into comparatively small areas of Silicon, computing resources of embedded CPUs remain limited. If such a device is attached to a heavily loaded 1 G or even 10 G network environment, packet processing has to be implemented primarily in hardware to avoid overloading the CPU or even worse rendering the device unable to perform a given task, for example to respond to a request in a given time frame. Several packet filters with deep packet inspection capabilities operating independently from each other are required as well as dedicated hardware blocks capable of generating packets on their own without any interference of the CPU. Designing and especially efficiently verifying such SoC devices remains challenging. The design and architecture optimization process for a typical Ethernet-based building block of offload engines is presented together with a highly automated hardware-software co-verification approach. The paper concludes describing the design challenges, the architecture, and the implementation results of a single chip high performance IEEE1588-2008 clock synchronization node.