Hardware Security Research Articles

Modeling and physical attack resistant authentication protocol with double PUFs

As new lightweight hardware security primitive, the physical unclonable function (PUF) is used in various hardware-based secure applications like keys generation and device authentication. But PUFs are vulnerable to modeling attacks using machine learning (ML) technology. To solve the problem, a dynamically configurable obfuscation unit for PUF using a dynamic linear feedback shift register (DLFSR) is proposed. The structure of this obfuscation unit can change with the clock cycle running, making the PUF difficult to model. Using the obfuscation unit, a dual-PUF-based mutual device authentication protocol for low-cost IoT systems is proposed. New technologies like dual-stage and device-to-server authentication are used to limit the amount of data that an attacker can obtain. A random pattern-based mechanism is introduced to the protocol to enhance the robustness against physical attacks. A mathematical model of the proposed unit is presented and analyzed. Experimental results on FPGA show that the design is simpler, more reliable, and lightweight. It can effectively resist ML-based attacks and physical attacks.

Fine-Grained Access Control with User Revocation in Smart Manufacturing

Collaborative manufacturing is a key enabler of Industry 4.0 that requires secure data sharing among multiple parties. However, intercompany data-sharing raises important privacy and security concerns, particularly given intellectual property and business-sensitive information collected by many devices. In this paper, we propose a solution that combines four technologies to address these challenges: Attribute-Based Encryption for data access control, blockchain for data integrity and non-repudiation, Hardware Security Modules for authenticity, and the Interplanetary File System for data scalability. We also use OpenID for dynamic client identification and propose a new method for user revocation in Attribute-Based Encryption. Our evaluation shows that the solution can scale up to 2,000,000 clients while maintaining all security guarantees.

Design and Analysis of a Secure Hardware Implementation for Cryptography Applications (2020)

Design and Analysis of a Secure Hardware Implementation for Cryptography Applications (2020)

Testing and reliability enhancement of security primitives: Methodology and experimental validation

The test of security primitives is particularly strategic as any bias coming from the implementation or environment can wreak havoc on the security it is intended to provide. This paper presents how some security properties are tested on hardware security primitives including True Random Number Generation (TRNG), Physically Unclonable Function (PUF), and cryptographic modules. Moreover, we discuss how the sensors embedded to protect cryptographic modules against fault injection attacks should be calibrated over time to fulfill the requirement it was designed for. The testing we discuss in this paper is different from the conventional testing where we consider a fault model and generate test patterns via an ATPG to detect such faults. The test of TRNG and PUF to ensure a high level of security is mainly about the entropy assessment, which requires specific statistical tests. The security against side-channel analysis (SCA) of cryptographic primitives, like the substitution box in symmetric cryptography, is generally ensured by masking. However, the hardware implementation of masking can be damaged by glitches, which create leakages on sensitive variables. Accordingly, a test method is to search for nets of the cryptographic netlist, which are vulnerable to glitches. Finally, the Digital Sensor (DS) is an efficient primitive to detect disturbances and raise alarms in the case of fault injection attack (FIA). The dimensioning of this primitive requires a precise test to take into account the environmental variations including aging.This paper extends on a conference paper presented at DFTS’21 by the same co-authors, where the test methodology for three critical security primitives is presented. In addition, in this paper, we add experimental validation to show how such testing methodology is applied in practice.

Experimental analysis of variability in WS2-based devices for hardware security

This work investigates the variability of tungsten disulfide (WS2)-based devices by experimental characterization in view of possible application in the field of hardware security. To this aim, a preliminary analysis was performed by measurements across voltages and temperatures on a set of seven Si/SiO2/WS2 back-gated devices, also considering the effect of different stabilization conditions on their conductivity. Obtained results show appreciable variability in the conductivity, while also revealing similar dependence on bias and temperature across tested devices. Overall, our analysis demonstrates that WS2-based devices can be potentially exploited to ensure adequate randomness and robustness against environmental variations and then used as building blocks for hardware security primitives.

A memristor fingerprinting and characterisation methodology for hardware security

The modern IC supply chain encompasses a large number of steps and manufacturers. In many applications it is critically important that chips are of the right quality and are assured to have been obtained from the legitimate supply chain. To this end, it is necessary to be able to uniquely identify systems to aid in supply chain tracking and quality assurance. Many identifiers, however, can be cloned onto counterfeit devices and are therefore untrustworthy. This paper proposes a methodology for using post-CMOS memristor devices as a fingerprint to uniquely identify ICs. To achieve this, memristors’ unique and variable I–V characteristics are exploited to produce a fingerprint that can be generally applicable to a wide variety of different memristor technologies and identifiable over time, even where cell retention is non-ideal. In doing so it aims to minimise the hardware required on-chip both to minimise cost and maximise the auditability of the system. The methodology is applied to a text {TiO}_x memristor technology, and shown to be able to identify cells in a set.

A RRAM-Based True Random Number Generator with 2T1R Architecture for Hardware Security Applications.

Resistance random access memory (RRAM) based true random number generator (TRNG) has great potential to be applied to hardware security owing to its intrinsic switching variability. Especially the high resistance state (HRS) variation is usually taken as the entropy source of RRAM-based TRNG. However, the small HRS variation of RRAM may be introduced owing to fabrication process fluctuations, which may lead to error bits and be vulnerable to noise interference. In this work, we propose an RRAM-based TRNG with a 2T1R architecture scheme, which can effectively distinguish the resistance values of HRS with an accuracy of 1.5 kΩ. As a result, the error bits can be corrected to a certain extent while the noise is suppressed. Finally, a 2T1R RRAM-based TRNG macro is simulated and verified using the 28 nm CMOS process, which suggests its potential for hardware security applications.

An Efficient Algorithm and Architecture for the VLSI Implementation of Integer DCT That Allows an Efficient Incorporation of the Hardware Security with a Low Overhead

In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm demonstrates multiple benefits specific to integer transforms with efficient hardware implementation and sufficient precision in approximating irrational transform coefficients for practical applications. The proposed integer DCT algorithm can be efficiently restructured into five regular and modular computational structures of lengths of four and one of length two called pseudo-cycle convolutions which translate into efficient VLSI implementations using systolic arrays. Moreover, besides an efficient VLSI implementation with high-speed performances due to the parallel decomposition of the proposed integer DCT algorithm, the proposed VLSI architecture uses a tag control mechanism that facilitates the integration of an obfuscation technique that significantly improves the hardware security with low overheads, maintaining all the implementation performances.

Design of programmable hardware security modules for enhancing blockchain based security framework

Globalization of the chip design and manufacturing industry has imposed significant threats to the hardware security of integrated circuits (ICs). It has made ICs more susceptible to various hardware attacks. Blockchain provides a trustworthy and distributed platform to store immutable records related to the evidence of intellectual property (IP) creation, authentication of provenance, and confidential data storage. However, blockchain encounters major security challenges due to its decentralized nature of ledgers that contain sensitive data. The research objective is to design a dedicated programmable hardware security modules scheme to safeguard and maintain sensitive information contained in the blockchain networks in the context of the IC supply chain. Thus, the blockchain framework could rely on the proposed hardware security modules and separate the entire cryptographic operations within the system as stand-alone hardware units. This work put forth a novel approach that could be considered and utilized to enhance blockchain security in real-time. The critical cryptographic components in blockchain secure hash algorithm-256 (SHA-256) and the elliptic curve digital signature algorithm are designed as separate entities to enhance the security of the blockchain framework. Physical unclonable functions are adopted to perform authentication of transactions in the blockchain. Relative comparison of designed modules with existing works clearly depicts the upper hand of the former in terms of performance parameters.

Simulation of SDN in mininet and detection of DDoS attack using machine learning

Most contemporary businesses are embracing software defined networking (SDN), a developing architecture that enables an aerial-like perspective of the entire network. SDN operates by virtualizing the network and provides advantages including improved performance, visibility, speed, and scalability. SDN attempts to divide the network control plane from the forwarding plane. The control plane, which includes one or more controllers and incorporates complete intelligence, is thought of as the brain of the SDN. However, SDN has challenges with controller vulnerability, flexibility, and hardware security. But distributed denial of service (DDoS) assaults constitutes a serious threat to the SDN. Transmission control protocol-synchronized (TCP-SYN) floods, a common cyberattack that can harm SDNs, can deplete network resources by opening an excessive number of illegitimate TCP connections. In this research, we provide an OpenFlow port statistic-based architecture for machine learning (ML) enabled TCP-SYN flood detection. This research showed that ML models like support vector machine (SVM), Navie Bayes, and multi-layered perceptron can distinguish between regular traffic and SYN flood traffic and can mitigate the impacts of the attacking node on the network. Results showed that the multilayered perceptron can classify the traffic with highest accuracy of 99.75% for the simulation dataset.

A survey on security analysis of machine learning-oriented hardware and software intellectual property

Intellectual Property (IP) includes ideas, innovations, methodologies, works of authorship (viz., literary and artistic works), emblems, brands, images, etc. This property is intangible since it is pertinent to the human intellect. Therefore, IP entities are indisputably vulnerable to infringements and modifications without the owner’s consent. IP protection regulations have been deployed and are still in practice, including patents, copyrights, contracts, trademarks, trade secrets, etc., to address these challenges. Unfortunately, these protections are insufficient to keep IP entities from being changed or stolen without permission. As for this, some IPs require hardware IP protection mechanisms, and others require software IP protection techniques. To secure these IPs, researchers have explored the domain of Intellectual Property Protection (IPP) using different approaches. In this paper, we discuss the existing IP rights and concurrent breakthroughs in the field of IPP research; provide discussions on hardware IP and software IP attacks and defense techniques; summarize different applications of IP protection; and lastly, identify the challenges and future research prospects in hardware and software IP security.

Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key

This article proposes a robust encrypted protein molecular biometric signature-based hardware security approach to secure hardware accelerators (like digital signal processing (DSP) and multimedia intellectual property (IP) cores) against threats of piracy/IP counterfeiting and ownership abuse. In the proposed approach, protein molecular biometric signature is formulated by taking the protein sequence of 20 different unique amino acid combinations from human body protein sample, followed by robust encryption using facial biometric key and encodings. This IP vendor’s encrypted protein molecular biometric signature is then subsequently converted into its corresponding digital proof, followed by embedding into the design as a covert protein molecular signature security constraint, thus producing a secured hardware accelerator design. The proposed approach is more robust than recent hardware security approaches proposed in the literature in terms of stronger proof of ownership (authorship) as well as tamper tolerance (TT) ability. The results present the following analysis of the proposed protein molecular biometric signature approach: 1) very low probability of coincidence (Pc) metric (signifying strength of digital proof) for different DSP hardware accelerators in the range of 3.40E-13–6.33E-2 and 2) stronger TT ability in the range of 5.39E <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 67–1.0E <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 421 for different DSP hardware accelerators.

Fully Ferroelectric-FETs Reservoir Computing Network for Temporal and Random Signal Processing

Reservoir computing (RC), a derivation of recurrent neural networks (RNNs), is an energy-efficient computational framework suitable for temporal signal processing. Owing to the short-term and long-term memory capability, the ferroelectric field-effect transistor (FeFET) is regarded as a promising hardware component for implementing RC networks. This article aims to optimize the fully FeFETs RC network by evaluating the recognition accuracy in various classification tasks, which includes the operating voltage sequence, device numbers as well as connection methods. The physical random telegraph noise (RTN), working as an ideal temporal and random signal, is investigated and extended by using the optimized fully FeFET RC network, resulting in a rapid time constant extraction method. Our findings may provide the broad potential for hardware security and cyber security based on the fully FeFET RC network.

A cycle-level recovery method for embedded processor against HT tamper

As the core of Internet of Things (IoT), embedded processors are being used more and more extensive. However, embedded processors face various hardware security issues such as hardware trojans (HT) and code tamper attacks. In this paper, a cycle-level recovery method for embedded processor against HT tamper is proposed, which builds two hardware-implementation units, a General-Purpose Register (GPRs) backup unit and a PC rollback unit. Once a HT tamper is detected, the two units will carry out fast recovery through rolling back to the exact PC address corresponding to the wrong instruction and resuming the instruction execution. An open RISC-V core of PULPino is adopted for recovery mechanism verification, the experimental results and hardware costs show that the proposed method could guarantee the processor restore from abnormal state in real time with a reasonable hardware overhead.

A Comprehensive Formalization of Propositional Logic in Coq: Deduction Systems, Meta-Theorems, and Automation Tactics

The increasing significance of theorem proving-based formalization in mathematics and computer science highlights the necessity for formalizing foundational mathematical theories. In this work, we employ the Coq interactive theorem prover to methodically formalize the language, semantics, and syntax of propositional logic, a fundamental aspect of mathematical reasoning and proof construction. We construct four Hilbert-style axiom systems and a natural deduction system for propositional logic, and establish their equivalences through meticulous proofs. Moreover, we provide formal proofs for essential meta-theorems in propositional logic, including the Deduction Theorem, Soundness Theorem, Completeness Theorem, and Compactness Theorem. Importantly, we present an exhaustive formal proof of the Completeness Theorem in this paper. To bolster the proof of the Completeness Theorem, we also formalize concepts related to mappings and countability, and deliver a formal proof of the Cantor–Bernstein–Schröder theorem. Additionally, we devise automated Coq tactics explicitly designed for the propositional logic inference system delineated in this study, enabling the automatic verification of all tautologies, all internal theorems, and the majority of syntactic and semantic inferences within the system. This research contributes a versatile and reusable Coq library for propositional logic, presenting a solid foundation for numerous applications in mathematics, such as the accurate expression and verification of properties in software programs and digital circuits. This work holds particular importance in the domains of mathematical formalization, verification of software and hardware security, and in enhancing comprehension of the principles of logical reasoning.

IoT based smart home automation using blockchain and deep learning models.

For the past few years, the concept of the smart house has gained popularity. The major challenges concerning a smart home include data security, privacy issues, authentication, secure identification, and automated decision-making of Internet of Things (IoT) devices. Currently, existing home automation systems address either of these challenges, however, home automation that also involves automated decision-making systems and systematic features apart from being reliable and safe is an absolute necessity. The current study proposes a deep learning-driven smart home system that integrates a Convolutional neural network (CNN) for automated decision-making such as classifying the device as "ON" and "OFF" based on its utilization at home. Additionally, to provide a decentralized, secure, and reliable mechanism to assure the authentication and identification of the IoT devices we integrated the emerging blockchain technology into this study. The proposed system is fundamentally comprised of a variety of sensors, a 5 V relay circuit, and Raspberry Pi which operates as a server and maintains the database of each device being used. Moreover, an android application is developed which communicates with the Raspberry Pi interface using the Apache server and HTTP web interface. The practicality of the proposed system for home automation is tested and evaluated in the lab and in real-time to ensure its efficacy. The current study also assures that the technology and hardware utilized in the proposed smart house system are inexpensive, widely available, and scalable. Furthermore, the need for a more comprehensive security and privacy model to be incorporated into the design phase of smart homes is highlighted by a discussion of the risks analysis' implications including cyber threats, hardware security, and cyber attacks. The experimental results emphasize the significance of the proposed system and validate its usability in the real world.

A Graphene-Based Straintronic Physically Unclonable Function.

Physically unclonable functions (PUFs) are an integral part of modern-day hardware security. Various types of PUFs already exist, including optical, electronic, and magnetic PUFs. Here, we introduce a novel straintronic PUF (SPUF) by exploiting strain-induced reversible cracking in the contact microstructures of graphene field-effect transistors (GFETs). We found that strain cycling in GFETs with a piezoelectric gate stack and high-tensile-strength metal contacts can lead to an abrupt transition in some GFET transfer characteristics, whereas other GFETs remain resilient to strain cycling. Strain sensitive GFETs show colossal ON/OFF current ratios >107, whereas strain-resilient GFETs show ON/OFF current ratios <10. We fabricated a total of 25 SPUFs, each comprising 16 GFETs, and found near-ideal performance. SPUFs also demonstrated resilience to regression-based machine learning (ML) attacks in addition to supply voltage and temporal stability. Our findings highlight the opportunities for emerging straintronic devices in addressing some of the critical needs of the microelectronics industry.

A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks

Modeling attacks such as machine learning attacks are pretty efficient in breaking hardware security primitives like silicon strong physical unclonable functions (PUFs). As compared to regular strong PUFs such as arbiter PUFs and lightweight (LW)-PUFs, subthreshold current array (SCA)-PUFs exhibit a better resilience against modeling attacks since they utilize the non-linear relationship between the subthreshold current and gate voltage of transistors to obfuscate the corresponding relationship between input challenge and output response. Unfortunately, the degree of non-linearity (DoNL) within SCA-PUFs is still not sufficiently high to resist against state-of-the-art modeling attacks. Therefore, to further enhance DoNL for resisting against modeling attacks, a new strong PUF architecture is proposed in this paper by embedding reconfigurable neural networks (RNNs) into SCA-PUFs. Mathematical foundations are established for finding appropriate RNNs that are able to maximize the DoNL of an SCA-PUF. As shown in the result, when state-of-the-art modeling attacks like Lagrange multiplier attacks (LMAs) are selected, the robustness of the proposed RNN-embedded SCA-PUF is enhanced over 20 times with less than 18.5% power and area overhead as compared to a regular SCA-PUF.

Cyber-Physical System for Diagnostic Along the Controlled Section of the Oil Pipeline

The purpose of the work is to develop an experimental model of the control system for compliance with turns along the control length of the pipeline. The open issue of detecting oil product leaks along the controlled section of the pipeline. Preliminary analysis of leak detection methods and principles of operation of hardware and software security diagnostics of the state of pipe transport networks has been considered. A method of studying experimental data and presenting results has been developed. Different literature sources have been analyzed, these literature sources provide information about real cases of pipeline system diagnostics and leak or defect detection. The software and hardware part of the control systems for conducting checks along the control part of the pipeline have been developed, and checks and evaluations of the results of the system checks have been carried out.

Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications

The generation of random numbers is crucial for practical implementations of cryptographic algorithms. In this sense, hardware security modules (HSMs) include true random number generators (TRNGs) implemented in hardware to achieve good random number generation. In the case of cryptographic algorithms implemented on FPGAs, the hardware implementation of RNGs is limited to the programmable cells in the device. Among the different proposals to obtain sources of entropy and process them to implement TRNGs, those based in ring oscillators (ROs), operating in parallel and combined with XOR gates, present good statistical properties at the cost of high area requirements. In this paper, these TRNGs are revisited, showing a method for area optimization independently of the FPGA technology used. Experimental results show that three ring oscillators requiring only three LUTs are enough to build a TRNG on Artix 7 devices from Xilinx with a throughput of 33.3 Kbps, which passes NIST tests. A throughput of 50 Kbps can be achieved with four ring oscillators, also requiring three LUTs in Artix 7 devices, while 100 Kbps can be achieved using an structure with four ring oscillators requiring seven LUTs.