Hardware Security Primitives Research Articles

Volatile threshold switching devices for hardware security primitives: Exploiting intrinsic variability as an entropy source

In the age of the Internet of Things, the proliferation of edge devices has resulted in a significant increase in personal information that is susceptible to theft and counterfeiting at various stages of data communication. As a result, substantial attention has been focused on hardware (HW) security elements, such as the true random number generator and physical unclonable function. With the recent surge in research and development of emerging memristors, which exploit the inherent variability of these devices, there has been a notable increase in studies on HW security. Particularly, volatile threshold switch (TS) devices, which exhibit insulator/metal characteristics below/above a certain threshold voltage, show great promise as security devices due to their lower power consumption and higher cycling endurance compared to nonvolatile memory devices. Despite the promising attributes and increasing demand for TS devices for HW security, there remains a lack of a comprehensive overview covering various TS devices and their potential contributions to HW privacy. To address this gap, this review provides an encompassing analysis of different types of TS devices and their performance in HW security literature, providing insight into current limitations and the future prospects of HW security primitives based on TS devices.

Electrically‐Reconfigurable Extremely‐High Density Physical Unclonable Cryptographic Keys Based on Aurivillius Ferroelectrics

AbstractIn the era of information, emerging hardware security primitives, i.e., hardware random number generators and physically unclonable functions, hold profound promise for the establishment of exceptionally secure network information systems. Nonetheless, these potential solutions are constrained by inherent drawbacks, including the need for additional error correction circuits or algorithms, heightened susceptibility to environmental interference, and limited data density. This paper demonstrates the extremely high‐density, physical‐unclonable cryptographic keys by harnessing stochastically ferroelectric domain polarizations in Aurivillius ferroelectric material CaBi2Nb2O9 (CBNO). Ferroelectric polarization of CBNO nanodomains can serve as a robust source of physical unclonable entropy. Through the application of high‐speed voltage pulses, the inherent randomness of ferroelectric polarizations can be enhanced, thereby yielding cryptographic keys characterized by remarkable uniformity, uniqueness, and negligible environmental sensitivity. More importantly, the voltage pulse operations facilitate the configurability of the ferroelectric cryptographic keys with no correlation. An unprecedented data density of 435 Gbit µm−2 is therefore achievable with a miniaturized CBNO of less than 1 um2. Notably, the reconfigured keys successfully pass the National Institute of Standards and Technology random number tests without requiring additional post‐processing steps. Emanating from the inherent attributes of the material, these high‐density ferroelectric keys confer intrinsic advantages to information security, evincing substantial resistance to duplication or cloning.

Advancing Hardware Security: A Review and Novel Design of Configurable Arbiter PUF with DCM-Induced Metastability for Enhanced Resource Efficiency and Unpredictability

As the Internet of Things (IoT) and Blockchain technologies continue to assert their dominance in the technical landscape, the demand to enhance security measures becomes foremost. In this context, Physical Unclonable Functions (PUFs) are widely used hardware security primitives that can be used to solve a wide range of security issues. To support hardware security solutions, this paper presents an extensive overview and analysis of the existing Physical Unclonable Functions (PUFs) used as True Random Number Generators (TRNGs). Recognizing the shortcomings of current PUF designs, we propose a configurable Arbiter PUF design employing Digital Clock Manager (DCM)-induced metastability as an entropy source, presenting a robust solution for evolving hardware security. To mitigate the adverse consequences of metastability, the proposed Arbiter PUF includes a Carry Chain primitive with four Flip-Flop clones. Acknowledging the constantly evolving IoT and Blockchain environment, the suggested configurable Arbiter PUF is made to satisfy the highest security standards. By exploiting the inherent variations in FPGA technology, we aim to reduce system resource and area consumption, aligning with the efficiency criteria of modern applications. The system's performance is additionally enhanced by an on-chip post-processing based on DSP. Simulation results demonstrate successful implementation on a Xilinx Basys-3 FPGA board, offering a scalable and efficient solution. The generated sequences of the proposed PUF undergo rigorous testing, including National Institute of Standards and Technology (NIST) statistical tests for uniqueness, reliability, and randomness. This holistic approach aims to improve the PUF's performance and security.

A low-overhead and high-reliability physical unclonable function (PUF) for cryptography

Silicon Physical unclonable functions (PUFs) are regarded as emerging hardware security primitives that can be used for generating secret keys for cryptographic algorithms. Unfortunately, the reliability issues greatly limit the applications of most PUFs since ambient noises and aging issues may alter the output responses of the PUFs. In this paper, a novel error calibration technique (ECT) based on average sampling circuit (ASC) and self-checking circuit (SCC) is proposed for significantly boosting the reliability of PUFs. The primary role of ASC is filtering the ambient noises that may affect the output responses of the PUFs. In contrast, SCC rehabilitates the PUFs once aging issues damage the process mismatches within the PUFs. As shown in the result, a PUF with the proposed ECT is able to achieve a 99% reliability with a 50 Mbps throughput.

Concealable physical unclonable function generation and an in-memory encryption machine using vertical self-rectifying memristors.

The importance of hardware security increases significantly to protect the vast amounts of private data stored on edge devices. Physical unclonable functions (PUFs) are gaining prominence as hardware security primitives due to their ability to generate true random digital keys by exploiting the inherent randomness of the physical devices. Traditional approaches, however, require significant data movement between memory units and PUF generation circuits to perform encryption, presenting considerable energy efficiency and security challenges. This study introduces an innovative approach where PUF key generation and encryption are accomplished in the same vertically integrated resistive random access memory (V-RRAM), alleviating the data movement issue. The proposed V-RRAM encryption machine offers concealable PUFs, high area efficiency, and multi-thread data handling using parallel XOR logic operations. The encryption machine is compared with other machines, demonstrating the highest spatiotemporal cost-effectiveness.

A robust architecture of ring oscillator PUF: Enhancing cryptographic security with configurability

Physically Unclonable Functions (PUFs) are becoming more widely recognized as tamper-resistant, high-entropy hardware security primitives. Leveraging the intrinsic manufacturing properties of integrated circuits, PUFs provide a lightweight, cost-effective technique for device identification and cryptographic key generation. Despite the existence of various PUF designs and architectures, the ring oscillator (RO) PUF stands out as one of the most notable. This significance is due to its simplicity of implementation and outstanding performance metrics. However, traditional RO-PUFs are often classified as weak PUFs because they support a limited size of input-output combinations. This paper introduces a configurable inversion unit designed to construct a lightweight, robust architecture configurable (RAC) RO-PUF. The proposed unit comprises an XOR gate, an XNOR gate, and a multiplexer. The RACRO-PUF significantly increases the size of generated output bits while efficiently utilizing minimal hardware resources. The performance of the RACRO-PUF stands out in evaluations, recording a uniqueness of 49.78 %, uniformity of 49.42 %, reliability of 97.72 %, and impressive randomness of 98.34 %.

CNT-PUFs: Highly Robust and Heat-Tolerant Carbon-Nanotube-Based Physical Unclonable Functions.

In this work, we explored a highly robust and unique Physical Unclonable Function (PUF) based on the stochastic assembly of single-walled Carbon NanoTubes (CNTs) integrated within a wafer-level technology. Our work demonstrated that the proposed CNT-based PUFs are exceptionally robust with an average fractional intra-device Hamming distance well below 0.01 both at room temperature and under varying temperatures in the range from 23 ∘C to 120 ∘C. We attributed the excellent heat tolerance to comparatively low activation energies of less than 40 meV extracted from an Arrhenius plot. As the number of unstable bits in the examined implementation is extremely low, our devices allow for a lightweight and simple error correction, just by selecting stable cells, thereby diminishing the need for complex error correction. Through a significant number of tests, we demonstrated the capability of novel nanomaterial devices to serve as highly efficient hardware security primitives.

Testing and reliability enhancement of security primitives: Methodology and experimental validation

The test of security primitives is particularly strategic as any bias coming from the implementation or environment can wreak havoc on the security it is intended to provide. This paper presents how some security properties are tested on hardware security primitives including True Random Number Generation (TRNG), Physically Unclonable Function (PUF), and cryptographic modules. Moreover, we discuss how the sensors embedded to protect cryptographic modules against fault injection attacks should be calibrated over time to fulfill the requirement it was designed for. The testing we discuss in this paper is different from the conventional testing where we consider a fault model and generate test patterns via an ATPG to detect such faults. The test of TRNG and PUF to ensure a high level of security is mainly about the entropy assessment, which requires specific statistical tests. The security against side-channel analysis (SCA) of cryptographic primitives, like the substitution box in symmetric cryptography, is generally ensured by masking. However, the hardware implementation of masking can be damaged by glitches, which create leakages on sensitive variables. Accordingly, a test method is to search for nets of the cryptographic netlist, which are vulnerable to glitches. Finally, the Digital Sensor (DS) is an efficient primitive to detect disturbances and raise alarms in the case of fault injection attack (FIA). The dimensioning of this primitive requires a precise test to take into account the environmental variations including aging.This paper extends on a conference paper presented at DFTS’21 by the same co-authors, where the test methodology for three critical security primitives is presented. In addition, in this paper, we add experimental validation to show how such testing methodology is applied in practice.

Experimental analysis of variability in WS2-based devices for hardware security

This work investigates the variability of tungsten disulfide (WS2)-based devices by experimental characterization in view of possible application in the field of hardware security. To this aim, a preliminary analysis was performed by measurements across voltages and temperatures on a set of seven Si/SiO2/WS2 back-gated devices, also considering the effect of different stabilization conditions on their conductivity. Obtained results show appreciable variability in the conductivity, while also revealing similar dependence on bias and temperature across tested devices. Overall, our analysis demonstrates that WS2-based devices can be potentially exploited to ensure adequate randomness and robustness against environmental variations and then used as building blocks for hardware security primitives.

Hardware and Information Security Primitives Based on 2D Materials and Devices.

Hardware security is a major concern for the entire semiconductor ecosystem that accounts for billions of dollars in annual losses. Similarly, information security is a critical need for the rapidly proliferating edge devices that continuously collect and communicate a massive volume of data. While silicon-based complementary metal-oxide-semiconductor technology offers security solutions, these are largely inadequate, inefficient, and often inconclusive, as well as resource intensive in time, energy, and cost, leading to tremendous room for innovation in this field. Furthermore, silicon-based security primitives have shown vulnerability to machine learning (ML) attacks. In recent years, 2D materials such as graphene and transition metal dichalcogenides have been intensely explored to mitigate these security challenges. In this review, 2D-materials-based hardware security solutions such as camouflaging, true random number generation, watermarking, anticounterfeiting, physically unclonable functions, and logic locking of integrated circuits (ICs) are summarized with accompanying discussion on their reliability and resilience to ML attacks. In addition, the role of native defects in 2D materials in developing high entropy hardware security primitives is also examined. Finally, the existing challenges for 2D materials, which must be overcome for large-scale deployment of 2D ICs to meet the security needs of the semiconductor industry, are discussed.

A novel hardware authentication primitive against modeling attacks

SummaryTraditional hardware security primitives such as physical unclonable functions (PUFs) are quite vulnerable to machine learning (ML) attacks. The primary reason is that PUFs rely on process mismatches between two identically designed circuit blocks to generate deterministic math functions as the secret information sources. Unfortunately, ML algorithms are pretty efficient in modeling deterministic math functions. In order to resist against ML attacks, in this letter, a novel hardware security primitive named neural network (NN) chain is proposed by utilizing noise data to generate chaotic NNs for achieving authentication. In a NN chain, two independent batches of noise data are utilized as the input and output training data of NNs, respectively, to maximize the uncertainty within the NN chain. In contrast to a regular PUF, the proposed NN chain is capable of achieving over 20 times ML attack‐resistance and 100% reliability with less than 39% power and area overhead.

A Design Strategy to Improve Machine Learning Resiliency for Ring Oscillator Physically Unclonable Function

Physically unclonable functions (PUFs) are hardware security primitives that utilize non-reproducible manufacturing variations to provide device-specific challenge-response pairs (CRPs). Such primitives are desirable for applications such as communication and intellectual property protection. PUFs have been gaining considerable interest from both the academic and industrial communities because of their simplicity and stability. However, many recent studies have exposed PUFs to machine-learning (ML) modeling attacks. To improve the resilience of a system to general ML attacks instead of a specific ML technique, a common solution is to improve the complexity of the system. Structures, such as XOR-PUFs, can significantly increase the nonlinearity of PUFs to provide resilience against ML attacks. However, an increase in complexity often results in an increase in area and/or a decrease in reliability. This study proposes a lightweight ring oscillator (RO)-based PUFs using an additional modulus process to improve ML resiliency. The idea was to increase the complexity of the RO-PUF without significant hardware overhead by applying a modulus process to the outcomes from the RO frequency counter. We also present a thorough investigation of the design space to balance ML resiliency and other performance metrics such as reliability, uniqueness, and uniformity.

MCRO-PUF: A Novel Modified Crossover RO-PUF with an Ultra-Expanded CRP Space

With the expanding use of the Internet of Things (IoT) devices and the connection of humans and devices to the Internet, the need to provide security in this field is constantly growing. The conventional cryptographic solutions need the IoT device to store secret keys in its non-volatile memory (NVM) leading the system to be vulnerable to physical attacks. In addition, they are not appropriate for IoT applications due to their complex calculations. Thus, physically unclonable functions (PUFs) have been introduced to simultaneously address these issues. PUFs are lightweight and easy-to-access hardware security primitives which employ the unique characteristics of integrated circuits (ICs) to generate secret keys. Among all proposed PUFs, ring oscillator PUF (RO-PUF) has had a more suitable structure for hardware implementation because of its high reliability and easier providing of circuital symmetry. However, RO-PUF has not been so attractive for authentication purposes due to its limited supported challenge-response pairs (CRPs). A few efforts have been made in recent years that could successfully improve the RO-PUF CRP space, such as configurable RO-PUF (CRO-PUF). In this paper, by considerably improving the CRO-PUF structure and adding spare paths, we propose a novel strong RO-PUF structure that exponentially grows the CRP space and dramatically reduces the hardware cost. We implement our design on a simple and low-cost FPGA chip named XC6SLX9-2tqg144, stating that the proposed design can be used in IoT applications. In addition, to improve the CRP space, our design creates a suitable improvement in different security/performance terms of the generated responses, and dramatically outperforms the state-of-the-art. The average reliability, uniqueness, and uniformity of the responses generated are 99.55%, 48.49%, and 50.99%, respectively.

Physics inspired compact modelling of hbox {BiFeO}_3 based memristors

With the advent of the Internet of Things, nanoelectronic devices or memristors have been the subject of significant interest for use as new hardware security primitives. Among the several available memristors, BiFemathrm{O}_{3} (BFO)-based electroforming-free memristors have attracted considerable attention due to their excellent properties, such as long retention time, self-rectification, intrinsic stochasticity, and fast switching. They have been actively investigated for use in physical unclonable function (PUF) key storage modules, artificial synapses in neural networks, nonvolatile resistive switches, and reconfigurable logic applications. In this work, we present a physics-inspired 1D compact model of a BFO memristor to understand its implementation for such applications (mainly PUFs) and perform circuit simulations. The resistive switching based on electric field-driven vacancy migration and intrinsic stochastic behaviour of the BFO memristor are modelled using the cloud-in-a-cell scheme. The experimental current–voltage characteristics of the BFO memristor are successfully reproduced. The response of the BFO memristor to changes in electrical properties, environmental properties (such as temperature) and stress are analyzed and consistant with experimental results.

Implementation and characterization of flash‐based hardware security primitives for cryptographic key generation

AbstractHardware security primitives, also known as physical unclonable functions (PUFs), perform innovative roles to extract the randomness unique to specific hardware. This paper proposes a novel hardware security primitive using a commercial off‐the‐shelf flash memory chip that is an intrinsic part of most commercial Internet of Things (IoT) devices. First, we define a hardware security source model to describe a hardware‐based fixed random bit generator for use in security applications, such as cryptographic key generation. Then, we propose a hardware security primitive with flash memory by exploiting the variability of tunneling electrons in the floating gate. In accordance with the requirements for robustness against the environment, timing variations, and random errors, we developed an adaptive extraction algorithm for the flash PUF. Experimental results show that the proposed flash PUF successfully generates a fixed random response, where the uniqueness is 49.1%, steadiness is 3.8%, uniformity is 50.2%, and min‐entropy per bit is 0.87. Thus, our approach can be applied to security applications with reliability and satisfy high‐entropy requirements, such as cryptographic key generation for IoT devices.

Spintronic Physical Unclonable Functions Based on Field-Free Spin-Orbit-Torque Switching.

Physical unclonable function(PUFs) utilize inherent random physical variations of solid-state devices and are a core ingredient of hardware security primitives. PUFs promise more robust information security than that provided by the conventional software-based approaches. While silicon- and memristor-based PUFs are advancing, their reliability and scalability require further improvements. These are currently limited by output fluctuations and associated additional peripherals. Here, highly reliable spintronic PUFs that exploit field-free spin-orbit-torque switching in IrMn/CoFeB/Ta/CoFeB structures are demonstrated. It is shown that the stochastic switching polarity of the perpendicular magnetization of the top CoFeB can be achieved by manipulating the exchange bias directions of the bottom IrMn/CoFeB. This serves as an entropy source for the spintronic PUF, which is characterized by high entropy, uniqueness, reconfigurability, and digital output. Furthermore, the device ensures a zero bit-error-rate under repetitive operations and robustness against external magnetic fields, and offers scalable and energy-efficient device implementations.

An efficient modeling attack for breaking the security of XOR-Arbiter PUFs by using the fully connected and long-short term memory

Physical Unclonable Functions (PUFs) have been proposed as potential hardware security primitives for various cryptographic applications in recent years. The idea of generating a unique fingerprint for each silicon chip by leveraging variations in the hardware manufacturing has created even more amazing comfortable, and affordable possibilities. On the other hand, some PUFs have shown to be vulnerable to modeling attacks. In this study, we investigate the ability of new Deep Learning (DL)-based technique as potential modeling attacks against more complicated PUF structures. To that end, we utilize the advantage of Long-Short Term Memory (LSTM) for attacking XOR-Arbiter PUFs (XOR-APUFs) for the first time. By combining the proposed LSTM with Fully Connected (FC) neural network, our FC-LSTM obtains 99% modeling accuracy on 7-XOR-APUF and 8-XOR-APUF. Furthermore, our experiments show that, despite the precise mathematical models of PUFs, our proposed modeling attacks effectively overcome the constraints imposed by prior studies in a shorter period of time and with fewer sets of training Challenge-Response Pairs (CRPs).

STT-MRAM-Based Reliable Weak PUF

In recent years, micro-nano device characteristics like ferroelectrics and resistive switching are being used to build important security primitives such as Physical Unclonable Function (PUF). The micro-nano device-based hardware security primitives, although with higher security, energy efficiency, and integration density, suffer from serious reliability issues caused by process scaling. To mitigate this issue, this paper introduces a reconfigurable weak PUF based on spin-transfer torque magnetoresistive random-access memory (STT-MRAM), which adopts the crossing switches implemented with simple demultiplexes (DEMUXs) to improve the flexibility and reliability. Moreover, two algorithms, <monospace>neighboring bit lines</monospace> and <monospace>top-<inline-formula><tex-math notation="LaTeX">$n$</tex-math><alternatives><mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>n</mml:mi></mml:math><inline-graphic xlink:href="hu-ieq1-3095657.gif" xmlns:xlink="http://www.w3.org/1999/xlink"/></alternatives></inline-formula></monospace> , are proposed to enlarge the gap between two parallel reading currents, thus further enhancing the reliability of PUF responses. Experimental results demonstrate that the proposed PUF scheme achieves good uniqueness (50.64 percent), uniformity (50.02 percent), and bit-aliasing ( <inline-formula><tex-math notation="LaTeX">$\approx$</tex-math></inline-formula> 49.80%). Particularly, the proposed method significantly improves the PUF reliability, achieving low bit error rate (BER <inline-formula><tex-math notation="LaTeX">$\leq$</tex-math></inline-formula> 2.13%) within the range of -20 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C to 90 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C.

Molecular-Scale Hardware Encryption Using Tunable Self-Assembled Nanoelectronic Networks

Nanomaterials are promising alternatives for creating hardware security primitives that are considered more robust and less susceptible to physical attacks compared to standard CMOS-based approaches. Here, nanoscale electronic circuits composed of tunable ratios of molecules and colloidal nanoparticles formed via self-assembly on silicon wafers are investigated for information and hardware security by utilizing device-level physical variations induced during fabrication. Two-terminal electronic transport measurements show variations in current through different parts of the nanoscale network, which are used to define electronic physically unclonable functions. By comparing different current paths, arrays of binary bits are generated that can be used as encryption keys. Evaluation of the keys using Hamming inter-distance values indicates that performance is improved by varying the ratio of molecules to nanoparticles in the network, which demonstrates self-assembly as a potential path toward implementing molecular-scale hardware security primitives. These nanoelectronic networks thus combine facile fabrication with a large variety of possible network building blocks, enabling their utilization for hardware security with additional degrees of freedom that is difficult to achieve using conventional systems.

Agile-AES: Implementation of configurable AES primitive with agile design approach

In the data-centric era, interconnected devices must be able to communicate efficiently and securely with their hosts even over untrusted networks. This led to the adoption of several end-to-end security protocols that employ various efficient and elegant encryption algorithms, such as Advanced Encryption Standard (AES), often implemented with hardware modules since there is usually no good solution to install security software on the device itself. State-of-the-art AES hardware implementations typically focus on optimizing a single metric, e.g. throughput or area, and are tedious to adapt to a wider set of design constraints. Applying an agile approach to hardware development is increasingly important, and this is especially critical for hardware security primitives that need to be consumed in various systems. In this work, we develop Agile-AES, an open-source, flexible, parameterizable, hardware implementation of AES, combining many best-known practices. The agile and feature-rich implementation was based on the Chisel framework, through which flexibility is instrumented to support various key length, topology, mode of operation, local memory type, S-box fabric, side-channel attack defense techniques, and interfaces. Despite covering a larger design space, our proposed implementation has 50% fewer lines of code compared to existing Verilog versions — a crucial advantage in terms of maintainability and development productivity. To evaluate the QoR out of this implementation approach, we pick representative configurations and evaluate utilization, power and throughput on both entry level and server-grade FPGAs and compare against the Verilog and HLS counterpart implementations. It shows very comparable results to the Verilog implementation and better QoR compared to the HLS-based implementation.