Hardware Security Primitives Research Articles

QCAPUF: QCA-based physically unclonable function as a hardware security primitive

Physically unclonable functions (PUFs) are increasingly used as innovative security primitives to provide the hardware authentication and identification as well as the secret key generation based on unique and random variations in identically fabricated devices. Security and low power have appeared to become two crucial necessities to modern designs. As an emerging nanoelectronic technology, a quantum-dot cellular automata (QCA) can achieve ultra-low power consumption as well as an extremely small area for implementing digital designs. However, there are various classes of permanent defects that can happen during the manufacture of QCA devices. The recent extensive research has been focused on how to eliminate errors in QCA structures resulting from fabrication variances. By a completely different vision, to turn this disadvantage into an advantage, this paper presents a novel QCA-based PUF (QCAPUF) architecture to exploit the unique physical characteristics of fabricated QCA cells in order to produce different hardware fingerprint instances. This architecture is composed of proposed logic and interconnect blocks that have critical vulnerabilities and perform unexpected logical operations. The behaviour of QCAPUF is thoroughly analysed through physical relations and simulations. Results confirm that the proposed QCAPUF has state of the art PUF characteristics in the QCA technology. This paper will serve as a basis for further research into QCA-based hardware security primitives and applications.

Design Considerations for Memristive Crossbar Physical Unclonable Functions

Hardware security has emerged as a field concerned with issues such as integrated circuit (IC) counterfeiting, cloning, piracy, and reverse engineering. Physical unclonable functions (PUF) are hardware security primitives useful for mitigating such issues by providing hardware-specific fingerprints based on intrinsic process variations within individual IC implementations. As technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies, such as memristors or RRAMs (resistive random-access memory), have become interesting options for emerging computing systems. In this article, using a comprehensive temperature dependent model of an HfO x (hafnium-oxide) memristor, based on experimental measurements, we explore the best region of operation for a memristive crossbar PUF (XbarPUF). The design considered also employs XORing and a column shuffling technique to improve reliability and resilience to machine learning attacks. We present a detailed analysis for the noise margin and discuss the scalability of the XbarPUF structure. Finally, we present results for estimates of area, power, and delay alongside security performance metrics to analyze the strengths and weaknesses of the XbarPUF. Our XbarPUF exhibits nearly ideal (near 50%) uniqueness, bit-aliasing and uniformity, good reliability of 90% and up (with 100% being ideal), a very small footprint, and low average power consumption ≈104μW.

Binary Decision Diagram Assisted Modeling of FPGA-Based Physically Unclonable Function by Genetic Programming

We present a computationally efficient technique to build concise and accurate computational models for large (60 or more inputs, 1 output) Boolean functions, only a very small fraction of whose truth table is known during model building. We use Genetic Programming with Boolean logic operators, and enhance the accuracy of the technique using Reduced Ordered Binary Decision Diagram based representations of Boolean functions, whereby we exploit their canonical forms. We demonstrate the effectiveness of the proposed technique by successfully modeling several common Boolean functions, and ultimately by accurately modeling a 63-input Physically Unclonable Function circuit design on Xilinx Field Programmable Gate Array. We achieve better accuracy (at lesser computational overhead) in predicting truth table entries not seen during model building, than a previously proposed machine learning based modeling technique for similar Physically Unclonable Function circuits using Support Vector Machines . The success of this modeling technique has important implications in determining the acceptability of Physically Unclonable Functions as useful hardware security primitives, in applications such as anti-counterfeiting of integrated circuits.

MVL‐PUFs: multiple‐valued logic physical unclonable functions

SummaryPhysical unclonable functions (PUFs) are promising hardware security primitives suitable for protecting resource‐constrained devices. In this paper, we propose to use multiple‐valued logic (MVL) for implementing hardware‐efficient PUF integrated circuits. We show that by extracting device mismatch in either current‐mode or voltage‐mode MVL comparators, the proposed PUF circuits can generate unique and reliable chip identifiers. In order to stabilize PUF responses, we utilize multiple thresholds of MVL comparators, whose outputs are selected and combined according to the sensed temperature. To reduce power and further enhance reliability, the PUF circuits are biased in the weak‐inversion region. Evaluation results show that the proposed MVL‐PUFs are unique and reliable over a wide temperature range. In addition, they significantly improve the energy efficiency of the state‐of‐the‐art PUFs. Copyright © 2016 John Wiley & Sons, Ltd.

A novel current controlled configurable RO PUF with improved security metrics

Physical Unclonable Functions (PUFs) are promising hardware security primitives which produce unique signatures. Out of several delay based PUF circuits, Configurable Ring Oscillator (CRO) PUF has got higher uniqueness and it is resilient against modelling attacks. In this paper, we present a novel Current controlled CRO (C-CRO) PUF in which inverters of RO uses different logic styles: static CMOS and Feedthrough logic (FTL). Use of different logic styles facilitates improvement of security metrics of PUF. The analysis of security metrics of the proposed architecture is carried out in 90nm CMOS technology shows, using FTL logic leads to better security metrics. Proposed C-CRO PUF is also both power and area efficient. Further, in order to measure the vulnerability of proposed PUF, machine learning attack is carried out and the result shows FTL RO based C-CRO PUF is highly resilient to machine learning attack because of its non-linearity property.

Spintronics and Security: Prospects, Vulnerabilities, Attack Models, and Preventions

The experimental demonstration of current-driven spin-transfer torque (STT) for switching magnets and push domain walls (DWs) in magnetic nanowires have opened up new avenues for spintronic computations. These devices have shown great promise for logic and memory applications due to superior energy efficiency and nonvolatility. It has been noted that the nonlinear dynamics of DWs in the physical magnetic system is an untapped source of entropy that can be leveraged for hardware security. The inherent noise, spatial, and temporal randomness in the magnetic system can be employed in conjunction with microscopic and macroscopic properties to realize novel hardware security primitives. Due to simplicity of integration, the spintronic circuits can be an add-on to the silicon substrate to complement the existing CMOS-based security and trust infrastructures. This paper investigates the prospects of spintronics in hardware security by exploring the security-specific properties and novel security primitives realized using spintronic building blocks. As spintronic elements enter the mainstream computing platforms, they are exposed to emerging attacks that were infeasible before. This paper covers the security vulnerabilities, security and privacy attack models, and possible countermeasures to enable safe computing environment using spintronics.

Ultra‐energy‐efficient temperature‐stable physical unclonable function in 65 nm CMOS

Physical unclonable functions (PUFs) are promising hardware security primitives suitable for resource-constrained devices requiring lightweight cryptographic methods. This Letter proposes an ultra-low-power and reliable PUF based on a customised dynamic two-stage comparator operating in the sub-threshold region. The proposed PUF is implemented in a standard 65 nm CMOS technology and validated through Monte-Carlo simulations. Evaluation results show a worst-case reliability of 98.3% over the commercial temperature range of 0°C to 85°C and 10% fluctuations in supply voltage. In addition, the 128-bit PUF array consumes only 1.33 μW at 1 Mb/s, which corresponds to 10.3 fJ/bit, being the most energy-efficient design to date.

A novel memristor based physically unclonable function

Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as Physically Unclonable Functions (PUFs). In this paper, we first introduce a novel hybrid memristor–CMOS XOR/XNOR logic circuit that offers several advantages such as combinational circuit behavior, simpler operation and lower hardware overhead than existing solutions. Then, we use this XOR circuit as a component to design a hybrid memristor–CMOS PUF circuit and demonstrate its effectiveness through extensive simulations of environmental and process variation effects. The proposed PUF circuit has substantially lesser hardware overhead than previously proposed memristor-based PUF circuits, while being resistant against machine learning based modelling attacks. The proposed PUF can be conveniently used in many security applications and protocols based on hardware-intrinsic security.

Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications

Information security has emerged as an important system and application metric. Classical security solutions use algorithmic mechanisms that address a small subset of emerging security requirements, often at high-energy and performance overhead. Further, emerging side-channel and physical attacks can compromise classical security solutions. Hardware security solutions overcome many of these limitations with less energy and performance overhead. Nanoelectronics-based hardware security preserves these advantages while enabling conceptually new security primitives and applications. This tutorial paper shows how one can develop hardware security primitives by exploiting the unique characteristics such as complex device and system models, bidirectional operation, and nonvolatility of emerging nanoelectronic devices. This paper then explains the security capabilities of several emerging nanoelectronic devices: memristors, resistive random-access memory, contact-resistive random-access memory, phase change memories, spin torque-transfer random-access memory, orthogonal spin transfer random access memory, graphene, carbon nanotubes, silicon nanowire field-effect transistors, and nanoelectronic mechanical switches. Further, the paper describes hardware security primitives for authentication, key generation, data encryption, device identification, digital forensics, tamper detection, and thwarting reverse engineering. Finally, the paper summarizes the outstanding challenges in using emerging nanoelectronic devices for security.

A Novel Memristor-Based Hardware Security Primitive

Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as Physically Unclonable Functions (PUFs). In this article, we propose a novel hybrid memristor-CMOS PUF circuit and demonstrate its suitability through extensive simulations of environmental and process variation effects. The proposed PUF circuit has substantially less hardware overhead than previously proposed memristor-based PUF circuits while being inherently resistant to machine learning-based modeling attacks because of challenge-dependent delays of the memristor stages. The proposed PUF can be conveniently used in many security applications and protocols based on hardware-intrinsic security.

Fault Injection Modeling Attacks on 65 nm Arbiter and RO Sum PUFs via Environmental Changes

Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. So-called strong PUFs provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. To prevent cloning, modeling of the challenge-response pair (CRP) behavior should be infeasible. Machine learning (ML) algorithms are a well-known threat. Recently, repeatability imperfections of PUF responses have been identified as another threat. CMOS device noise renders a significant fraction of the CRPs unstable, hereby providing a side channel for modeling attacks. In previous work, 65 nm arbiter PUFs have been modeled as such with accuracies exceeding 97%. However, more PUF evaluations were required than for state-of-the-art ML approaches. In this work, we accelerate repeatability attacks by increasing the fraction of unstable CRPs. Response evaluation faults are triggered via environmental changes hereby. The attack speed, which is proportional to the fraction of unstable CRPs, increases with a factor 2.4 for both arbiter and ring oscillator (RO) sum PUFs. Data originates from a 65 nm silicon chip and hence not from simulations.