Hardware Security Applications Research Articles

CMOS Design of Chaotic Systems Using Biquadratic OTA-C Filters

CMOS Design of Chaotic Systems Using Biquadratic OTA-C Filters

CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency

Conventional security systems incur considerable computational resources, which become a significant hindrance for resource constraints internet of things (IoT) and wireless sensor network applications. Downsizing the existing security processes necessitates demand for lightweight cryptography for a secure system. The Physically Unclonable Function (PUF) extracts the uncontrollable randomness in the physical variation of integrated circuits (ICs). It is now proven to be promising security primitive for many hardware security applications, including authentication and anti-counterfeiting. The Arbiter PUF (APUF) provides a viable solution with minimal design overhead. This work proposes a new PUF variant, the Configurable Circular Arbiter PUF (CAPUF), for hardware security applications. In the CAPUF, the position of switches in an APUF are selectively altered to amalgam non-linearity and Strict Avalanche Criterion (SAC) properties, which enhances its security at low design overhead. An important feature of the CAPUF is that it is configurable, and this flexibility gives it a considerable advantage over many existing PUF variants. Simulation results and statistical analyses establish that the CAPUF outperforms the existing APUF variants through a combination of cost-effective architecture, SAC property, adequate modeling robustness, and the trade-off between security and hardware overhead.

Performance Improvement of AlN-Based RRAMs Using Ag Layer for Hardware Security Applications

In this study, the 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 8 aluminum nitride (AlN)-based complementary resistive switching (CRS) resistive random access memory (RRAM) crossbar array has been fabricated and was applied for a hardware security. Since CRS has a nonlinear <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> characteristic curve, it can effectively alleviate the actual impact caused by sneak current. A 5 nm silver electrode auxiliary layer is inserted between the electrode and the resistance switching layer to form a titanium nitride (TiN)/Ag/AlN/Pt/AlN/Ag/TiN seven-layer structure. The ultimate result here shows that the forming voltage of the device has eventually dropped from 5.5 to 2.8 V and the nonlinearity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> has gradually increased from 10.5 to 255 so that the number of arrays can ideally be expanded to more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{426}$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ \text{426}$</tex-math> </inline-formula> bits. In addition, because a small amount of silver ions formed a relatively discontinuous conductive filament (CF), the device with an auxiliary layer of 5 nm Ag has a wider high-resistance state distribution. Therefore, it is suitable as the source of physical unclonable function (PUF) key generation for hardware security. After being compared by the read circuit comparator, we have generated a RRAM PUF key with reliability 99.1%, uniformity 49.5%, and randomness 48.9%. To authors’ knowledge, it is first report about nitride-based CRS RRAM as PUF for hardware security applications.

A RRAM-Based True Random Number Generator with 2T1R Architecture for Hardware Security Applications.

Resistance random access memory (RRAM) based true random number generator (TRNG) has great potential to be applied to hardware security owing to its intrinsic switching variability. Especially the high resistance state (HRS) variation is usually taken as the entropy source of RRAM-based TRNG. However, the small HRS variation of RRAM may be introduced owing to fabrication process fluctuations, which may lead to error bits and be vulnerable to noise interference. In this work, we propose an RRAM-based TRNG with a 2T1R architecture scheme, which can effectively distinguish the resistance values of HRS with an accuracy of 1.5 kΩ. As a result, the error bits can be corrected to a certain extent while the noise is suppressed. Finally, a 2T1R RRAM-based TRNG macro is simulated and verified using the 28 nm CMOS process, which suggests its potential for hardware security applications.

A true random number generator based on double threshold-switching memristors for image encryption

True random number generator (TRNG) that cannot be arbitrary attacked with predictable software algorithm is a promising data security solution. Memristors, possessing specific intrinsic stochasticity, are just appropriate to be the random sources for encryption applications. In this work, a TRNG system based on the stochastic duration time of double threshold-switching (TS) memristors is proposed. The reliable stochasticity of this system is mainly attributed to the gradual dissolution of Ag conductive channels and the synergistic effect of these two TS memristors. A digital circuit system based on the micro-controller unit is designed to produce stable random “0” and “1” bitstreams. The random data key generated by this double TS memristor TRNG passed the National Institute of Standards and Technology randomness tests without post-processing procedure. Taking advantage of the true random data key, the binary image can be encrypted and decrypted by executing the XNOR logic operation. In addition, the Gaussian noise effect on the decryption stability of image information secure communication is also analyzed. Although 90% Gaussian noise was applied to the original image, the pristine binary image still can be roughly recognized. This work demonstrates that the double TS memristors-based TRNG system has great potential for hardware security applications.

Security Attack on Remote Sensing Equipment: PoIs Recognition Based on HW with Bi-LSTM Attention

&lt;p&gt;Deep learning is an influencer in hardware security applications, which grows up to be an essential tool in hardware security, threats the confidentiality, integrity, and availability of remote sensing equipment. Comparing to traditional physical attack, not only it can greatly reduce the workload of manual selection of POIs (Points of Interests) in security attack and Trojan backdoor, but also replenishes the toolbox for attacking. On account of minute changes between network structure model and hyperparameters constantly affecting the training and attacking effect, literally, deep learning serves as a tool but not key role in hardware security attack, which means it cannot completely replace template attack and other traditional energy attack methods. In this study, we present a method using Bi-LSTM Attention mechanism to focus on the POIs related to Hamming Weight at the last round s-box output. Firstly, it can increase attacking effect and decrease guessing entropy, where attacking FPGA data demonstrates the efficiency of attacking. Secondly, it is different from the traditional template attack and deep learning attack without preprocessing subjecting to raw traces but provides attentional POIs which is the same with artificial selection. Finally, it provides a solution for attacking encrypting equipment running in parallel.&lt;/p&gt; &lt;p&gt;&amp;nbsp;&lt;/p&gt;

Self-Parameterized Chaotic Map for Low-Cost Robust Chaos

This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterization scheme uses only one existing chaotic map, referred to as the seed map, and a simple transformation block. The effective control parameter of the seed map is treated as an intermediate variable derived from the input and control parameter of the self-parameterized map, under some constraints, to achieve the desired functionality. The widening of the chaotic region after adding self-parameterization is first demonstrated on three ideal map functions: Logistic; Tent; and Sine. A digitized version of the scheme was developed and realized in a field-programmable gate array (FPGA) implementation. An analog version of the proposed scheme was developed with very low transistor-count analog topologies for hardware-constrained integrated circuit (IC) implementation. The chaotic performance of both digital and analog implementations was evaluated with bifurcation plots and four established chaotic entropy metrics: the Lyapunov Exponent; the Correlation Coefficient; the Correlation Dimension; and Approximate Entropy. An application of the proposed scheme was demonstrated in a random number generator design, and the statistical randomness of the generated sequence was verified with the NIST test.

Stochastic current response in diffusive memristor for security applications

Among various emerging information encryption technologies, diffusive memristors play an important role in such hardware security applications due to their volatile characteristics and intrinsic stochasticity. Here, we propose a true random number generator (TRNG) based on the random distributed current response of Ag/phenylalanine dipeptide microrod (FF MR)/Ag diffusive memristor which passes all National Institute of Standards and Technology tests. The key innovation of this method is that the degree of randomness of the output bits can be controlled by adjusting the reference voltage (Vref) where ideal 50% average uniformity of the generated random bits can be achieved. Furthermore, we used the true random number generated by TRNG as the cryptographic key to constructing a data encryption system and experimentally demonstrated the fully functional implementation of the encryption process. Through scanning electron microscopy and line scan energy dispersion spectrum analysis of the device, the confinement effect of FF MR on the Ag conductive filaments was verified, ensuring the reliable operation of TRNG and the entire encryption system.

Stabilizing Techniques for Secure On-chip Key Generation Based on RO-PUF

Based on intrinsic physical characteristics of devices, Physically Unclonable Functions (PUFs) provide the high reliability while maintaining the sufficient uniqueness. However, in the practical implementation based on PUFs, the extracted bit-string normally exhibits the unavoidable small fluctuation. Hence, PUFs can be used for the application of chip identification, but not suitable for the application that strictly requires an exact generated number. In this work, we propose several techniques to stabilize the generated value based on the existing Ring Oscillator (RO)-PUF circuit so that the stable unique number can be directly used for high-profile hardware security applications. In detail, we design a specialized on-chip key generation circuit that repeatedly samples the RO frequency values for statistical analysis and dynamically phases out the unstable bits, resulting in a unique and stable output bit-string. The experiments are conducted for the actual data measured from Xilinx Artix-7 FPGA devices. The generated key is proven to be relatively stable and can be readily used for the emerging security applications.

EigenCircuit: Divergent Synthetic Benchmark Generation for Hardware Security Using PCA and Linear Programming

Benchmarks are the standards by which technologies can be evaluated and fairly compared. In the field of digital circuits, benchmarks were critical for the development of CAD and FPGA tools decades ago. Hardware security is an emerging field of research where new techniques of security and vulnerability of hardware designs are being proposed in higher volume each year. Using decade-old VLSI/CAD-oriented benchmarks for analyzing the techniques has many issues as these benchmarks were not developed for security research. Additionally, the rise of statistical analysis or machine learning (ML) to model vulnerabilities and solve security issues demands a very large set of samples for training purposes. Since the number of available VLSI/CAD benchmarks is limited, such volume can only be obtained through synthetic benchmark generation tools. To accommodate both of these needs, the first hardware security-oriented synthetic circuit benchmark generation framework is developed in this article. With the use of principal component analysis (PCA) and linear optimization tool, the benchmarks generated by the proposed framework are “divergent,” that is having maximum variation in structures from each other. By accommodating user inputs for desired features, the framework offers customization for generating richer and more challenging benchmarks for data-driven hardware security. With thorough experimentation, we demonstrate our framework’s scalability, the structural and functional variations in the generated benchmarks, and the advantage of structurally variant synthetic benchmarks in hardware security applications.

Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications

Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications

A process variation resilient spintronic true random number generator for highly reliable hardware security applications

True random number generators (TRNGs) are critical in cryptography and security systems. This paper presents a reliable TRNG relying on the stochastic switching of the spin-transfer torque magnetic tunnel junction (STT-MTJ) in the sub-critical current regime. Using an XOR-based structure in our proposed design eliminates the need for succeeding post-processing units while ensuring a reliable generation of random numbers, even in the presence of major variations. Moreover, utilizing gate-all-around (GAA) carbon nanotube field-effect transistors (CNTFETs) and the efficient structure of the proposed design leads to a low-power and high-performance operation. Comprehensive transient simulations verify the functionality of the proposed TRNG in fabrication process corners. According to the simulation results, our proposed TRNG has, on average, 53% and 63% lower power consumption and energy per bit, respectively, and a 70% smaller area compared to its counterparts. A statistical randomness test provided by the U.S. National Institute of Standards and Technology (NIST) validates the randomness quality of the generated random bitstreams.

A ±0.5dB, 6nW RSSI Circuit with RF Power-to-Digital Conversion Technique for Ultra-low Power IoT Radio Applications.

This paper presents a new technique of radio frequency (RF) signal strength detection with a received signal strength indicator (RSSI) circuit which can be deployed in an internet-of-things (IoT) network. The proposed RSSI circuit is based on a direct conversion of RF to digital code indicating the signal strength. The direct conversion is achieved by the repeated switching of a rectifier's output voltage using an ultra-low power comparator. A 5-bit programmable feedback circuit is used to correct detection inaccuracies. The RSSI circuit is implemented in a 65-nm CMOS process and consumes 6nW power. It has a linear dynamic range of 26dB and exhibits an error of ±0.5dB with a wide bandwidth of 750MHz. A detailed analysis of the RSSI circuit is presented and verified with simulation and measurement results. The high detection accuracy with ultra-low power consumption of our RSSI circuit is favourable for IoT applications including localization, beamforming, hardware security and other low-power applications.

Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%–1.5% Bit Instability at 0.4–1.8 V Operation in 180 nm

This article introduces a novel class of static and monostable CMOS physically unclonable functions (PUFs) for hardware security applications. The PUF bitcell is based on a sub-threshold four-transistor (4T) voltage divider as the core block, along with an inverter as the output stage. The 4T voltage divider consists of two series-connected and nominally identical PMOS-only two-transistor (2T) circuits. This allows inherently random bit generation assisted by mismatch while also ensuring inherent robustness against environmental variations. A 180-nm test chip was characterized to validate our solution. Measurements of the 4T bitcell core prove its capability to generate random voltages with high dispersion (i.e., close to either ground or supply voltage levels) and high stability across a wide range of environmental conditions. The statistical PUF performance was evaluated on an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times32$ </tex-math></inline-formula> bitcell array without applying any post-silicon stability-enhancement technique. Raw measurements reveal a bit instability of only ~0.6% at golden key (GK) conditions (1.8 V and 25 °C), which increases up to 1.5% at 0.4 V and room temperature. When compared to prior art, our solution shows competitive performance in terms of stability, uniqueness (mean normalized inter-PUF Hamming distance (HD) of 0.493), and reproducibility (mean normalized intra-PUF HD of 0.0016), at the cost of more area-hungry design (~7200-F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> bitcell area).

Physically Unclonable Function Using GSHE Driven SOT Assisted p-MTJ for Next Generation Hardware Security Applications

The increasing threat of security attacks on hardware security applications has driven research towards exploring beyond CMOS devices as an alternative. Spintronic devices offer advantages like low power, non-volatility, inherent spatial and temporal randomness, simplicity of integration with a silicon substrate, etc., making them a potential candidate for next-generation hardware security systems. In this work, we explore the Giant Spin Hall effect (GSHE) driven spin-orbit torque magnetic tunnel junction (MTJ) implementing physically unclonable function (PUFs). The effect of process variation is considered in key MTJ parameters like TMR ratio, free and oxide layer thickness following Gaussian distribution, and Monte-Carlo simulations to determine the effect of the process variations. A unique challenge-response (C-R) pair is obtained utilizing the inherent variations in magnetization dynamics of the free layer due to process variations.

RRAM Random Number Generator Based on Train of Pulses

In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications.

Low-Power True Random Number Generator Based on Randomly Distributed Carbon Nanotube Networks

Although the intrinsic variability in nanoelectronic devices has been a major obstacle and has prevented mass production, this natural stochasticity can be an asset in hardware security applications. Herein, we demonstrate a true random number generator (TRNG) based on stochastic carrier trapping/detrapping processes in randomly distributed carbon nanotube networks. The bitstreams collected from the TRNG passed all the National Institute of Standards and Technology randomness tests without post-processing. The random bit generated in this study is sufficient for encryption applications, particularly those related to the Internet of Things and edge computing, which require significantly lower power consumption.

Hardware Security Exploiting Post-CMOS Devices: Fundamental Device Characteristics, State-of-the-Art Countermeasures, Challenges and Roadmap

Emerging nanoelectronic semiconductor devices have been quite promising in enhancing hardware-oriented security and trust. However, implementing hardware security primitives and methodologies requires large area overhead and power consumption. Furthermore, emerging new attack models and vulnerabilities are regularly evolving and cannot be adequately addressed by current CMOS technology. This paper for the first time presents a comprehensive review of numerous post-CMOS technologies based hardware security primitives and methodologies, particularly true random number generators, physically unclonable functions, sidechannel analysis countermeasures, and hardware obfuscation techniques. Various beyond-CMOS device technologies including tunneling FET (TFET), hybrid phase transition FET (HyperFET), carbon nanotube FET (CNTFET), silicon nanowire FET (SiNWFET), symmetrical tunneling FET (SymFET), phase-change memory (PCM), spin-transfer torque magnetic tunnel junction (STT-MTJ), resistive random access memory (RRAM) have been considered in this study. First, the basic principle of operation and unusual characteristics of nanoelectronic devices used for hardware security applications have been extensively discussed. Later, CMOS technology challenges and benefits of emerging nanotechnologies for the design of hardware security primitives and methodologies have been reported. Finally, different analyses have been presented to demonstrate the promising performance of post-CMOS devices over the current CMOS technology in different countermeasures. Additionally, challenges, future directions, and plans have been presented to achieve more research outcomes in this field.

Design and synthesis of low temperature printed metal oxide memristors

Printed combustion-based aluminium oxide (AlOx) resistive switching devices produced at low temperature show a high reproducibility (95%) and multilevel cell operation with potential for hardware security applications.

Two-dimensional transistors with reconfigurable polarities for secure circuits

Security is a critical aspect in modern circuit design, but research into hardware security at the device level is rare as it requires modification of existing technology nodes. With the increasing challenges facing the semiconductor industry, interest in out-of-the-box security solutions has grown, even if this implies introducing novel materials such as two-dimensional layered semiconductors. Here, we show that high-performance, low-voltage, two-dimensional black phosphorus field-effect transistors (FETs) that have reconfigurable polarities are suitable for hardware security applications. The transistors can be dynamically switched between p-FET and n-FET operation through electrostatic gating and can achieve on–off ratios of 105 and subthreshold swings of 72 mV dec−1 at room temperature. Using the transistors, we create inverters that exhibit gains of 33.3 and are fully functional at a supply voltage of 0.2 V. We also create a security primitive circuit with polymorphic NAND/NOR obfuscation functionality with sub-1-V operation voltages, and the robustness of the polymorphic gate against power supply variations is tested using Monte Carlo simulations. Transistors that use two-dimensional black phosphorus as the active material can dynamically switch between p-type and n-type operation, and can be used to create security primitive circuits with polymorphic NAND/NOR obfuscation functionality.