Hardware Platform Research Articles

Research on a Real-Time Monitoring System for Campus Woodland Fires via Deep Learning

To solve the problems of low recognition accuracy and large amounts of computation required in forest fire detection algorithms, this paper, aiming to make improvements in these two aspects, proposes a G-YOLOv5n-CB forest fire detection algorithm based on the YOLOv5 algorithm and develops a set of real-time fire monitoring systems applicable to campus forest land with the aid of deep learning technology. The system employs an unmanned vehicle to navigate automatically and collect image information through a camera and deploys its algorithm on the unmanned vehicle’s Jetson Nano hardware platform. The results demonstrate that the proposed YOLOv5n-CB algorithm increased the mAP value index by 1.4% compared with the original algorithm on the self-made forest fire dataset. The improved G-YOLOv5n-CB model was deployed on the Jetson Nano platform for testing, and its detection speed reached 15 FPS. It can accurately detect and display real-time forest fires on campus and has, thus, a high application value.

Performance Evaluation of Spintronic-Based Spiking Neural Networks using Parallel Discrete-Event Simulation

Spintronics devices that use the spin of electrons as the information state variable have the potential to emulate neuro-synaptic dynamics and can be realized within a compact form-factor, while operating at ultra-low energy-delay point. In this paper, we benchmark the performance of a spintronics hardware platform designed for handling neuromorphic tasks. To explore the benefits of spintronics-based hardware on realistic neuromorphic workloads, we developed a Parallel Discrete-Event Simulation model called Doryta, which is further integrated with a materials-to-systems benchmarking framework. The benchmarking framework allows us to obtain quantitative metrics on the throughput and energy of spintronics-based neuromorphic computing and compare these against standard CMOS-based approaches. Although spintronics hardware offers significant energy and latency advantages, we find that for larger neuromorphic circuits, the performance is limited by the interconnection networks rather than the spintronics-based neurons and synapses. This limitation can be overcome by architectural changes to the network. Through Doryta we are also able to show the power of neuromorphic computing by simulating Conway’s Game of Life (GoL), thus showing that it is Turing complete. We show that Doryta obtains over 300 × speedup using 1,024 CPU cores when tested on a convolutional, sparse, neural architecture. When scaled-up 64 times, to a 200 million neuron model, the simulation ran in 3:42 minutes for a total of 2000 virtual clock steps. The conservative approach of execution was found to be faster in most cases than the optimistic approach, even when a tie-breaking mechanism to guarantee deterministic execution, was deactivated.

FortiFix : A Fault Attack Aware Compiler Framework for Crypto Implementations

Fault attacks are one of the most powerful forms of cryptanalytic attack on embedded systems, that can corrupt cipher’s operations leading to a breach of confidentiality and integrity. A single precisely injected fault during the execution of a cipher can be exploited to retrieve the secret key in a few milliseconds. Naïve countermeasures introduced into implementation can lead to huge overheads, making them unusable in resource-constraint environments. On the other hand, optimized countermeasures requires significant knowledge, not just about the attack, but also on the (a) the cryptographic properties of the cipher, (b) the program structure, and (c) the underlying hardware architecture. This makes the protection against fault attacks tedious and error-prone. In this paper, we introduce the first automated compiler framework named FortiFix that can detect and patch fault exploitable regions in a block cipher implementation. The framework has two phases. The pre-compilation phase identifies regions in the source code of a block cipher that are vulnerable to fault attacks. The second phase is incorporated as transformation passes in the LLVM compiler to find exploitable instructions, quantify the impact of a fault on these instructions, and finally insert appropriate countermeasures based on user defined security requirements. As a proof of concept, we have evaluated two block cipher implementations AES-128 and CLEFIA-128 on three different hardware platforms such as MSP430 (16-bit), ARM (32-bit) and RISCV (32-bit).

Fundamental scaling relationships in additive manufacturing and their implications for future manufacturing and bio-manufacturing systems

The field of additive manufacturing (AM) has advanced considerably over recent decades through the development of novel methods, materials, and systems. As the field approaches a level of maturity, it is relevant to investigate emerging trends which may shed light on the fundamental scaling limits of AM systems to pattern matter from digital data. Here we propose a simplified mathematical model which describes process dynamics of many AM hardware platforms. In this model, the influence of several key parameters on total manufacturing time is examined and compared with performance results obtained from real-world AM systems. The model describes the dependence of volumetric build rate of many types of AM systemson their minimal feature size, and total build volume. Furthermore, we put forward a new framework for classifying manufacturing processes as “top-down” or “bottom-up,” which differs from the conventional usage of such terms. Finally, we offer a geometric model for one type of “bottom-up” manufacturing, and the limitations of such systems are contrasted with the limiting factors for “top-down” manufacturing systems.

An improved resource allocation method for mapping service function chains based on A3C

AbstractNetwork function virtualization (NFV) technology deploys network functions as software functions on a generalised hardware platform and provides customised network services in the form of service function chain (SFC), which improves the flexibility and scalability of network services and reduces network service costs. However, irrational resource allocation during service function chain mapping will cause problems such as low resource utilisation, long service request processing time and low mapping rate. To address the unreasonable problem of service mapping resource allocation, an improved service function chain mapping resource allocation method (SA3C) based on the Asynchronous advantageous action evaluation algorithm (A3C) is proposed. This study proposes an SFC mapping model and a mathematical model for joint allocation, which modeled the minimization of processing time as a Markov process. The main network was trained and multiple sub‐networks were generated in parallel using the ternary and deep reinforcement learning algorithm A3C, with the goal of identifying the optimal resource allocation strategy. The experimental simulation results show that compared with the Actor‐Critic (AC) and Policy Gradient (PG) methods, SA3C algorithm can improve the resource utilisation by 9.85%, reduce the total processing time by 10.72%, and improve the mapping rate by 6.72%, by reasonably allocating node computational resources and link bandwidth communication resources.

An optical-based measurement method for center distance between two double-hole components

PurposeIn the context of fixed-wing aircraft wing assembly, there is a need for a rapid and precise measurement technique to determine the center distance between two double-hole components. This paper aims to propose an optical-based spatial point distance measurement technique using the spatial triangulation method. The purpose of this paper is to design a specialized measurement system, specifically a spherically mounted retroreflector nest (SMR nest), equipped with two laser displacement sensors and a rotary encoder as the core to achieve accurate distance measurements between the double holes.Design/methodology/approachTo develop an efficient and accurate measurement system, the paper uses a combination of laser displacement sensors and a rotary encoder within the SMR nest. The system is designed, implemented and tested to meet the requirements of precise distance measurement. Software and hardware components have been developed and integrated for validation.FindingsThe optical-based distance measurement system achieves high precision at 0.04 mm and repeatability at 0.02 mm within a range of 412.084 mm to 1,590.591 mm. These results validate its suitability for efficient assembly processes, eliminating repetitive errors in aircraft wing assembly.Originality/valueThis paper proposes an optical-based spatial point distance measurement technique, as well as a unique design of a SMR nest and the introduction of two novel calibration techniques, all of which are validated by the developed software and hardware platform.

Synchronized measurement method for urban distribution networks based on proportional-integral control

In the context of the rising prevalence of renewable energy, the need for precise and synchronized measurements in urban distribution networks has become increasingly critical. Conventional synchronization techniques, which predominantly depend on Global Navigation Satellite System (GNSS) timing signals, are often plagued by significant sampling time errors. Addressing this challenge, this study introduces an innovative automatic synchronization measurement method employing proportional-integral (PI) control. This method is composed of three integral components: the monitoring of local clock phases via pulses per second (PPS) signals, modulation of the clock phase through a PI controller, and the estimation of grid phasors from the synchronized sampled data. The test results of this method on a hardware platform demonstrate its capability to significantly reduce the sampling error from 2 × 10−3 V to an impressive 1 × 10−5 V, while also meeting the requirements of the synchronized phasor measurement standards outlined in C37.118.1. These advancements underscore the significant potential of PI-controlled simultaneous sampling in enhancing the operational efficiency and reliability of urban distribution networks, particularly in environments with a high integration of renewable energy sources.

Training self-learning circuits for power-efficient solutions

As the size and ubiquity of artificial intelligence and computational machine learning models grow, the energy required to train and use them is rapidly becoming economically and environmentally unsustainable. Recent laboratory prototypes of self-learning electronic circuits, such as “physical learning machines,” open the door to analog hardware that directly employs physics to learn desired functions from examples at a low energy cost. In this work, we show that this hardware platform allows for an even further reduction in energy consumption by using good initial conditions and a new learning algorithm. Using analytical calculations, simulations, and experiments, we show that a trade-off emerges when learning dynamics attempt to minimize both the error and the power consumption of the solution—greater power reductions can be achieved at the cost of decreasing solution accuracy. Finally, we demonstrate a practical procedure to weigh the relative importance of error and power minimization, improving the power efficiency given a specific tolerance to error.

Measurement-Free Fault-Tolerant Quantum Error Correction in Near-Term Devices

Logical qubits can be protected from decoherence by performing quantum error-correction (QEC) cycles repeatedly. Algorithms for fault-tolerant QEC must be compiled to the specific hardware platform under consideration in order to practically realize a quantum memory that operates for in principle arbitrary long times. All circuit components must be assumed as noisy unless specific assumptions about the form of the noise are made. Modern QEC schemes are challenging to implement experimentally in physical architectures where in-sequence measurements and feed forward of classical information cannot be reliably executed fast enough or even at all. Here we provide a novel scheme to perform QEC cycles without the need of measuring qubits that is fully fault-tolerant with respect to all components used in the circuit. Our scheme can be used for any low-distance CSS code since its only requirement towards the underlying code is a transversal gate. Similarly to Steane-type EC, we coherently copy errors to a logical auxiliary qubit but then apply a coherent feedback operation from the auxiliary system to the logical data qubit. The logical auxiliary qubit is prepared fault tolerantly without measurements, too. We benchmark logical failure rates of the scheme in comparison to a flag-qubit-based EC cycle. We map out a parameter region where our scheme is feasible and estimate physical error rates necessary to achieve the break-even point of beneficial QEC with our scheme. We outline how our scheme could be implemented in ion traps and with neutral atoms in a tweezer array. For recently demonstrated capabilities of atom shuttling and native multiatom Rydberg gates, we achieve moderate circuit depths and beneficial performance of our scheme while not breaking fault tolerance. These results thereby enable practical fault-tolerant QEC in hardware architectures that do not support midcircuit measurements. Published by the American Physical Society 2024

Neural network methods for radiation detectors and imaging

Recent advances in image data proccesing through deep learning allow for new optimization and performance-enhancement schemes for radiation detectors and imaging hardware. This enables radiation experiments, which includes photon sciences in synchrotron and X-ray free electron lasers as a subclass, through data-endowed artificial intelligence. We give an overview of data generation at photon sources, deep learning-based methods for image processing tasks, and hardware solutions for deep learning acceleration. Most existing deep learning approaches are trained offline, typically using large amounts of computational resources. However, once trained, DNNs can achieve fast inference speeds and can be deployed to edge devices. A new trend is edge computing with less energy consumption (hundreds of watts or less) and real-time analysis potential. While popularly used for edge computing, electronic-based hardware accelerators ranging from general purpose processors such as central processing units (CPUs) to application-specific integrated circuits (ASICs) are constantly reaching performance limits in latency, energy consumption, and other physical constraints. These limits give rise to next-generation analog neuromorhpic hardware platforms, such as optical neural networks (ONNs), for high parallel, low latency, and low energy computing to boost deep learning acceleration (LA-UR-23-32395).

Comprehensive analysis of energy efficiency and performance of ARM and RISC-V SoCs

Over the past few years, ARM has been the dominant player in embedded systems and System-on-Chips (SoCs). With the emergence of hardware platforms based on the RISC-V architecture, a practical comparison focusing on their energy efficiency and performance is needed. In this study, our goal is to comprehensively evaluate the energy efficiency and performance of ARM and RISC-V SoCs in three different systems. We will conduct benchmark tests to measure power consumption and overall system performance. The results of our study are valuable to developers and researchers looking for the most appropriate hardware platform for energy-efficient computing applications. Our observations suggest that RISC-V Instruction Set Architecture (ISA) implementations may demonstrate lower average power consumption than ARM, but this does not automatically imply a superior performance per watt ratio for RISC-V. The primary focus of the study is to evaluate and compare these ISA implementations, aiming to identify potential areas for enhancing their energy efficiency. Furthermore, to ensure the practical applicability of our findings, we will use the Computational Fluid Dynamics software OpenFOAM. This step serves to validate the relevance of our results in real-world scenarios. It allows us to fine-tune execution parameters based on the insights gained from our initial study. By doing so, we aim not only to provide meaningful conclusions but also to investigate the transferability of our results to practical applications. Our analysis will also scrutinize the capabilities of these SoCs when handling nonsynthetic software workloads, thereby broadening the scope of our evaluation.

A Neuromorphic Vision and Feedback Sensor Fusion Based on Spiking Neural Networks for Real‐Time Robot Adaption

For some years now, the locomotion mechanisms used by vertebrate animals have been a major inspiration for the improvement of robotic systems. These mechanisms range from adapting their movements to move through the environment to the ability to chase prey, all thanks to senses such as sight, hearing, and touch. Neuromorphic engineering is inspired by brain problem‐solving techniques with the goal of implementing models that take advantage of the characteristics of biological neural systems. While this is a well‐defined and explored area in this field, there is no previous work that fuses analog and neuromorphic sensors to control and modify robotic behavior in real time. Herein, a system is presented based on spiking neural networks implemented on the SpiNNaker hardware platform that receives information from both analog (force‐sensing resistor) and digital (neuromorphic retina) sensors and is able to adapt the speed and orientation of a hexapod robot depending on the stability of the terrain where it is located and the position of the target. These sensors are used to modify the behavior of different spiking central pattern generators, which in turn will adapt the speed and orientation of the robotic platform, all in real time. In particular, experiments show that the network is capable of correctly adapting to the stimuli received from the sensors, modifying the speed and heading of the robotic platform.

Construction and Practice of the Undergraduate Teaching System of New Media Technology

With the rapid development of new technologies such as mobile internet, big data, and artificial intelligence, new media has become an important force in the communication field. It is imperative to build a complete undergraduate teaching system of new media technology and cultivate versatile talents to meet the needs of industry development. Taking the majors of new media technology and new media (big data news communication direction) at Qilu University of Technology as an example, this study analyzes the issues in talent training objectives, curriculum setting, teaching content and teaching methods through literature review, questionnaires and interviews. It is proposed to build a modularized and flexible curriculum system oriented to ability training, increase cutting-edge new media technology courses, and strengthen the cultivation of software and hardware platform application abilities. In terms of teaching methods, project-driven teaching methods are implemented, distinctive project training courses are set up to promote knowledge application and comprehensive ability training. The research shows that building an open, flexible undergraduate teaching system of new media technology that emphasizes cross integration will help improve the quality of talent cultivation and enable talents to better meet the needs of new media industry development. This study provides theoretical support and practical approaches for promoting the teaching reform of the new media technology major.

Qibolab: an open-source hybrid quantum operating system

We present Qibolab, an open-source software library for quantum hardware control integrated with the Qibo quantum computing middleware framework. Qibolab provides the software layer required to automatically execute circuit-based algorithms on custom self-hosted quantum hardware platforms. We introduce a set of objects designed to provide programmatic access to quantum control through pulses-oriented drivers for instruments, transpilers and optimization algorithms. Qibolab enables experimentalists and developers to delegate all complex aspects of hardware implementation to the library so they can standardize the deployment of quantum computing algorithms in a extensible hardware-agnostic way, using superconducting qubits as the first officially supported quantum technology. We first describe the status of all components of the library, then we show examples of control setup for superconducting qubits platforms. Finally, we present successful application results related to circuit-based algorithms.

An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration

Field Programmable Gate Array (FPGA) is a versatile and programmable hardware platform, which makes it a promising candidate for accelerating Deep Neural Networks (DNNs). However, FPGA’s computing energy efficiency is low due to the domination of energy consumption by interconnect data movement. In this article, we propose an all-digital Compute-in-memory FPGA architecture for deep learning acceleration. Furthermore, we present a bit-serial computing circuit of the Digital CIM core for accelerating vector-matrix multiplication (VMM) operations. A Network-CIM-deployer ( NCIMD ) is also developed to support automatic deployment and mapping of DNN networks. NCIMD provides a user-friendly API of DNN models in Caffe format. Meanwhile, we introduce a Weight-stationary dataflow and describe the method of mapping a single layer of the network to the CIM array in the architecture. We conduct experimental tests on the proposed FPGA architecture in the field of Deep Learning (DL), as well as in non-DL fields, using different architectural layouts and mapping strategies. We also compare the results with the conventional FPGA architecture. The experimental results show that compared to the conventional FPGA architecture, the energy efficiency can achieve a maximum speedup of 16.1×, while the latency can decrease up to 40% in our proposed CIM FPGA architecture.

Integrating Merkle Trees with Transformer Networks for Secure Financial Computation

In this paper, the Merkle-Transformer model is introduced as an innovative approach designed for financial data processing, which combines the data integrity verification mechanism of Merkle trees with the data processing capabilities of the Transformer model. A series of experiments on key tasks, such as financial behavior detection and stock price prediction, were conducted to validate the effectiveness of the model. The results demonstrate that the Merkle-Transformer significantly outperforms existing deep learning models (such as RoBERTa and BERT) across performance metrics, including precision, recall, accuracy, and F1 score. In particular, in the task of stock price prediction, the performance is notable, with nearly all evaluation metrics scoring above 0.9. Moreover, the performance of the model across various hardware platforms, as well as the security performance of the proposed method, were investigated. The Merkle-Transformer exhibits exceptional performance and robust data security even in resource-constrained environments across diverse hardware configurations. This research offers a new perspective, underscoring the importance of considering data security in financial data processing and confirming the superiority of integrating data verification mechanisms in deep learning models for handling financial data. The core contribution of this work is the first proposition and empirical demonstration of a financial data analysis model that fuses data integrity verification with efficient data processing, providing a novel solution for the fintech domain. It is believed that the widespread adoption and application of the Merkle-Transformer model will greatly advance innovation in the financial industry and lay a solid foundation for future research on secure financial data processing.

Hardware Acceleration for Object Detection using YOLOv5 Deep Learning Algorithm on Xilinx Zynq FPGA Platform

Object recognition presents considerable difficulties within the domain of computer vision. Field-Programmable Gate Arrays (FPGAs) offer a flexible hardware platform, having exceptional computing capabilities due to their adaptable topologies, enabling highly parallel, high-performance, and diverse operations that allow for customized reconfiguration of integrated circuits to enhance the effectiveness of object detection accelerators. However, there is a scarcity of assessments that offer a comprehensive analysis of FPGA-based object detection accelerators, and there is currently no comprehensive framework to enable object detection specifically tailored to the unique characteristics of FPGA technology. The You Only Look Once (YOLO) algorithm is an innovative method that combines speed and accuracy in object detection. This study implemented the YOLOv5 algorithm on a Xilinx® Zynq-7000 System on a Chip (SoC) to perform real-time object detection. Using the MS-COCO dataset, the proposed study showed an improvement in resource utilization with approximately 42 thousand (78%) look-up tables, 56 thousand (52%) flip-flops, 65 (46%) BRAMs, and 19 (9%) DSPs at a frequency of 250 MHz, improving the effectiveness compared to previous simulated results.

A framework for embedded software portability and verification: from formal models to low-level code

AbstractPorting software to new target architectures is a common challenge, particularly when dealing with low-level functionality in drivers or OS kernels that interact directly with hardware. Traditionally, adapting code for different hardware platforms has been a manual and error-prone process. However, with the growing demand for dependability and the increasing hardware diversity in systems like the IoT, new software development approaches are essential. This includes rigorous methods for verifying and automatically porting Real-Time Operating Systems (RTOS) to various devices. Our framework addresses this challenge through formal methods and code generation for embedded RTOS. We demonstrate a hardware-specific part of a kernel model in Event-B, ensuring correctness according to the specification. Since hardware details are only added in late modeling stages, we can reuse most of the model and proofs for multiple targets. In a proof of concept, we refine the generic model for two different architectures, also ensuring safety and liveness properties. We then showcase automatic low-level code generation from the model. Finally, a hardware-independent factorial function model illustrates more potential of our approach.

Design and construction of gradient coils for an MRI-guided small animal radiation platform

Small animal radiation experiments use a dedicated hardware platform to deliver radiation to small animals to support pre-clinical radiobiological studies. Image guidance is critical to achieve experiment accuracy. MR-based image guidance became recently available in human radiation therapy by integrating an MR scanner with a medical linear accelerator. Our group is developing a small animal MR-guidance system for pre-clinical radiation studies using a unique low-field unilateral magnet design. In this paper, we reported our design, construction, and characterization of split gradient coils for the MRI scanner. The coils were designed to have a 4 cm gap to allow the radiation beam to pass through for radiation experiments. We designed the coil patterns by solving an optimization problem. We constructed the coils by printing molds for the designed coil patterns using 3D printing technology and wiring the coils following the pattern. We measured parameters of the coils to characterize their performance. The coils achieved a linear magnetic field throughout a 4 cm spherical region of interest. The slew rates were 8640 and 1970 T/m⋅s, and the efficiencies were 1.2 and 0.21 mT/m⋅A for the Y-coil and X-coil, respectively. Preliminary imaging with the coils on our proposed system validates spatial encoding functions of the developed coils.

An Intelligent Classification Framework for Complex PQDs Using Optimized KS-Transform and Multiple Fusion CNN

Intelligent classification of multiple power quality disturbances (PQDs) is a top priority in pollution control of the power grid. However, the large-scale application of renewable energy introduces lots of nonlinear and impact loads, which makes the PQDs more complex and challenges the effectiveness of conventional detection frameworks. In this paper, a novel framework based on optimized Kaiser window-based S-transform (OKST) and multiple fusion convolutional neural network (MFCNN) is proposed to identify multiple complex PQDs. First, the OKST is used for the time-frequency positioning of PQDs, where an improved control function is proposed to meet different detection requirements of time-frequency. Additionally, the parameters of the control function are adjusted automatically using maximum energy concentration. Then, the MFCNN based on residual networks (ResNets) is further proposed to extract and classify these time-frequency features automatically. In MFCNN, feature information is fused using different convolution kernels at a 2-dimensional level, which can effectively reduce information loss and improve classification performance. The network model is set up using the Pytorch platform, and the dataset containing 28 types of PQDs and 2 types of nonlinearly mixed PQDs is built to test our framework. The result shows that the proposed OKST-MFCNN obtains an average accuracy of 99.38% under the 20 dB noise level, which is more accurate and robust than some advanced PQDs detection frameworks. Moreover, the accuracy of 97.94% is achieved with satisfactory real-time performance in hardware platform experiments, proving its superior identification performance for complex PQDs.