Hardware Platform Research Articles

Evaluation of Assembler and C Programming Languages on PIC16F877 Microcontroller

The programming of microcontrollers is essential for their correct operation, high computational efficiency, low-power solutions, and it is also key to get the most out of their capabilities with the hardware features that each of the microcontroller families has. There are different programming languages that can be used in microcontrollers, in this work we will focus on C and Assembler. C is one of the most widely used due to its efficiency and its ability to control the hardware directly. Assembly is a low-level language that allows more control over the instructions executed in the microcontroller, two songs have been implemented in assembler and C languages and the resources used for their execution on a Microchip PIC16F877 have been analyzed. The research results allow the developer to obtain results for a selection of the optimal hardware platform as well as the programming language according to the required memory utilization. Coding performed in MPLAB software with the asm and XC8 compilers, indicate that the C-code programs cover a larger amount of memory close to 4 times greater or higher.

Elementary cellular automata realized by stateful three-memristor logic operations

Cellular automata (CA) are computational systems that exhibit complex global behavior arising from simple local rules, making them a fascinating candidate for various research areas. However, challenges such as limited flexibility and efficiency on conventional hardware platforms still exist. In this study, we propose a memristor-based circuit for implementing elementary cellular automata (ECA) by extending the stateful three-memristor logic operations derived from material implication (IMP) logic gates. By leveraging the inherent physical properties of memristors, this approach offers simplicity, minimal operational steps, and high flexibility in implementing ECA rules by adjusting the circuit parameters. The mathematical principles governing circuit parameters are analyzed, and the evolution of multiple ECA rules is successfully demonstrated, showcasing the robustness in handling the stochastic nature of memristors. This approach provides a hardware solution for ECA implementation and opens up new research opportunities in the hardware implementation of CA.

Memory Usage Estimation for Dataflow-Model-Based Software Development Methodology

In designing software on an embedded hardware platform with limited memory size, it is critical to guarantee that the peak memory requirement does not exceed the memory capacity. We propose a memory usage estimation technique in a model-based software development methodology where the application code is synthesized from a dataflow model-based specification. To minimize the degree of overestimation without running the synthesized software, the proposed technique analyzes the binary file and shared library dependencies of dataflow tasks. We verify the proposed technique in developing real-life applications on Linux and bare-metal systems.

Field-programmable-gate-array based hardware platform for nitrogen-vacancy center based fast magnetic imaging

A nitrogen-vacancy center based scanning magnetic microscope can be used to characterize magnetics at the nanoscale with high sensitivity. This paper reports a field-programmable-gate-array based hardware system that is designed to realize control and signal readout for fast scanning magnetic imaging with a nitrogen-vacancy center. A 10-channel 1 Msps @ 20 bit analog signal generator, a 12-channel 50 ps resolution pulse generator, a 300 Msps @ 16 bit lock-in amplifier with proportional integral derivative control function, and a 4-channel 200 Msps counter are integrated on the platform. A customized acceleration algorithm is realized with the re-configurable field-programmable-gate-array chip to accelerate the imaging speed of the nitrogen-vacancy system, and the experimental results prove that the imaging efficiency can be accelerated by five times compared to the system without the acceleration algorithm. The platform has considerable potential for future applications of fast scanning magnetic imaging.

Sentiment Analysis in Portuguese Restaurant Reviews: Application of Transformer Models in Edge Computing

This study focuses on improving sentiment analysis in restaurant reviews by leveraging transfer learning and transformer-based pre-trained models. This work evaluates the suitability of pre-trained deep learning models for analyzing Natural Language Processing tasks in Portuguese. It also explores the viability of utilizing edge devices for Natural Language Processing tasks, considering their computational limitations and resource constraints. Specifically, we employ bidirectional encoder representations from transformers and robustly optimized BERT approach, two state-of-the-art models, to build a sentiment review classifier. The classifier’s performance is evaluated using accuracy and area under the receiver operating characteristic curve as the primary metrics. Our results demonstrate that the classifier developed using ensemble techniques outperforms the baseline model (from 0.80 to 0.84) in accurately classifying restaurant review sentiments when three classes are considered (negative, neutral, and positive), reaching an accuracy and area under the receiver operating characteristic curve higher than 0.8 when examining a Zomato restaurant review dataset, provided for this work. This study seeks to create a model for the precise classification of Portuguese reviews into positive, negative, or neutral categories. The flexibility of deploying our model on affordable hardware platforms suggests its potential to enable real-time solutions. The deployment of the model on edge computing platforms improves accessibility in resource-constrained environments.

Design, optimization, debugging, and simulation of an agricultural biomimetic hexapod robot

This paper comprehensively studies the model establishment, kinematic analysis, hardware design, software development, and agricultural applications of hexapod robot, laying a solid foundation for their practical application in the agricultural field and proposing prospects for future research and development. This article mainly conducts in-depth research on the mechanical design, kinematic analysis, hardware implementation, software development, and application in the agricultural field of hexapod robots. Firstly, a brief introduction to biomimetic robots will be provided, and a comparative analysis will be conducted on existing common legged robots. Afterwards, use solidworks-2021 for 3D modeling to draw the legs and main structure of the robot. In terms of kinematic analysis, by studying the mechanism structure and motion characteristics of hexapod robot, the forward and inverse kinematic equations are derived, and the gait planning and motion control algorithms of the robot are analyzed in detail. These analyses provide a theoretical basis for the robot's program and actual motion. In terms of hardware, a lightweight and high-performance hexapod robot hardware platform has been designed using mainstream controllers such as Borboardino and ultrasonic sensors. This hardware platform has excellent responsiveness and adaptability, and can efficiently move and operate in complex agricultural environments. In terms of software, a comprehensive control system has been developed, including motion planning, action execution, and obstacle avoidance modules. By integrating triangular gait technology and related algorithms, robot can achieve navigation and obstacle avoidance, and perform tasks such as crop planting and spraying in the agricultural field. The simulation file of the hexapod robot was established using CoppeliaSim software, achieving motion based on the robot body, six legs, and end effectors. Finally, a 3D-printer is used to print and assemble all components, and complete the design through debugging and verification. The hexapod robot is capable of autonomous cruising in farmland, completing tasks such as planting and watering crops, providing efficient and intelligent agricultural production solutions for farmers.

Abnormal crop warning system based on OpenMV

In order to realize the early warning of abnormal crops, the photographing technology and image recognition technology of openMV and openCV are comprehensively applied to study the early warning of abnormal crops. The design take photos using openMV hardware platform and connects to the cloud through 5G module. Then it conducts in-depth processing such as gray processing, image denoising and boundary detection on the photos through the network server to obtain the location and size of abnormal areas, so as to help spray pesticides later and improve production efficiency.

Training multi-layer spiking neural networks with plastic synaptic weights and delays.

Spiking neural networks are usually considered as the third generation of neural networks, which hold the potential of ultra-low power consumption on corresponding hardware platforms and are very suitable for temporal information processing. However, how to efficiently train the spiking neural networks remains an open question, and most existing learning methods only consider the plasticity of synaptic weights. In this paper, we proposed a new supervised learning algorithm for multiple-layer spiking neural networks based on the typical SpikeProp method. In the proposed method, both the synaptic weights and delays are considered as adjustable parameters to improve both the biological plausibility and the learning performance. In addition, the proposed method inherits the advantages of SpikeProp, which can make full use of the temporal information of spikes. Various experiments are conducted to verify the performance of the proposed method, and the results demonstrate that the proposed method achieves a competitive learning performance compared with the existing related works. Finally, the differences between the proposed method and the existing mainstream multi-layer training algorithms are discussed.

Comparative analysis and FPGA realization of different control synchronization approaches for chaos-based secured communication systems.

Synchronization of the chaotic systems has attracted much attention in recent years due to its vital applications in secured communication systems. In this paper, an implementation and comparative analysis of two different control approaches for synchronization between two identical four-dimensional hyperchaotic systems is presented. The two control approaches are the Adaptive nonlinear controller and the linear optimal quadratic regulator LQR. To demonstrate the effectiveness of each controller, the numerical simulation is presented using Matlab/Simulink and the control law is derived. The performance of the proposed controllers is compared based on four factors; response time, squared error integration, energy applied from the controller, and cost function. To measure the robustness of the control approaches, the performance factors are compared when there is a change in system parameters and a variation in the initial conditions. Then the proposed synchronization methods are implemented on the FPGA platform to demonstrate the utilized resources on Field Programmable Gate Array (FPGA) hardware platform and the operation speed. Finally, to generalize the results of the comparison, the study is implemented for the synchronization of another secured communication system consisting of two identical three-dimensional chaotic. The experimental results show that the LQR method is more effective than the Adaptive controller based on the performance factors we propose. Moreover, the LQR is much simpler to implement on hardware and requires fewer resources on the FPGA.

HomeRobot: An Open Source Software Stack for Mobile Manipulation Research

Reproducibility in robotics research requires capable, shared hardware platforms which can be used for a wide variety of research. We’ve seen the power of these sorts of shared platforms in more general machine learning research, where there is constant iteration on shared AI platforms like PyTorch. To be able to make rapid progress in robotics in the same way, we propose that we need: (1) shared real-world platforms which allow different teams to test and compare methods at low cost; (2) challenging simulations that reflect real-world environments and especially can drive perception and planning research; and (3) low-cost platforms with enough software to get started addressing all of these problems. To this end, we propose HomeRobot, a mobile manipulator software stack with associated benchmark in simulation, which is initially based on the low-cost, human-safe Hello Robot Stretch.

Pseudorange reconstruction for high‐dynamic eLoran signal simulators using B‐spline interpolation

AbstractThe High‐Dynamic enhanced Loran (eLoran) signal simulator must accurately model the motion parameters and dynamic transmission delays of the carriers in the channel. A method was proposed based on B‐Spline interpolation, capable of arbitrary ratio interpolation and multi‐channel simulation. This method can regenerate carrier‐to‐transmitter distances from available discrete motion asynchronous data, it can effectively reproduce more motion details for carrier. The algorithm can be implemented using digital circuits, allowing for real‐time simulation on a hardware platform. The circuit structure is divided into integer and fractional calculations, which can satisfy the interpolation of asynchronous data with arbitrary ratios. Compared with existing methods, the approach simulates the motion parameters with satisfactory accuracy.

Energy Efficient ECC Authenticated Key Exchange Protocol for Star Topology Wireless Sensor Networks

The article proposes a new energy-efficient protocol designed for star topology wireless sensor networks. The protocol has been implemented using ECC, although it can be easily adapted to any algebraic structure, where the discrete logarithm problem is computationally challenging. In addition to the formal description, the authors provide the results of an investigation concerned with the protocol's security properties, conducted by verifying the model using Scyther software. The publication also includes an analysis of the protocol's energy consumption, performed with the use of hardware platforms with ARM microcontrollers.

A Low-Latency Approach for RFF Identification in Open-Set Scenarios

Radio frequency fingerprint (RFF) identification represents a promising technique for lightweight device authentication. However, current research on RFF primarily focuses on the close-set recognition assumption. Moreover, the high computational complexity and excessive latency during the identification stage represent an intolerable burden for Internet of Things (IoT) devices. In this paper, we propose a deep-learning-based RFF identification framework in relation to open-set scenarios. Specifically, we leverage a simulated training scheme, in which we strategically designate certain devices as simulated unknowns. This allows us to fine-tune our extractor to better handle open-set recognition. Additionally, we construct an exemplar set that only contains representative RFF features to further reduce time consumption in the identification stage. The experiments are carried out on a hardware platform involving LoRa devices and using a USRP N210 software-defined radio receiver. The results show that the proposed framework can achieve 90.23% accuracy for rogue device detection and 93.85% accuracy for legitimate device classification. Furthermore, it is observed that using an exemplar set consisting of half the total data size can reduce the time overhead by 58% compared to using the entire dataset.

Insulation Detection of Electric Vehicles by Using FPGA-Based Recursive-Least-Squares Algorithm

The principal reason for why electric vehicles are required to serve as an alternative to the more widespread gasoline and petroleum-based vehicles used in modern times is due to the use of an environmentally conscious means of transportation or to circumvent the tumultuous economic dealings of the compressed natural gas and petroleum industries. There is a growing daily need for large, high-voltage e-mobilities, mostly driven by anticipated advancements in electric vehicle technology. Consequently, all of the various components of these vehicles must be able to be accommodated within a limited and compact space. The battery is an essential component in e-mobility. The insulation, health monitoring, and problem diagnostics of lithium-ion (Li-ion) batteries are of utmost importance in ensuring these vehicles’ safety and efficient functioning. Real-time and fast insulation detection techniques are required to ensure safety in high-voltage (HV) vehicles and to avoid insulation failure. This paper used the Recursive-Least-Squares (RLS) algorithm because it is computationally efficient for building the insulation detection system. Based on the RLS technique, we proposed field programmable gate array (FPGA)-based algorithms and implemented them using VHDL coding. The FPGA is very fast at detection, and the error is lower. We validated the FPGA results with MATLAB simulation results from the existing literature, and the errors are much less when using FPGAs. An experimental hardware platform was also created to validate the proposed FPGA technique with various motor and resistive loadings on electric vehicles (EVs).

Flexible silicon photonic architecture for accelerating distributed deep learning

The increasing size and complexity of deep learning (DL) models have led to the wide adoption of distributed training methods in datacenters (DCs) and high-performance computing (HPC) systems. However, communication among distributed computing units (CUs) has emerged as a major bottleneck in the training process. In this study, we propose Flex-SiPAC, a flexible silicon photonic accelerated compute cluster designed to accelerate multi-tenant distributed DL training workloads. Flex-SiPAC takes a co-design approach that combines a silicon photonic hardware platform with a tailored collective algorithm, optimized to leverage the unique physical properties of the architecture. The hardware platform integrates a novel wavelength-reconfigurable transceiver design and a micro-resonator-based wavelength-reconfigurable switch, enabling the system to achieve flexible bandwidth steering in the wavelength domain. The collective algorithm is designed to support reconfigurable topologies, enabling efficient all-reduce communications that are commonly used in DL training. The feasibility of the Flex-SiPAC architecture is demonstrated through two testbed experiments. First, an optical testbed experiment demonstrates the flexible routing of wavelengths by shuffling an array of input wavelengths using a custom-designed spatial-wavelength selective switch. Second, a four-GPU testbed running two DL workloads shows a 23% improvement in job completion time compared to a similarly sized leaf-spine topology. We further evaluate Flex-SiPAC using large-scale simulations, which show that Flex-SiPAC is able to reduce the communication time by 26% to 29% compared to state-of-the-art compute clusters under representative collective operations.

FPGA-friendly compact and efficient AES-like 8 × 8 S-box

One of the main layers in the Advanced Encryption Standard (AES) is the substitution layer, where an 8 × 8 S-Box is used 16 times. The substitution layer provides confusion and makes the algorithm resistant to cryptanalysis techniques. Therefore, the security of the algorithm is also highly dependent on this layer. However, the cost of implementing 8 × 8 S-Box on FPGA platforms is considerably higher than other layers of the algorithm. Since S-Boxes are repeatedly used in the algorithm, the cost of the algorithm highly comes from the substitution layer. In 2005, Canright used different extension fields to represent AES S-Box to get FPGA-friendly compact designs. The best optimization proposed by Canright reduced the gate-area of the AES S-Box implementation by 20%.In this study, we use the same optimization methods that Canright used to optimize AES S-Box on hardware platforms. Our purpose is not to optimize AES S-Box; we aim to create another 8 × 8 S-Box which is strong and compact enough for FPGA platforms. We create an 8 × 8 S-Box using the inverse field operation as in the case of AES S-Box. We use another irreducible polynomial to represent the finite field and get an FPGA-friendly compact and efficient 8 × 8 S-Box. The finite field we propose provides the same level of security against cryptanalysis techniques with a 3.125% less gate-area on Virtex-7 and Artix-7 FPGAs compared to Canright’s results. Moreover, our proposed S-Box requires 11.76% less gate on Virtex-4 FPGAs. These gate-area improvements are beneficial for resource-constraint IoT devices and allow more copies of the S-Box for algorithm parallelism. Therefore, we claim that our proposed S-Box is more compact and efficient than AES S-Box. Cryptographers who need an 8 × 8 S-Box can use our proposed S-Box in their designs instead of AES S-Box with the same level of security but better efficiency.

Integrated multi-operand optical neurons for scalable and hardware-efficient deep learning

Abstract Optical neural networks (ONNs) are promising hardware platforms for next-generation neuromorphic computing due to their high parallelism, low latency, and low energy consumption. However, previous integrated photonic tensor cores (PTCs) consume numerous single-operand optical modulators for signal and weight encoding, leading to large area costs and high propagation loss to implement large tensor operations. This work proposes a scalable and efficient optical dot-product engine based on customized multi-operand photonic devices, namely multi-operand optical neuron (MOON). We experimentally demonstrate the utility of a MOON using a multi-operand-Mach–Zehnder-interferometer (MOMZI) in image recognition tasks. Specifically, our MOMZI-based ONN achieves a measured accuracy of 85.89 % in the street view house number (SVHN) recognition dataset with 4-bit voltage control precision. Furthermore, our performance analysis reveals that a 128 × 128 MOMZI-based PTCs outperform their counterparts based on single-operand MZIs by one to two order-of-magnitudes in propagation loss, optical delay, and total device footprint, with comparable matrix expressivity.

An algorithm/hardware co‐optimized method to accelerate CNNs with compressed convolutional weights on FPGA

SummaryConvolutional neural networks (CNNs) have shown remarkable advantages in a wide range of domains at the expense of huge parameters and computations. Modern CNNs still tend to be more complex and larger to achieve better inference accuracy. However, the complex and large structures of CNNs could slow down the inference speed. Recently, Compressing the convolutional weights to be sparse by pruning the unimportant parameters has been demonstrated as an efficient way to reduce the computations of CNNs. On the other hand, field‐programmable gate arrays (FPGAs) have been a popular hardware platform to accelerate CNN inference. In this paper, we propose an algorithm/hardware co‐optimized method for accelerating CNN inference on FPGAs. For the algorithm, we take advantage of unstructured and structured parameter sparsifying methods to achieve high sparsity and keep the regularity of convolutional weights. Correspondingly, hardware‐friendly index representations of sparse convolutional weights are proposed. For the hardware architecture, we propose row‐wise input‐stationary dataflow, which is tightly coupled with the algorithm. A row‐wise computing engine (RConv Engine) is proposed, which is based on the dataflow. Inside the RConv Engine, the scalar‐vector structure is applied to implement the basic processing elements (PEs). To flexibly calculate the feature map with various sizes, the PEs are organized in a 2D structure with two work modes. The experimental results demonstrate that our co‐optimized method implements high sparsity of convolutional weights, and the computing engine achieves high computation efficiency. Compared with other accelerators, our co‐optimized method implements a 10.9 speedup on FPS at most with the highest sparsity of convolutional weights and negligible accuracy loss.

3D vision technologies for a self-developed structural external crack damage recognition robot

Persistent cracking and progressive damage can weaken the operational performance of structures such as bridges, dams, and concrete buildings. Consequently, research into automated, high-precision crack detection methods remains pivotal within the realm of structural health monitoring (SHM). Presently, scholars predominantly rely on two-dimensional (2D) image-based algorithms for crack detection. However, these methods commonly struggle to accurately locate the three-dimensional (3D) coordinates of cracks on large structures and to extract the 3D contours of cracks. To address this challenge, this study proposes an automated 3D crack detection system for structures based on high-precision Light Detection and Ranging (LiDAR) and camera fusion. Firstly, precise registration of images and LiDAR point clouds was achieved through accurate extrinsic calibration of the sensors. Secondly, the lightweight MobileNetV2_DeepLabV3 crack semantic segmentation network was employed to detect and locate cracks. Finally, by automatically guiding the robotic arm, an industry-standard depth camera was able to capture high-precision 3D information about the crack at close observation points. Compared with the existing studies, this study emphasizes the extraction of high-precision 3D crack features and verifies the validity of the method by comparing the measurement results with those of the traditional method, demonstrating a remarkable measurement accuracy reaching sub-millimeter levels (0.1 mm). Moreover, the study introduces a comprehensive hardware platform and algorithmic framework, offering pioneering theoretical methodologies and replicable equipment references for automated surveillance and monitoring systems dedicated to structural health.

Influence of the operating regime of the magnonic active ring oscillator on the performance of the magnonic reservoir computer based on it

A magnonic active ring oscillator based on an yttrium iron garnet (YIG) is a promising hardware platform for physical reservoir computing. It meets the required conditions for the availability of fading memory and nonlinearity. However, its performance still needs further improvement. Two methods can be employed to improve the performance. One is increasing the time of establishing steady self-oscillations in the auto-oscillator. The second one is increasing the amplitude of spin waves propagating in the YIG film. In this work, we achieve an increase of the amplitude of the reservoir response by broadening the available range for the ring gain coefficient. We use a metallized YIG film as a waveguide in which spin waves propagate. This shifts up the amplitude threshold for the development of spin wave modulation instability in the ring. The threshold defines the upper limit of the gain range for the ring. Binary pulse sequence is entered into the ring by switching its gain between upper and lower levels. The modulation instability threshold then sets the upper limit for the higher gain level. In addition, in this work, we set the lower level of the gain to negative values. This is one more improvement with respect to earlier works. Switching the gain between a negative and a positive value increases the amplitude of the reservoir response and the depth of its fading memory. We employ the standard short-term memory and parity-check tests to quantify the performance of the reservoir computer. Both tests demonstrate an increase in the computational efficiency of the magnonic reservoir.