Hardware Optimization Research Articles

Automatic Deployment of Convolutional Neural Networks on FPGA for Spaceborne Remote Sensing Application

In recent years, convolutional neural network (CNN)-based algorithms have been widely used in remote sensing image processing and show tremendous performance in a variety of application fields. However, large amounts of data and intensive computations make the deployment of CNN-based algorithms a challenging problem, especially for the spaceborne scenario where resources and power consumption are limited. To tackle this problem, this paper proposes an automatic CNN deployment solution on resource-limited field-programmable gate arrays (FPGAs) for spaceborne remote sensing applications. Firstly, a series of hardware-oriented optimization methods are proposed to reduce the complexity of the CNNs. Secondly, a hardware accelerator is designed. In this accelerator, a reconfigurable processing engine array with efficient convolutional computation architecture is used to accelerate CNN-based algorithms. Thirdly, to bridge the optimized CNNs and hardware accelerator, a compilation toolchain is introduced into the deployment solution. Through the automatic conversion from CNN models to hardware instructions, various networks can be deployed on hardware in real-time. Finally, we deployed an improved VGG16 network and an improved YOLOv2 network on Xilinx AC701 to evaluate the effectiveness of the proposed deployment solution. The experiments show that with only 3.407 W power consumption and 94 DSP consumption, our solution achieves 23.06 giga operations per second (GOPS) throughput in the improved VGG16 and 22.17 GOPS throughput in the improved YOLOv2. Compared to the related works, the DSP efficiency of our solution is improved by 1.3–2.7×.

Towards a Secure and Scalable Maritime Monitoring System Using Blockchain and Low-Cost IoT Technology

Maritime Domain Awareness (MDA) is a strategic field of study that seeks to provide a coastal country with an effective monitoring of its maritime resources and its Exclusive Economic Zone (EEZ). In this scope, a Maritime Monitoring System (MMS) aims to leverage active surveillance of military and non-military activities at sea using sensing devices such as radars, optronics, automatic Identification Systems (AISs), and IoT, among others. However, deploying a nation-scale MMS imposes great challenges regarding the scalability and cybersecurity of this heterogeneous system. Aiming to address these challenges, this work explores the use of blockchain to leverage MMS cybersecurity and to ensure the integrity, authenticity, and availability of relevant navigation data. We propose a prototype built on a permissioned blockchain solution using HyperLedger Fabric—a robust, modular, and efficient open-source blockchain platform. We evaluate this solution’s performance through a practical experiment where the prototype receives sensing data from a Software-Defined-Radio (SDR)-based low-cost AIS receiver built with a Raspberry Pi. In order to reduce scalability attrition, we developed a dockerized blockchain client easily deployed on a large scale. Furthermore, we determined, through extensive experimentation, the client optimal hardware configuration, also aiming to reduce implementation and maintenance costs. The performance results provide a quantitative analysis of the blockchain technology overhead and its impact in terms of Quality of Service (QoS), demonstrating the feasibility and effectiveness of our solution in the scope of an MMS using AIS data.

An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems

Data reduction technologies have proven their effectiveness to decrease the ever-growing demands on storage system capacities, but also introduce new complexity in the system I/O stack that can easily invalidate well-known best practices. In this paper, we conduct an extensive set of experiments on an enterprise all-flash storage (AFS) system equipped with an open-source data reduction module, i.e., RedHat VDO, and reveal novel observations on the performance gap between the state-of-the-art and the optimal AFS stack with integrated data reduction. We then offer cross-layer optimizations to enhance the performance of AFS, which range from deriving new optimal hardware RAID configurations up to modifications of the enterprise storage stack tailored to the major bottlenecks observed. By implementing all proposed optimizations in an enterprise AFS, we show up to 12.5x speedup over the baseline AFS with integrated data reduction, and up to 57x performance/cost improvement over an optimized AFS (with no data reduction) for 100% write, high-reduction workload scenarios.

Hardware Optimizations of the X-ray Pre-Processing for Interventional Computed Tomography Using the FPGA

In computed tomography imaging, the computationally intensive tasks are the pre-processing of 2D detector data to generate total attenuation or line integral projections and the reconstruction of the 3D volume from the projections. This paper proposes the optimization of the X-ray pre-processing to compute total attenuation projections by avoiding the intermediate step to convert detector data to intensity images. In addition, to fulfill the real-time requirements, we design a configurable hardware architecture for data acquisition systems on FPGAs, with the goal to have a “on-the-fly” pre-processing of 2D projections. Finally, this architecture was configured for exploring and analyzing different arithmetic representations, such as floating-point and fixed-point data formats. This design space exploration has allowed us to find the best representation and data format that minimize execution time and hardware costs, while not affecting image quality. Furthermore, the proposed architecture was integrated in an open-interface computed tomography device, used for evaluating the image quality of the pre-processed 2D projections and the reconstructed 3D volume. By comparing the proposed solution with the state-of-the-art pre-processing algorithm that make use of intensity images, the latency was decreased 4.125×, and the resources utilization of ∼6.5×, with a mean square error in the order of 10−15 for all the selected phantom experiments. Finally, by using the fixed-point representation in the different data precisions, the latency and the resource utilization were further decreased, and a mean square error in the order of 10−1 was reached.

Hardware-Robust In-RRAM-Computing for Object Detection

In-memory computing is becoming a popular architecture for deep-learning hardware accelerators recently due to its highly parallel computing, low power, and low area cost. However, in-RRAM computing (IRC) suffered from large device variation and numerous nonideal effects in hardware. Although previous approaches including these effects in model training successfully improved variation tolerance, they only considered part of the nonideal effects and relatively simple classification tasks. This paper proposes a joint hardware and software optimization strategy to design a hardware-robust IRC macro for object detection. We lower the cell current by using a low word-line voltage to enable a complete convolution calculation in one operation that minimizes the impact of nonlinear addition. We also implement ternary weight mapping and remove batch normalization for better tolerance against device variation, sense amplifier variation, and IR drop problem. An extra bias is included to overcome the limitation of the current sensing range. The proposed approach has been successfully applied to a complex object detection task with only 3.85\% mAP drop, whereas a naive design suffers catastrophic failure under these nonideal effects.

A Real-Time 1280 × 720 Object Detection Chip With 585 MB/s Memory Traffic

Memory bandwidth has become the real-time bottleneck of current deep learning accelerators (DLA), particularly for high definition (HD) object detection. Under resource constraints, this paper proposes a low memory traffic DLA chip with joint hardware and software optimization. To maximize hardware utilization under memory bandwidth, we morph and fuse the object detection model into a group fusion-ready model to reduce intermediate data access. This reduces the YOLOv2's feature memory traffic from 2.9 GB/s to 0.15 GB/s. To support group fusion, our previous DLA based hardware employes a unified buffer with write-masking for simple layer-by-layer processing in a fusion group. When compared to our previous DLA with the same PE numbers, the chip implemented in a TSMC 40nm process supports 1280x720@30FPS object detection and consumes 7.9X less external DRAM access energy, from 2607 mJ to 327.6 mJ.

An Enterprise-Grade Open-Source Data Reduction Architecture for All-Flash Storage Systems

All-flash storage (AFS) systems have become an essential infrastructure component to support enterprise applications, where sub-millisecond latency and very high throughput are required. Nevertheless, the price per capacity ofsolid-state drives (SSDs) is relatively high, which has encouraged system architects to adoptdata reduction techniques, mainlydeduplication andcompression, in enterprise storage solutions. To provide higher reliability and performance, SSDs are typically grouped usingredundant array of independent disk (RAID) configurations. Data reduction on top of RAID arrays, however, adds I/O overheads and also complicates the I/O patterns redirected to the underlying backend SSDs, which invalidates the best-practice configurations used in AFS. Unfortunately, existing works on the performance of data reduction do not consider its interaction and I/O overheads with other enterprise storage components including SSD arrays and RAID controllers. In this paper, using a real setup with enterprise-grade components and based on the open-source data reduction module RedHat VDO, we reveal novel observations on the performance gap between the state-of-the-art and the optimal all-flash storage stack with integrated data reduction. We therefore explore the I/O patterns at the storage entry point and compare them with those at the disk subsystem. Our analysis shows a significant amount of I/O overheads for guaranteeing consistency and avoiding data loss through data journaling, frequent small-sized metadata updates, and duplicate content verification. We accompany these observations with cross-layer optimizations to enhance the performance of AFS, which range from deriving new optimal hardware RAID configurations up to introducing changes to the enterprise storage stack. By analyzing the characteristics of I/O types and their overheads, we propose three techniques: (a) application-aware lazy persistence, (b) a fast, read-only I/O cache for duplicate verification, and (c) disaggregation of block maps and data by offloading block maps to a very fast persistent memory device. By consolidating all proposed optimizations and implementing them in an enterprise AFS, we show 1.3× to 12.5× speedup over the baseline AFS with 90% data reduction, and from 7.8× up to 57× performance/cost improvement over an optimized AFS (with no data reduction) running applications ranging from 100% read-only to 100% write-only accesses.

Energy Efficient Hardware Loop Based Optimization for CGRAs

Research interest and industry investment in edge computing solutions have increased dramatically in recent years. Consequent quest for balanced performance, energy efficiency and flexibility bestowed surging popularity on Coarse Grained Reconfigurable Array (CGRA) architectures. To further improve the performance and energy efficiency, several hardware and software-based loop optimizations are adopted for CGRAs. In this paper, we propose a centralized hardware-based loop optimization technique to achieve better area and energy results compared to the previously implemented distributed version. Without incurring any performance degradation, area overhead against the reference architecture is reduced down to \(1.5\%\) for a 4\(\times\)2 CGRA configuration. A maximum of \(47.3\%\) and an arithmetic mean of \(27.2\%\) reduction in energy consumption is attained by the centralized version of hardware loop compared to the baseline model employing software loop. Furthermore, the paper explores the co-existence of CGRA-specific hardware and software optimizations and their impact on loop efficiencies. Enhanced results are obtained by coupling loop unrolling with centralized hardware loop support. The combination allows achieving up to \(68.7\%\) reduction in energy consumption and 5.46\(\times\) speed-up against the baseline model with no optimizations applied.

An Efficient Hardware Design for Accelerating Sparse CNNs With NAS-Based Models

Deep convolutional neural networks (CNNs) have achieved remarkable performance at the cost of huge computation. As the CNN models become more complex and deeper, compressing CNNs to sparse by pruning the redundant connection in the networks has emerged as an attractive approach to reduce the amount of computation and memory requirement. On the other hand, FPGAs have been demonstrated to be an effective hardware platform to accelerate CNN inference. However, most existing FPGA accelerators focus on dense CNN models, which are inefficient when executing sparse models as most of the arithmetic operations involve addition and multiplication with zero operands. In this work, we propose an accelerator with software–hardware co-design for sparse CNNs on FPGAs. To efficiently deal with the irregular connections in the sparse convolutional layers, we propose a weight-oriented dataflow that exploits element–matrix multiplication as the key operation. Each weight is processed individually, which yields low decoding overhead. Then, we design an FPGA accelerator that features a tile look-up table (TLUT) and a channel multiplexer (CMUX). The TLUT is designed to match the index between sparse weights and input pixels. Using TLUT, the runtime decoding overhead is mitigated by using an efficient indexing operation. Moreover, we propose a weight layout to enable efficient on-chip memory access without conflicts. To cooperate with the weight layout, a CMUX is inserted to locate the address. Finally, we build a neural architecture search (NAS) engine that leverages the reconfigurability of FPGAs to generate an efficient CNN model and choose the optimal hardware design parameters. The experiments demonstrate that our accelerator can achieve 223.4-309.0 GOP/s for the modern CNNs on Xilinx ZCU102, which provides a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.4\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$12.9\times $ </tex-math></inline-formula> speedup over previous dense CNN accelerators on FPGAs. Our FPGA-aware NAS approach shows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> speedup over MobileNetV2 with 1.5% accuracy loss.

Leveraging special-purpose hardware for local search heuristics

As we approach the physical limits predicted by Moore’s law, a variety of specialized hardware is emerging to tackle specialized tasks in different domains. Within combinatorial optimization, adiabatic quantum computers, complementary metal-oxide semiconductor annealers, and optical parametric oscillators are a few emerging specialized hardware technologies to solve optimization problems. The Ising optimization model unifies all of these emerging special-purpose hardware for optimization in terms of mathematical framework. In other words, they are all designed to solve optimization problems expressed in the Ising model or equivalently as a quadratic unconstrained binary optimization model. Due to various constraints specific to each type of hardware, they usually suffer from a major challenge: the number of variables that the hardware can manage to solve is very limited. The local search meta-heuristic is one of the approaches to tackle large-scale problems. However, a general optimization step within local search is not traditionally formulated in the Ising form. In this work, we introduce a new modeling framework for modeling local search heuristics for special-purpose hardware. In particular, we propose models that take the limitations of the Ising model and current hardware into account. As such, we demonstrate the advantage of our approach compared to previous methods by carrying out experiments to show that our local search models produce higher-quality solutions.

GALU: A Genetic Algorithm Framework for Logic Unlocking

Logic locking is a circuit obfuscation technique that inserts additional key gates to the original circuit in order to prevent potential threats such as circuit overproduction, piracy, and counterfeiting. The encrypted circuit generates desired outputs only when the correct keys are applied to the key gates. Previous works have identified the vulnerability of logic locking to satisfiability (SAT)-based attacks. However, SAT attacks are unscalable and have limited effectiveness on circuits with SAT-hard structures. To address the above constraints, we propose GALU, the first genetic algorithm-based logic unlocking framework that is parallelizable and significantly faster than the conventional SAT-based counterparts. GALU works by formulating circuit deobfuscation (i.e., identifying the correct keys) as a combinatorial optimization problem and approaches it using genetic algorithms (GAs). We consider key sequences as individuals in distinct populations and propose an adaptive, diversity-guided GA framework consisting of four main steps: circuit fitness evaluation, population selection, crossover, and mutation. In each iteration, the key sequences with high fitness scores are selected and transformed into the offspring key sequences. As a result of evolutionary key searching, GALU is highly scalable, effective, and efficient. To optimize the runtime overhead of logic unlocking, we integrate the design of GALU’s algorithm, software and hardware in a closed loop. In particular, we identify circuit fitness evaluation as the performance bottleneck and employ hardware emulation on programmable hardware for runtime optimization. To this end, GALU framework automatically constructs customized auxiliary circuitry to pipeline the computation in constraints checking, sorting, crossover, and mutation. GALU is the first adaptive and scalable attack framework that provides the flexibility/trade-off between runtime overhead and key usability. This is achieved by producing a group of approximate keys with improving quality over time. We perform a comprehensive evaluation of GALU’s performance on various benchmarks and demonstrate that GALU achieves up to 1089.2× speedup and 4268.6× more energy-efficiency compared to the state-of-the-art SAT attacks for circuit logic unlocking.

A Virtual EMG Signal Control and Analysis for Optimal Hardware Design

Background: A muscle-computer interface is one of the new applications of the human-computer interface technologies and specifically the brain-computer interface. Brain-muscle-computer interface based on the Electromyography (EMG) signal. EMG signal is an electrical activity from a muscle that is used as an input for effecting several tasks.Objective: This work presented an interfacing process between the Graphical User Interface (GUI) and hardware system. Using the implemented system, the researcher shall deals with the raw EMG data easily by analyzing the signal from the muscle sensor detection.Material and Methods: A novel virtual EMG signal control and analysis system design is proposed in this work. The system consists mainly of two parts, hardware and software toolbox. Hardware design is mainly dependent on using a muscle movement sensor as well as the feedback from the virtual toolbox. The virtual software design offers a relatively simple design of a friendly graphical user interface. It consists mainly of the input EMG signal and output signal after using different processing methods. Feedback response from the final EMG signal results after the processing may help the designer to present the optimal hardware design.Results: The output results show the output performance of the proposed virtual EMG data controlling and analysis with the implemented hardware design of the muscle sensor movement detection. The results show promise that these interfaces may provide a new option to benefit the designer in choosing the optimal prosthesis design of severely disabled persons.

Single-Center Retrospective Analysis of Device-Related Complications Related to Dorsal Root Ganglion Stimulation for Pain Relief in 31 Patients

IntroductionDorsal root ganglion (DRG) stimulation is a form of neuromodulation used to treat neuropathic pain due to a myriad of etiologies. Though this relatively new therapy has been shown to be quite effective, complications associated with the implantation of this therapy have not been well documented. ObjectivesThe primary objective of this study was to describe the device-related complications associated with DRG stimulator implantations. Materials and MethodsThis was a single-center retrospective analysis of 31 patients who underwent full implantation of neuromodulation hardware marketed for DRG stimulation. The predefined endpoints included device-related complications associated with DRG implantations, such as hardware failure, explantation procedures, and revision surgery. Additional endpoints included percentage of patients receiving therapy and pain as measured using the visual analog scale (VAS) pain scale at initial, six-month, and 12-month follow-up after hardware implantation. ResultsThirty-one patients were included out of 42 patients trialed. Baseline VAS in patients was 7.7 (31 patients). At initial follow-up, six-month follow-up, and one-year follow-up, VAS scores were 4.7 (31 patients), 5.3 (20 patients), and 5.5 (13 patients), respectively. Paired t-test between preoperative VAS (mean 7.3) and one-year follow-up VAS (5.5) demonstrated statistical significance (p = 0.027). At initial, six-month, and one-year follow-up, 30/31 (97%), 19/24 (79%), and 18/23 (78%) patients were confirmed to be receiving DRG stimulation therapy after permanent implant. Of the 31 patients who were implanted with a permanent system, 8 (26%) were explanted and an additional 10 (29%) required revision surgery. ConclusionIn this study, we examine the various device-related complications associated with DRG stimulation requiring repeat surgery. High rates of hardware failure, revision surgery, and explantation of stimulators illustrate the need for hardware optimization to improve patient outcomes.

3-regular three-XORSAT planted solutions benchmark of classical and quantum heuristic optimizers

With current semiconductor technology reaching its physical limits, special-purpose hardware has emerged as an option to tackle specific computing-intensive challenges. Optimization in the form of solving quadratic unconstrained binary optimization problems, or equivalently Ising spin glasses, has been the focus of several new dedicated hardware platforms. These platforms come in many different flavors, from highly-efficient hardware implementations on digital-logic of established algorithms to proposals of analog hardware implementing new algorithms. In this work, we use a mapping of a specific class of linear equations whose solutions can be found efficiently, to a hard constraint satisfaction problem (three-regular three-XORSAT, or an Ising spin glass) with a ‘golf-course’ shaped energy landscape, to benchmark several of these different approaches. We perform a scaling and prefactor analysis of the performance of Fujitsu’s digital annealer unit (DAU), the D-Wave advantage quantum annealer, a virtual MemComputing machine, Toshiba’s simulated bifurcation machine (SBM), the SATonGPU algorithm from Bernaschi et al, and our implementation of parallel tempering. We identify the SATonGPU and DAU as currently having the smallest scaling exponent for this benchmark, with SATonGPU having a small scaling advantage and in addition having by far the smallest prefactor thanks to its use of massive parallelism. Our work provides an objective assessment and a snapshot of the promise and limitations of dedicated optimization hardware relative to a particular class of optimization problems.

Field-programmable gate arrays-based Morris-Lecar implementation using multiplierless digital approach and new divider-exponential modules

Simulation, modeling, and hardware implementation of different parts of central nervous system (CNS) are very attractive research areas in terms of neuromorphic engineering aspects. Considering the neuronal parts of the human brain, the hardware implementation of neural models of spiking neural networks should be evaluated from preparing a simple efficient model and optimal hardware implementation. In this paper, Morris-Lecar (ML) model as a biological neuronal model with nonlinear differential equations and hyperbolic functions is discussed. This original model with non-linear complex functions needs high-computational high-cost hardware implementation on Field-Programmable Gate Arrays (FPGA). This paper presents a new divider module and exponential term (2X) to provide low-cost and high-speed implementation of original ML called Division-Based ML (DBML). DBML model suggests simpler equations using division-based exponential terms, logical shifts and simple arithmetic operations. Thus, high-performance neuronal design is presented following original ML model in terms of time domain and different dynamic behaviors.

Review of energy‐dispersive X‐ray fluorescence on food elements detection

AbstractEnergy‐dispersive X‐ray fluorescence (EDXRF) is a physical rapid detection method to analyze the types of elements through the energy characteristics of fluorescent X‐ray particles. When applied to the detection of food element content, it not only needs simple sample pretreatment but also the element measurement time generally does not exceed 10 min to have the accuracy of μg/g, which can greatly reduce the time and cost of detection. Due to the limitations of the EDXRF instrument and measurement mechanism, it has low sensitivity to light elements in food, and the detection sensitivity varies with elements in food element analysis. For example, the detection sensitivity of Ca, Mg, Fe, Zn, Cu and other elements concerned by people is not high when the content is low, and the measurement accuracy is extremely dependent on the detector resolution. However, with the improvement of detector performance and algorithm optimization of EDXRF, the detection limit of this technology can reach 0.1 μg/g, the detection of trace elements has also been improved, which has made a new breakthrough in the field of food element detection. Therefore, this paper reviews that in recent 20 years, in order to overcome the various difficulties of EDXRF in food detection, the hardware optimization of EDXRF (For example, the development of an analyzer without sample preparation can greatly reduce the time required for the detection of food elements, and a series of instruments combined with EDXRF and cluster capillary technology can greatly improve the excitation efficiency of lighter elements in food. The spectrometer with a high‐resolution detector can improve the detection accuracy of target elements with low content in food) and in order to solve the problem of spectrum resolution in food detection, (For example, the wavelet transform method which has good performance in spectrum smoothing, identifying weak peaks and maintaining peak shape is applied to EDXRF spectrum resolution, which can better solve the problem that the X‐ray characteristic peaks of elements with a low atomic number in food are submerged) the reform and innovation of spectrum resolution methods are introduced. This paper summarizes and analyzes the representative application examples of EDXRF in food safety detection, discusses the advantages and disadvantages of EDXRF compared with other rapid detection or food detection methods in different situations, concludes its application conditions, and discusses the application prospect of EDXRF technology in the field of food detection.

FPGA Implementation of a Hardware Optimized Automatic Target Detection and Classification Algorithm for Hyperspectral Image Analysis

In hyperspectral image analysis one of the most important tasks is target detection, requiring the execution of algorithms with high computational complexity. Recently, research efforts have focused on on-board real-time target detection to provide timely responses for swift decisions. Therefore, it is necessary to use a technology that provides the performance needed for real-time target detection, and at the same time meets the satellite payload requirements. Field-programmable gate arrays (FPGAs) have very interesting properties in terms of performance, size and power consumption, which have become the standard option for on-board processing. In this letter, we present a hardware optimized implementation for FPGAs of the automatic target detection and classification algorithm (ATDCA) using the Gram&#x2013;Schmidt (GS) method for orthogonalization purposes. The ATDCA-GS algorithm is directly coded using VHDL and verified on a Virtex-7 XC7VX690T FPGA using real hyperspectral data (collected by Hyperspectral Digital Imagery Collection Experiment (HYDICE) sensor and by NASA&#x2019;s Airborne Visible/Infrared Imaging Spectrometer (AVIRIS)) and a synthetic image. Experimental results demonstrate that our hardware version of the ATDCA-GS algorithm outperforms previous implementations (multicore processors, GPUs and accelerators) in both computation time (obtaining real-time performance) and power consumption, demonstrating the suitability of FPGAs for this purpose.

Characterizing and Understanding Distributed GNN Training on GPUs

Graph neural network (GNN) has been demonstrated to be a powerful model in many domains for its effectiveness in learning over graphs. To scale GNN training for large graphs, a widely adopted approach is distributed training which accelerates training using multiple computing nodes. Maximizing the performance is essential, but the execution of distributed GNN training remains preliminarily understood. In this work, we provide an in-depth analysis of distributed GNN training on GPUs, revealing several significant observations and providing useful guidelines for both software optimization and hardware optimization.

Exploiting Hardware and Software Advances for Quadratic Models of Wind Farm Layout Optimization

A key aspect of the design of a wind farm is the wind farm layout optimization (WFLO) problem: given a wind farm site and information about the wind patterns, the problem is to decide the location of individual wind turbines to maximize energy production subject to proximity restrictions and wake-based interference between turbines. Given the pairwise wake interactions, it is natural to model the energy objective as a quadratic function as, indeed, has been done in some existing optimization approaches. However, state-of-the-art solutions often trade-off between speed in producing designs and quality in terms of finding and proving optimal solutions. In this work, we aim to find a balanced approach to obtain WFLO solutions quickly for interactive design and solve the problem to optimality when quality is more important. To this end, we exploit recent advances in optimization hardware and software that target quadratic constraints: commercial mixed integer linear solvers have been extended to address some quadratic problems and nascent specialized hardware, including quantum computing systems, have focused on solving quadratic unconstrained binary optimization (QUBO) problems. We introduce two novel quadratic programming models for WFLO: a quadratic constrained optimization problem (QCOP) with binary decision variables and a QUBO. A thorough numerical evaluation using a commercial solver and specialized QUBO hardware show that our quadratic framework achieves fast, high-quality solutions that improve the state of the art and strike a balance between speed and quality. In particular, the QUBO model delivers high quality solutions in a few seconds while the QCOP model can be used to find better solutions and provide quality guarantees over a longer run-time.

MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures

Despite the promising future of near-bank computing to address the ”memory wall”, there are still critical hardware and software challenges, such as designing compute logics within a stringent area budget and developing software support for efficient data mapping. An open-source simulation framework plays an important role in addressing these challenges, which is unfortunately missing. In this paper, we introduce our open-source simulator for in-DRAM near-bank processing accelerators, MPU-Sim, to complete this missing piece in the research and development of future near-bank processing solutions. We detail the design, implementation, and interface of MPU-Sim, and conduct calibration studies for key hardware components with state-of-the-art simulators to validate our implementations. Finally, we use MPU-Sim for two case studies, DRAM refreshing and thread-block scheduling, to demonstrate the potential usage of MPU-Sim to study hardware and software optimizations for near-bank processing architectures.