MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures

Abstract

Despite the promising future of near-bank computing to address the ”memory wall”, there are still critical hardware and software challenges, such as designing compute logics within a stringent area budget and developing software support for efficient data mapping. An open-source simulation framework plays an important role in addressing these challenges, which is unfortunately missing. In this paper, we introduce our open-source simulator for in-DRAM near-bank processing accelerators, MPU-Sim, to complete this missing piece in the research and development of future near-bank processing solutions. We detail the design, implementation, and interface of MPU-Sim, and conduct calibration studies for key hardware components with state-of-the-art simulators to validate our implementations. Finally, we use MPU-Sim for two case studies, DRAM refreshing and thread-block scheduling, to demonstrate the potential usage of MPU-Sim to study hardware and software optimizations for near-bank processing architectures.