Hardware Non-idealities Research Articles

Passive Beamforming for Practical RIS-Assisted Communication Systems With Non-Ideal Hardware

Passive Beamforming for Practical RIS-Assisted Communication Systems With Non-Ideal Hardware

RSMA-aided satellite-aerial-vehicle integrated networks: Secrecy performance evaluation with non-ideal hardware

RSMA-aided satellite-aerial-vehicle integrated networks: Secrecy performance evaluation with non-ideal hardware

Resource allocation for practical phase shift STAR-RIS enabled MISO-NOMA wireless network with non ideal hardware

This study investigates the sum secrecy rate SRsum of a simultaneous transmission and reflection reconfigurable intelligent surface (STAR-RIS)-enabled multiple input single-output (MISO) non-orthogonal multiple access (NOMA) downlink network with non-ideal hardware defects (HWDs) at the transceivers. Earlier STAR-RIS studies assumed an ideal phase shift model, with each element reflect and transmit the signal without regard to its phase shift. The proposed practical phase shift model accounts for the phase-dependent amplitude variation in the reflection and transmission (RAT) coefficients. The goal is to maximize the SRsum through an alternating optimization (AO) iterative algorithm, leverages a classical semidefinite relaxation (SDR) for beamformer vector design (BVD), and employs an interior point method (IPM) to calculate NOMA power allocation factors αt,αr. The analysis focuses on the evaluation of the SRsum in scenarios with eavesdroppers, under the consideration of both ideal and practical phase shift cases. The study examines the impact of different non-ideal HWDs on the SRsum of the system and provides insights into vulnerabilities and limitations arising from these effects.

Threshold learning algorithm for memristive neural network with binary switching behavior

On-chip learning is an effective method for adjusting artificial neural networks in neuromorphic computing systems by considering hardware intrinsic properties. However, it faces challenges due to hardware nonidealities, such as the nonlinearity of potentiation and depression and limitations on fine weight adjustment. In this study, we propose a threshold learning algorithm for a variation-tolerant ternary neural network in a memristor crossbar array. This algorithm utilizes two tightly separated resistance states in memristive devices to represent weight values. The high-resistance state (HRS) and low-resistance state (LRS) defined as read current of < 0.1 μA and > 1 μA, respectively, were successfully programmed in a 32 × 32 crossbar array, and exhibited half-normal distributions due to the programming method. To validate our approach experimentally, a 64 × 10 single-layer fully connected network were trained in the fabricated crossbar for an 8 × 8 MNIST dataset using the threshold learning algorithm, where the weight value is updated when a gradient determined by backpropagation exceeds a threshold value. Thanks to the large margin between the two states of the memristor, we observed only a 0.42 % drop in classification accuracy compared to the baseline network results. The threshold learning algorithm is expected to alleviate the programming burden and be utilized in variation-tolerant neuromorphic architectures.

Gem5-NVDLA: A Simulation Framework for Compiling, Scheduling and Architecture Evaluation on AI System-on-Chips

Recent years have seen an increasing trend in designing AI accelerators together with the rest of the system, including CPUs and memory hierarchy. This trend calls for high-quality simulators or analytical models that enable such kind of co-exploration. Currently, the majority of such exploration is supported by AI accelerator analytical models. But such models usually overlook the non-trivial impact of congestion of shared resources, non-ideal hardware utilization and non-zero CPU scheduler overhead, which could only be modeled by cycle-level simulators. However, most simulators with full-stack toolchains are proprietary to corporations, and the few open-source simulators are suffering from either weak compilers or limited space of modeling. This framework resolves these issues by proposing a compilation and simulation flow to run arbitrary Caffe neural network models on the NVIDIA Deep Learning Accelerator (NVDLA) with gem5, a cycle-level simulator, and by adding more building blocks including scratchpad allocation, multi-accelerator scheduling, tensor-level prefetching mechanisms and a DMA-aided embedded buffer to map workload to multiple NVDLAs. The proposed framework has been tested and verified on a set of convolution neural networks, showcasing the capability of modeling complex buffer management strategies, scheduling policies and hardware architectures. As a case study of this framework, we demonstrate the importance of adopting different buffering strategies for activation and weight tensors in AI accelerators to acquire remarkable speedup.

A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects.

A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector-matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.

Enhancing Robustness of Memristor Crossbar‐Based Spiking Neural Networks against Nonidealities: A Hybrid Approach for Neuromorphic Computing in Noisy Environments

Memristor crossbar‐based spiking neural networks (SNNs) face challenges caused by nonidealities associated with their hardware‐based neurons and synapses. The key nonidealities include electric‐field noise, conductance noise, and conductance drift. This study investigates the robustness of fully connected, convolutional, residual, and spike‐timing‐dependent plasticity‐based SNNs against hardware nonidealities using the MNIST, Fashion MNIST, and CIFAR10 datasets. In response to these challenges, a novel hybrid residual SNN (HRSNN) is proposed that incorporates a new neuron circuit and a weight‐dependent loss function. The HRSNN in a high‐intensity noise environment is evaluated using the neuromorphic DVS128 Gesture dataset. The achieved accuracy rate of 92.71% is only 2.15% lower than that of the noise‐free environment. These results demonstrate the robustness of the proposed HRSNN under high‐intensity noise conditions and present new possibilities for the advancement of neuromorphic computing in noisy environments.

On the Performance of the UAV RIS-Assisted Dual-Hop PLC-RF Systems

In this work, we propose an unmanned aerial vehicle (UAV)-based reconfigurable intelligent surface (RIS)-assisted dual-hop power line communication and radio frequency (PLC-RF) system, in which a UAV-based RIS (URIS) located in the sky forwards signals from the relay to the terrestrial user. More specifically, we assume that the PLC channel suffers from a log-normal distribution, and the URIS-assisted RF link follows the Rician distribution. With the amplify-and-forward (AF) and decode-and-forward (DF) relaying models, the closed-form expressions for the outage probability and average bit-error-rate are derived. In addition, by taking into account the hardware impairments, the outage probability of the non-ideal hardware system is derived. Finally, the Monte Carlo simulation verifies the analytical results, which demonstrates the effect of impulsive noise and the number of the reflecting surface units on the system performance.

DT2CAM: A Decision Tree to Content Addressable Memory Framework

Decision trees are powerful tools for data classification. Accelerating the decision tree search is crucial for on-the-edge applications with limited power and latency budget. In this paper, we propose a content-addressable memory compiler for decision tree inference acceleration. We propose a novel ”adaptive-precision” scheme that results in a compact implementation and enables an efficient bijective mapping to ternary content addressable memories while maintaining high inference accuracies. We also develop a resistive-based functional synthesizer to map the decision tree to resistive content addressable memory arrays and perform functional simulations for energy, latency, and accuracy evaluations. We study the decision tree accuracy under hardware non-idealities including device defects, manufacturing variability, and input encoding noise. We test our framework on various decision tree datasets including <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Give Me Some Credit</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Titanic</i> , and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">COVID-19</i> . Our results reveal up to 42.4% energy savings and up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$17.8\times$</tex-math></inline-formula> better energy-delay-area product compared to the state-of-art hardware accelerators, and up to 333 million decisions per sec for the pipelined implementation.

Residual Transceiver Impairments Aware Expectation Propagation Algorithm Receiver for PDMA Systems

Pattern division multiple access (PDMA) is a promising non-orthogonal multiple access technology for the next generation wireless communication systems. In PDMA systems, the inherent residual transceiver impairments introduced by nonideal hardwares incur significant performance degradation. In this paper, we propose a residual-transceiver-impairments-aware (RTIA) expectation propagation algorithm (EPA) receiver to mitigate the detrimental influences of the nonideal hardware imperfections for uplink PDMA systems. The user-specific transmitter distortion powers are considered in the message passing procedure of the EPA detection. The parallel interference cancellation (PIC) scheme is incorporated into the proposed RTIA-EPA receiver to further improve the system performance and reduce the computational complexity. Simulation results illustrate that the proposed RTIA-EPA and RTIA-EPA-PIC receivers achieve significant performance gains over the conventional residual-transceiver-impairments-agnostic counterparts with negligible computational complexity overhead.

A Binary-Activation, Multi-Level Weight RNN and Training Algorithm for ADC-/DAC-Free and Noise-Resilient Processing-in-Memory Inference With eNVM

We propose a new algorithm for training neural networks with binary activations and multi-level weights, which enables efficient processing-in-memory circuits with embedded nonvolatile memories (eNVM). Binary activations obviate costly DACs and ADCs. Multi-level weights leverage multi-level eNVM cells. Compared to existing algorithms, our method not only works for feed-forward networks (e.g., fully-connected and convolutional), but also achieves higher accuracy and noise resilience for recurrent networks. In particular, we present an RNN-based trigger-word detection PIM accelerator, with detailed hardware noise models and circuit co-design techniques, and validate our algorithm's high inference accuracy and robustness against a variety of real hardware non-idealities.

Integrated Satellite Multiple Two-Way Relay Networks: Secrecy Performance Under Multiple Eves and Vehicles With Non-Ideal Hardware

In this paper, we study the secrecy performance for an integrated satellite multiple two-way terrestrial relay network, where the non-ideal hardware, multiple vehicle eavesdroppers and multiple legitimate vehicle users are applied in the considered networks. To derive better secrecy performance, opportunistic terrestrial selection scheme is considered for the networks. Besides, the colluding eavesdropping scheme is also considered, where all the vehicle eaves work together to overhear the information. On these foundations, the closed-form expression for the secrecy outage probability is gotten. To obtain the further insights of system parameters and channel parameters in high signal-to-noise ratio regime, the asymptotic investigations for the secrecy outage probability is also investigated. At last, Monte Carlo results are given to show the efficiency and correctness of the analytical results.

Evaluating RF Hardware Characteristics for Automotive JCRS Systems Based on PMCW-CDMA at 77GHz

Joint communications and radar sensing (JCRS) applications are currently being hailed as the innovation of the next generation of mobile communications. The combination of communications and sensor technology on one hardware platform offers various advantages, such as significant savings in space and costs. The two technologies are no longer being optimized and developed side by side, as has been the case in the past, but jointly. The physical channel is used by both simultaneously, including the transmitter and receiver structures, which must be optimized for the combined application. This inevitably leads to an influence on the performance of both systems. In this work, this influence is considered and analyzed with respect to the effects of the radio frequency components. For this purpose, our previously published code-division multiple access (CDMA)-based and vehicle-to-vehicle-focused model is extended to a JCRS model and evaluated according to the achieved bit error rate as well as the mean deviation of the detected distance and velocity in Simulink. The influence of the non-ideal hardware components (mixers, power amplifier, low noise amplifier, filter, antenna) and characteristics (S-parameters, non-linearity of the amplifiers and the noise) on the sensing and communications are analyzed and compared in this automotive context. The results reveal that the noise of the low noise amplifier at the receiver side has the most decisive influence. In contrast, the noise generated by the power amplifier at the transmitter has no effect due to the relatively high signal power. The non-linearity of amplifiers at the transmitter also significantly impacts the available sensing range by limiting and compressing signal power. Besides, the phase noise with a frequency offset higher than 10MHz can increase the communications and sensing error rate. In contrast, the influence of S-parameters is negligible, as the performance of communications and sensing is almost unchanged with different S-parameters. In the future, the proposed single-target scene will be further extended to a multi-target one.

Mixed THz/FSO Relaying Systems: Statistical Analysis and Performance Evaluation

In this paper, the performance of a mixed Terahertz/free-space optical (THz/FSO) wireless transmission system is studied, where the joint effects of channel fading and pointing errors are considered for both THz and FSO links. Employing the semi-blind amplify-and-forward protocol, we derive the cumulative distribution function and probability density function of the end-to-end signal-to-noise ratio. By applying the derived statistics, exact expressions for the outage probability (OP), average bit error rate (BER), and average channel capacity are obtained. In order to attain useful physical insights, asymptotic OP and average BER expressions are also presented. Based on them, the diversity gain is determined, which is shown to depend on channel fading and pointing errors of both links. In addition, by taking into account the hardware impairments, the OP of the non-ideal hardware system is derived. Moreover, the analysis is extended to multi-antenna scenarios and the asymptotic OP is obtained. Finally, illustrative numerical results are plotted and it can be observed that the path loss, channel fading, pointing errors and hardware impairments lead to a considerable degradation in system performance.

Phase Impairment Estimation for mmWave MIMO Systems with Low Resolutions ADC and Imperfect CSI

Multiple-Input Multiple-Output systems operating at millimeter wave band (mmWave MIMO) are a promising technology next generations of mobile networks. In practice, the non-ideal hardware is a challenge for commercially viable mmWave MIMO transceivers and come from non-linearities of the amplifier, phase noise, quantization errors, mutual coupling between antenna ports, and In-phase/Quadrature (I/Q) imbalance. As a result, the received signals are affected by non-ideal transceiver hardware components, thus reduce the performance of such systems, especially phase impairment caused by phase noise and carrier frequency offset (CFO). In this paper, we consider a mmWave MIMO system model that takes into account many practical hardware impairments and imperfect channel state information (CSI). Our main contributions are a problem formulation of phase impairments with imperfect CSI and a low-complexity estimation method to solve the problem. Numerical results are provided to evaluate the performance of the proposed algorithm.

On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars

Applications based on deep neural networks (DNNs) have grown exponentially in the past decade. To match their increasing computational needs, several nonvolatile memory (NVM) crossbar-based accelerators have been proposed. Recently, researchers have shown that apart from improved energy efficiency and performance, such approximate hardware also possess intrinsic robustness for defense against adversarial attacks. Prior works have focused on quantifying this intrinsic robustness for vanilla networks, that is DNNs trained on unperturbed inputs. However, adversarial training of DNNs, i.e., training with adversarially perturbed images, is the benchmark technique for robustness, and sole reliance on intrinsic robustness of the hardware may not be sufficient. In this work, we explore the design of robust DNNs through the amalgamation of adversarial training and the intrinsic robustness offered by NVM crossbar-based analog hardware. First, we study the noise stability of such networks on unperturbed inputs and observe that internal activations of adversarially trained networks have lower signal-to-noise ratio (SNR), and are sensitive to noise compared to vanilla networks. As a result, they suffer significantly higher performance degradation due to the approximate computations on analog hardware; on an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> accuracy drop. Noise stability analyses clearly show the instability of adversarially trained DNNs. On the other hand, for adversarial images generated using Square Black Box attacks, ResNet-10/20 adversarially trained on CIFAR-10/100 display a robustness improvement of 20%–30% under high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{\mathrm{ attack}}$ </tex-math></inline-formula> (degree of input perturbation). For adversarial images generated using projected-gradient-descent (PGD) White-Box attacks, the adversarially trained DNNs present a 5%–10% gain in robust accuracy due to the underlying NVM crossbar when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{\mathrm{ attack}}$ </tex-math></inline-formula> is greater than the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">epsilon</i> of the adversarial training ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{\mathrm{ train}}$ </tex-math></inline-formula> ). Our results indicate that implementing adversarially trained networks on analog hardware requires careful calibration between hardware nonidealities and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{\mathrm{ train}}$ </tex-math></inline-formula> to achieve optimum robustness and performance.

Quantization and sparsity-aware processing for energy-efficient NVM-based convolutional neural networks

Nonvolatile memory (NVM)-based convolutional neural networks (NvCNNs) have received widespread attention as a promising solution for hardware edge intelligence. However, there still exist many challenges in the resource-constrained conditions, such as the limitations of the hardware precision and cost and, especially, the large overhead of the analog-to-digital converters (ADCs). In this study, we systematically analyze the performance of NvCNNs and the hardware restrictions with quantization in both weight and activation and propose the corresponding requirements of NVM devices and peripheral circuits for multiply–accumulate (MAC) units. In addition, we put forward an in situ sparsity-aware processing method that exploits the sparsity of the network and the device array characteristics to further improve the energy efficiency of quantized NvCNNs. Our results suggest that the 4-bit-weight and 3-bit-activation (W4A3) design demonstrates the optimal compromise between the network performance and hardware overhead, achieving 98.82% accuracy for the Modified National Institute of Standards and Technology database (MNIST) classification task. Moreover, higher-precision designs will claim more restrictive requirements for hardware nonidealities including the variations of NVM devices and the nonlinearities of the converters. Moreover, the sparsity-aware processing method can obtain 79%/53% ADC energy reduction and 2.98×/1.15× energy efficiency improvement based on the W8A8/W4A3 quantization design with an array size of 128 × 128.

Long Short-Term Memory Implementation Exploiting Passive RRAM Crossbar Array

The ever-increasing demand to extract temporal correlations across sequential data and perform context-based learning in this era of big data has led to the development of long short-term memory (LSTM) networks. Furthermore, there is an urgent need to perform these time-series data-dependent applications including speech/video processing and recognition, language modelling and translation, etc. on compact internet-of-things (IoT) edge devices with limited energy. To this end, in this work, for the first time, we propose an extremely area- and energy-efficient LSTM network implementation exploiting the passive resistive random access memory (RRAM) crossbar array. We developed a hardware-aware LSTM network simulation framework and performed an extensive analysis of the proposed LSTM implementation considering the non-ideal hardware artifacts such as spatial (device-to-device) and temporal variations, non-linearity, noise, etc. utilizing an experimentally calibrated comprehensive phenomenological model for passive RRAM crossbar array. Our results indicate that the proposed passive RRAM crossbar-based LSTM network implementation not only outperforms the prior digital and active 1T-1R crossbar-based LSTM implementations by more than three orders of magnitude in terms of area and two orders of magnitude in terms of training energy for identical network accuracy, but also exhibits robustness against spatial and temporal variations and noise, and a faster convergence rate. Our work may provide the incentive for experimental realization of LSTM networks on passive RRAM crossbar arrays.

Secrecy Analysis of NOMA-Based Integrated Satellite-Multiple UAV Networks under Nonideal Hardware and Colluding Scheme

This paper studies the secrecy outage probability (SOP) of nonorthogonal multiple access (NOMA)-based integrated satellite-multiple unmanned aerial vehicle networks (ISMUAVNs) under nonideal hardware and colluding scheme. Colluding scheme is defined as that the eavesdroppers cooperate with each other to overhear the legitimate users’ signals. On this foundation, we obtain the closed-form expression for the SOP for the considered NOMA-based ISMUAVNs along with the partial unmanned aerial vehicle (UAV) selection scheme. To gain more things in the high signal-to-noise ratio (SNR) regime, we derive the asymptotic expression for the SOP, which gives fast ways to evaluate the benefit of the NOMA scheme and the impact of nonideal hardware impairments on the SOP. Finally, Monte Carlo simulation results are provided to show the correctness of the analytical results. In addition, with the help of representative results, some important and interesting findings are obtained.

Full Physical Layer Simulation Tool to Design Future 77 GHz JCRS-Applications

Vehicular communication systems get more and more attention with the upcoming fifth and sixth generation. Hereby, the focus lies on the development of the co-design or co-existence of communications and sensing. So called joints communications and radar sensing systems are seen as one key technology of 6G. As joint systems will have shared waveforms and hardware platforms, there is a huge benefit in cost and space which is one essential argument for the automotive industry. However, to design such a system for new applications like platooning or intersection assistance a physical layer has to be set up to represent the real physical layer properly. The proposed system design closes the lack of such a simulation tool and allows for full physical layer simulations, including e.g. the hardware non-idealities and the channel model for 77GHz. The whole signal processing chain of the physical layer is built up and will be integrated in the higher layer state-of-the-art simulation frameworks like Veins or Artery in the next step. The communications design is developed in Simulink, whereas the sensing part is discussed. The proposed communications architecture covers several transmission approaches (serial, parallel), a CDMA based spreading, a radio frequency representation, the channel (simulated in a 3D-Ray-Tracing-tool) and the receiver structure (e.g. the synchronisation or the channel estimation). Several design criteria are discussed, like the serial or parallel design architecture, the maximum ratio combining or the phase and frequency compensation method. The whole system architecture is freely available (<uri>https://doi.org/10.5281/zenodo.6482565</uri>) and in consequence, the different signal blocks and parameters can be enabled or disabled for evaluations according to future design criteria requirements.