Hardware Implementation Of Neural Networks Research Articles

Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks

Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex NN models remains challenging because different tasks, such as feature extraction and classification, should be performed at different memory elements and arrays. This further increases the required number of memory arrays and chip size. Here, we propose a three-dimensional ferroelectric NAND (3D FeNAND) array for the area-efficient hardware implementation of NNs. Vector-matrix multiplication is successfully demonstrated using the integrated 3D FeNAND arrays, and excellent pattern classification is achieved. By allocating each array of vertical layers in 3D FeNAND as the hidden layer of NN, each layer can be used to perform different tasks, and the classification of color-mixed patterns is achieved. This work provides a practical strategy to realize high-performance and highly efficient NN systems by stacking computation components vertically.

Text classification in memristor-based spiking neural networks

Memristors, emerging non-volatile memory devices, have shown promising potential in neuromorphic hardware designs, especially in spiking neural network (SNN) hardware implementation. Memristor-based SNNs have been successfully applied in a wide range of applications, including image classification and pattern recognition. However, implementing memristor-based SNNs in text classification is still under exploration. One of the main reasons is that training memristor-based SNNs for text classification is costly due to the lack of efficient learning rules and memristor non-idealities. To address these issues and accelerate the research of exploring memristor-based SNNs in text classification applications, we develop a simulation framework with a virtual memristor array using an empirical memristor model. We use this framework to demonstrate a sentiment analysis task in the IMDB movie reviews dataset. We take two approaches to obtain trained SNNs with memristor models: (1) by converting a pre-trained artificial neural network (ANN) to a memristor-based SNN, or (2) by training a memristor-based SNN directly. These two approaches can be applied in two scenarios: offline classification and online training. We achieve the classification accuracy of 85.88% by converting a pre-trained ANN to a memristor-based SNN and 84.86% by training the memristor-based SNN directly, given that the baseline training accuracy of the equivalent ANN is 86.02%. We conclude that it is possible to achieve similar classification accuracy in simulation from ANNs to SNNs and from non-memristive synapses to data-driven memristive synapses. We also investigate how global parameters such as spike train length, the read noise, and the weight updating stop conditions affect the neural networks in both approaches. This investigation further indicates that the simulation using statistic memristor models in the two approaches presented by this paper can assist the exploration of memristor-based SNNs in natural language processing tasks.

Complex Dynamics, Hardware Implementation and Image Encryption Application of Multiscroll Memeristive Hopfield Neural Network With a Novel Local Active Memeristor

Because of the nonlinearity and memory, memristors are the most suitable electrical component for simulating synapses. A novel local active and nonvolatile memristor is designed. By circuit experiments, its memristive properties are verified. By introducing this memristor, this brief constructs a 4D memristive Hopfield neural network (MHNN) which can perform complex dynamics, such as controllable double-scrolls attractors and controllable initial offset boosting coexistence. Compared with other multiscroll chaotic systems, the autonomy equation of the system is smooth for discarding the sign function. In addition, this MHNN performs well in image encryption applications for the significant complexity of multiscroll. Through safety analysis, the information entropy of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$512 \times 512$ </tex-math></inline-formula> Lena graph is 7.9993, which is very close to the ideal value of 8. Besides, the number of pixels changing rates (NPCR) and the unified averaged changed intensity (UACI) are 99.6097% and 33.4621%, which are almost equal ideal values. Finally, this brief designs the digital circuit of the multiscroll MHNN signal generator and verifies the function with the help of a field programmable gate array (FPGA) and oscilloscope. Besides, by designing a pseudo-random number generation circuit, FPGA can directly encrypt the image and transmit it to the input and output devices.

Hybrid MTJ/CNTFET-Based Binary Synapse and Neuron for Process-in-Memory Architecture

This paper proposes a reliable integrated binary synapse and neurons for hardware implementation of binary neural networks. Thanks to the nonvolatile nature of the magnetic tunnel junction ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MTJ</b> ) and the unique features of the carbon nanotube field-effect transistor ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CNTFET</b> ), the proposed design in this paper does not require external memory to store weights and also consumes low static power. Also, due to the proposed circuit structure that did not use sequential parts, the proposed circuit is immune to soft error. Because in binary neural networks, weights are limited to two values of ‘-1’ and ‘1’, the occurrence of soft errors dramatically reduces the accuracy of the network. Simulation results indicate that the proposed design in this paper consumes at least 9% lower power, occupies 34% lower area, and offers a 49% lower power delay area product ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PDAP</b> ). Also, Monte-Carlo simulations have been performed to study the effect of the process variation on the network. The result of the Monte-Carlo simulations shows that the proposed neuron has no logical error in 10000 simulations. Consequently, the accuracy of the network utilizing by the proposed neuron is equal to the software-implemented network and does not decrease even in the presence of process variations.

BTBT Based LIF Junctionless FET Neuron With Plausible Mimicking Efficiency

Amid the quest for nanoscale devices to mimic the biological neuronal dynamics, this article demonstrates a SOI Junctionless Field Effect Transistor (JLFET) based leaky integrate and fire (LIF) neuron in sub-20 nm technology. The band-to-band-tunneling (BTBT) mechanism is considered to imitate the leaky-integration behavior. As JLFET has strongly doped channel that supports fully depletion in the OFF state with considerable band overlapping of channel and drain regions that is subsequently allowing the BTBT in lateral direction. Moreover, the proposed device based LIF neuron requires neither metallurgical junction nor back gate bias to induce the floating body to confine the excess carrier. And, it requires only 0.4 V of supply voltage, which is much lower compared to its equivalent bulk FinFET and PD-SOI MOSFET based LIF neurons and it shows a GHz range of spiking frequency i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 8 orders greater than biological neuron. Hence, it presumes that the proposed SOI JLFET based LIF neuron is more suitable for large scale hardware implementation of spiking neural network (SNN) due to its energy and area efficiency comparable with biological neuron along with CMOS compatibility.

Neuromorphic Electronic Module, focused on the Use of Memristor ECB, for Image Recognition

Currently, the expansion of the range of tasks solved by neural networks occurs mainly due to the complication of their structure, an increase in the number of neurons and synapses. Networks with thousands of neurons and tens to hundreds of thousands of synapses can achieve impressive results in the areas of speech processing, image identification, computer vision, etc., but at the same time, their use and training require significant computing power and energy costs. This is unacceptable for embedded autonomous systems, which, as follows from current trends, will constitute one of the most important applications for neural networks on a chip and must perform their tasks using a minimum number of elements and with minimal energy consumption. In this article a method for increasing the efficiency of hardware implementation and minimizing the number of electronic synaptic elements of asynchronous spiking neural networks (ASNN) in solving image identification problems was developed. To achieve this goal, a theoretical analysis of ASNN architectural solutions was carried out, the number of electronic synaptic elements was minimized due to the decomposition of the image identification problem, an ASNN software model was developed, neuron parameters were optimized and the neural network was learned (the weights of electronic synaptic elements were sat) on a software model. An ASNN electrical circuit was developed and the results of SPICE modeling were obtained. A hardware implementation of an asynchronous spiking neural network on serial electronic components was performed. The effectiveness of the proposed method was demonstrated in the process of optimizing the parameters of neurons and learning the neural network on the developed software model and confirmed by the results of SPICE modeling of the developed electrical circuit of the ASNN and the results of measuring the signals of the neural network implemented on serial electronic components.

ИСКУССТВЕННЫЕ НЕЙРОННЫЕ СЕТИ: БАЗОВЫЕ ПРИНЦИПЫ И ВОЗМОЖНЫЕ РЕАЛИЗАЦИИ

There are many tasks solved by people that can be partially or completely automated. One of the most prom- ising tools for these purposes are artificial neural networks. Neural networks are a technology at the intersection of many disciplines: physics, mathematics, statistics, computer science and technology. They find application in a wide range of tasks, such as time series analysis, regression analysis, pattern recognition in images, etc. It is im- possible not to note an important feature of neural networks: to learn from data both with the participation of a teacher, and to go through the learning process without a teacher. This article discusses the basic terms and basic principles of the functioning of artificial neural networks. At the beginning, a mathematical model of the operation of an artificial neuron is given. The main constituent elements of an artificial neuron, such as synapses, inputs, axons, etc., are described. Some subtleties in optimization processes are generalized, and the main types of activa- tion functions are given. Examples of software implementations of neural networks are given, specific application cases are considered, their strengths are noted, as well as some limitations. Given the limitations, an alternative technology is presented: hardware implementations of artificial neural networks. A brief description of the use of neural networks in the world is given, after which the classification of hardware implementations is considered. Each class highlights the features of using such technologies, including strengths and weaknesses. At the end of the article, the question of the relevance of the problem of finding an element base for building hardware solutions in the field of artificial neural networks is raised, arguments are given in favor of the development of hardware solutions. It is shown that it is necessary to further develop the element base for the construction of artificial neu- ral networks.

Neuromorphic Functional Modules of a Spiking Neural Network

In the current era, the design and development of artificial neural networks exploiting the architecture of the human brain have evolved rapidly. Artificial neural networks (ANN) effectively solve a wide range of common artificial-intelligence tasks involving data classification and recognition, prediction, forecasting and adaptive control of the behavior of an object. The biologically inspired underlying principles of ANN operation have certain advantages over the conventional von Neumann architecture including unsupervised learning, architectural flexibility and adaptability to environmental change and high performance under significantly reduced power consumption due to large parallel and asynchronous data processing. In this paper, we present a circuit design of main functional blocks (neurons and synapses) intended for the hardware implementation of a perceptron-based feedforward spiking neural network. As the third generation of artificial neural networks, spiking neural networks perform data processing utilizing spikes, which are discrete events (or functions) that take place at points in time. Neurons in spiking neural networks initiate precisely timed spikes and communicate with each other via spikes transmitted through synaptic connections or synapses with adaptable scalable weight. One of the prospective approaches to emulating synaptic behavior in hardware implemented spiking neural networks is to use nonvolatile-memory devices with analog conduction modulation (or memristive structures). Here we propose a circuit design for functional analogues of memristive structures to mimic synaptic plasticity, pre- and postsynaptic neurons which could be used for developing a circuit design of spiking-neural-network architectures with different training algorithms including the spike-timing-dependent-plasticity learning rule. Two different circuits of an electrical synapse are developed. The first one is an analog synapse with a photoresistor optocoupler used to ensure the tunable conductivity for synaptic-plasticity emulation. While the second one is a digital synapse, in which the synaptic weight is stored in a digital code with its direct conversion into conductivity (without a digital-to-analog converter and photoresistor optocoupler). The results of prototyping the developed circuits for electronic analogs of synapses, pre- and postsynaptic neurons and the study of transient processes are presented. The developed approach could provide a basis for the ASIC (application-specific integrated circuit) design of spiking neural networks based on CMOS (complementary metal—oxide–semiconductor) design technology.

Method for Convolutional Neural Network Hardware Implementation Based on a Residue Number System

Method for Convolutional Neural Network Hardware Implementation Based on a Residue Number System

Synaptic Activity and Hardware Footprint of Spiking Neural Networks in Digital Neuromorphic Systems

Spiking neural networks are expected to bring high resources, power, and energy efficiency to machine learning hardware implementations. In this regard, they could facilitate the integration of Artificial Intelligence in highly constrained embedded systems, such as image classification in drones or satellites. If their logic resource efficiency is widely accepted in the literature, their energy efficiency still remains debated. In this article, a novel high-level metric is used to characterize the expected energy efficiency gain when using Spiking Neural Networks (SNN) instead of Formal Neural Networks (FNN) for hardware implementation: Synaptic Activity Ratio (SAR). This metric is applied to a selection of classification tasks including images and 1D signals. Moreover, a high-level estimator for logic resources, power usage, execution time, and energy is introduced for neural network hardware implementations on FPGA, based on four existing accelerator architectures covering both sequential and parallel implementation paradigms for both spiking and formal coding domains. This estimator is used to evaluate the reliability of the Synaptic Activity Ratio metric to characterize spiking neural network energy efficiency gain on the proposed dataset benchmark. This study led to the conclusion that spiking domain offers significant power and energy savings in sequential implementations. This study also shows that synaptic activity is a critical factor that must be taken into account when addressing low-energy systems.

Li‐Ion‐Based Electrolyte‐Gated Transistors with Short Write‐Read Delay for Neuromorphic Computing

AbstractThe hardware implementation of artificial neural networks requires synaptic devices with linear and high‐speed weight modulation. Memristors as a candidate suffer from excessive write variation and asymmetric resistance modulation that inherently rooted in their stochastic mechanisms. Thanks to a controllable ion intercalation/deintercalation mechanism, electrolyte‐gated transistors (EGTs) hold prominent switching linearity and low write variation, and thus have been the promising alternative for synaptic devices. However, the operation frequency of EGTs is seriously limited by the time that is required for the state stabilization, that is, the write‐read delay after each set/reset operation. Here, a Li‐ion‐based EGT (Li‐EGT) with write‐read delay of 3 ms along with multistates, low energy consumption, and quasi‐linear weight update is introduced. The origin of the short write‐read delay of the device is attributed to the permeable interface between electrolyte and gate electrode. Leveraging the Li‐EGT characteristic, near‐ideal accuracy (≈94%) on handwritten digital image data set has been achieved by the corresponding neural network simulation. These results provide an insight into the development of Li‐EGTs for high‐speed neuromorphic computing.

Recent Progress of Neuromorphic Computing Based on Silicon Photonics: Electronic–Photonic Co-Design, Device, and Architecture

The rapid development of neural networks has led to tremendous applications in image segmentation, speech recognition, and medical image diagnosis, etc. Among various hardware implementations of neural networks, silicon photonics is considered one of the most promising approaches due to its CMOS compatibility, accessible integration platforms, mature fabrication techniques, and abundant optical components. In addition, neuromorphic computing based on silicon photonics can provide massively parallel processing and high-speed operations with low power consumption, thus enabling further exploration of neural networks. Here, we focused on the development of neuromorphic computing based on silicon photonics, introducing this field from the perspective of electronic–photonic co-design and presenting the architecture and algorithm theory. Finally, we discussed the prospects and challenges of neuromorphic silicon photonics.

Analog Memristor of Lead‐Free Cs4CuSb2Cl12 Layered Double Perovskite Nanocrystals as Solid‐State Electronic Synapse for Neuromorphic Computing

AbstractBrain‐inspired artificial neural networks and neuromorphic computing are taking space to a new height based on solid‐state memristor devices. Despite considerable progress already made, the use of lead‐free double perovskite materials with direct bandgap can be recognized as a significant paradigm shift in this field. Here, growth, thin film deposition, and analog electroforming‐free resistive switching property along with promising artificial synaptic and neural activities of lead‐free layered cesium copper antimony chloride (Cs4CuSb2Cl12 or CCAC) double perovskite nanocrystals are reported. Optical and structural characterizations of CCAC microcrystals (MCs) and nanocrystals (NCs) confirm the growth, the existence of direct bandgap, and &lt;111&gt; oriented monoclinic crystal phase of space group C2/m. Interestingly, both the MCs and NCs display an almost equal bandgap of 1.1 eV in thin film even though they have higher bandgaps of 1.3 and 2.2 eV in dispersion, respectively. However, devices of NC thin film exhibit superior memristor behavior along with emulation of various synaptic and neural activities due to having less number of defects. Finally, the analog modulation of synaptic weight using CCAC memristor, in terms of postsynaptic currents, during potentiation and depression represents a significant achievement toward hardware implementation of neural networks and neuromorphic computing.

An organic synaptic circuit: toward flexible and biocompatible organic neuromorphic processing

In the nervous system synapses play a critical role in computation. In neuromorphic systems, biologically inspired hardware implementations of spiking neural networks, electronic synaptic circuits pass signals between silicon neurons by integrating pre-synaptic voltage pulses and converting them into post-synaptic currents, which are scaled by the synaptic weight parameter. The overwhelming majority of neuromorphic systems are implemented using inorganic, mainly silicon, technology. As such, they are physically rigid, require expensive fabrication equipment and high fabrication temperatures, are limited to small-area fabrication, and are difficult to interface with biological tissue. Organic electronics are based on electronic properties of carbon-based molecules and polymers and offer benefits including physical flexibility, low cost, low temperature, and large-area fabrication, as well as biocompatibility, all unavailable to inorganic electronics. Here, we demonstrate an organic differential-pair integrator synaptic circuit, a biologically realistic synapse model, implemented using physically flexible complementary organic electronics. The synapse is shown to convert input voltage spikes into output current traces with biologically realistic time scales. We characterize circuit’s responses based on various synaptic parameters, including gain and weighting voltages, time-constant, synaptic capacitance, and circuit response due to inputs of different frequencies. Time constants comparable to those of biological synapses and the neurons are critical in processing real-world sensory signals such as speech, or bio-signals measured from the body. For processing even slower signals, e.g., on behavioral time scales, we demonstrate time constants in excess of two seconds, while biologically plausible time constants are achieved by deploying smaller synaptic capacitors. We measure the circuit synaptic response to input voltage spikes and present the circuit response properties using custom-made circuit simulations, which are in good agreement with the measured behavior.

Frequency-Dependent Synapse Weight Tuning in 1S1R with a Short-Term Plasticity TiOx-Based Exponential Selector.

Short-term plasticity (STP) is an important synaptic characteristic in the hardware implementation of artificial neural networks (ANN), as it enables the temporal information processing (TIP) capability. However, the STP feature is rather challenging to reproduce from a single nonvolatile resistive random-access memory (RRAM) element, as it requires a certain degree of volatility. In this work, a Pt/TiOx/Pt exponential selector is introduced not only to suppress the sneak current but also to enable the TIP feature in a one selector-one RRAM (1S1R) synaptic device. Our measurements reveal that the exponential selector exhibits the STP characteristic, while a Pt/HfOx/Ti RRAM enables the long-term memory capability of the synapse. Thereafter, we experimentally demonstrated pulse frequency-dependent multilevel switching in the 1S1R device, exhibiting the TIP capability of the developed 1S1R synapse. The observed STP of the selector is strongly influenced by the bottom metal-oxide interface, in which Ar plasma treatment on the bottom Pt electrode resulted in the annihilation of the STP feature in the selector. A mechanism is thus proposed to explain the observed STP, using the local electric field enhancement induced at the metal-oxide interface coupled with the drift-diffusion model of mobile O2- and Ti3+ ions. This work therefore provides a reliable means of producing the STP feature in a 1S1R device, which demonstrates the TIP capability sought after in hardware-based ANN.

Improving HfO2-Based Resistive Switching Devices by Inserting a TaOx Thin Film via Engineered In Situ Oxidation

Resistive switching (RS) devices with binary and analogue operation are expected to play a key role in the hardware implementation of artificial neural networks. However, state of the art RS devices based on binary oxides (e.g., HfO2) still do not exhibit enough competitive performance. In particular, variability and yield still need to be improved to fit industrial requirements. In this study, we fabricate RS devices based on a TaOx/HfO2 bilayer stack, using a novel methodology that consists of the in situ oxidation of a Ta film inside the atomic layer deposition (ALD) chamber in which the HfO2 film is deposited. By means of X-ray reflectivity (XRR) and time-of-flight secondary ion mass spectrometry (ToF-SIMS), we realized that the TaOx film shows a substoichiometric structure, and that the TaOx/HfO2 bilayer stack holds a well-layered structure. An exhaustive electrical characterization of the TaOx/HfO2-based RS devices shows improved switching performance compared to the single-layer HfO2 counterparts. The main advantages are higher forming yield, self-compliant switching, lower switching variability, enhanced reliability, and better synaptic plasticity.

Molecular ferroelectric/semiconductor interfacial memristors for artificial synapses

With the burgeoning developments in artificial intelligence, hardware implementation of artificial neural network is also gaining pace. In this pursuit, ferroelectric devices (i.e., tunneling junctions and transistors) with voltage thresholds were recently proposed as suitable candidates. However, their development is hindered by the inherent integration issues of inorganic ferroelectrics, as well as poor properties of conventional organic ferroelectrics. In contrast to the conventional ferroelectric synapses, here we demonstrated a two-terminal ferroelectric synaptic device using a molecular ferroelectric (MF)/semiconductor interface. The interfacial resistance can be tuned via the polarization-controlled blocking effect of the semiconductor, owing to the high ferroelectricity and field amplification effect of the MF. Typical synaptic features including spike timing-dependent plasticity are substantiated. The introduction of the semiconductor also enables the attributes of optoelectronic synapse and in-sensor computing with high image recognition accuracies. Such interfaces may pave the way for the hardware implementation of multifunctional neuromorphic devices.

Connectome of memristive nanowire networks through graph theory

Hardware implementation of neural networks represents a milestone for exploiting the advantages of neuromorphic-type data processing and for making use of the inherent parallelism associated with such structures. In this context, memristive devices with their analogue functionalities are called to be promising building blocks for the hardware realization of artificial neural networks. As an alternative to conventional crossbar architectures where memristive devices are organized with a top-down approach in a grid-like fashion, neuromorphic-type data processing and computing capabilities have been explored in networks realized according to the principle of self-organization similarity found in biological neural networks. Here, we explore structural and functional connectivity of self-organized memristive nanowire (NW) networks within the theoretical framework of graph theory. While graph metrics reveal the link of the graph theoretical approach with geometrical considerations, results show that the interplay between network structure and its capacity to transmit information is related to a phase transition process consistent with percolation theory. Also the concept of memristive distance is introduced to investigate activation patterns and the dynamic evolution of the information flow across the network represented as a memristive graph. In agreement with experimental results, the emergent short-term dynamics reveals the formation of self-selected pathways with enhanced transport characteristics connecting stimulated areas and regulating the trafficking of the information flow. The network capability to process spatio-temporal input signals can be exploited for the implementation of unconventional computing paradigms in memristive graphs that take into advantage the inherent relationship between structure and functionality as in biological systems.

A Multifault‐Tolerant Training Scheme for Nonideal Memristive Neural Networks

Memristor crossbar is extensively investigated as an energy‐efficient accelerator for neural network (NN) computations. However, hardware implementation of NNs using realistic memristors is challenging due to the ubiquity of faults (mainly classified into hard and soft faults) in memristors. Herein, a hardware‐friendly, low‐power multifault‐tolerant training (MFTT) scheme capable of addressing both hard and soft faults simultaneously for memristive NNs is proposed. The MFTT scheme consists of multifault detection, targeted weight pruning, and in situ training with the Manhattan update rule. Specifically, multifault detection is first conducted to detect both hard and large soft faults. The detected faulty weights are subsequently pruned to prevent them from disturbing the NN. The sparsified NN after pruning is in situ trained so that the hard and large soft faults can be effectively tolerated using the sparsity and self‐adaptivity of NNs. In addition, the remaining small soft faults can be well tolerated by the Manhattan update rule. Experimentally, MFTT demonstrates the lowest accuracy losses among several representative fault‐tolerant schemes not only in the hard fault‐only (when the hard fault ratio exceeds 10%) and soft fault‐only (when the soft faults are large) cases, but also in the case where both types of faults coexist.

Linear and Symmetric Li-Based Composite Memristors for Efficient Supervised Learning.

Emerging energy-efficient neuromorphic circuits are based on hardware implementation of artificial neural networks (ANNs) that employ the biomimetic functions of memristors. Specifically, crossbar array memristive architectures are able to perform ANN vector-matrix multiplication more efficiently than conventional CMOS hardware. Memristors with specific characteristics, such as ohmic behavior in all resistance states in addition to symmetric and linear long-term potentiation/depression (LTP/LTD), are required in order to fully realize these benefits. Here, we demonstrate a Li-based composite memristor (LCM) that achieves these objectives. The LCM consists of three phases: Li-doped TiO2 as a Li reservoir, Li4Ti5O12 as the insulating phase, and Li7Ti5O12 as the metallic phase, where resistive switching correlates with the change in the relative fraction of the metallic and insulating phases. The LCM exhibits a symmetric and gradual resistive switching behavior for both set and reset operations during a full bias sweep cycle. This symmetric and linear weight update is uniquely enabled by the symmetric bidirectional migration of Li ions, which leads to gradual changes in the relative fraction of the metallic phase in the film. The optimized LCM in ANN simulation showed that exceptionally high accuracy in image classification is realized in fewer training steps compared to the nonlinear behavior of conventional memristors.