Hardware Implementation Scheme Research Articles

An Efficient Parallel CRC Computing Method for High Bandwidth Networks and FPGA Implementation

A cyclic redundancy check (CRC) is a widely used technique in data communication for detecting data transmission errors. However, existing FPGA-based parallel CRC hardware implementation schemes often face problems of excessive resource utilization and timing convergence difficulties in high-bandwidth networks. In addition, these problems are further exacerbated by the variable length of the end of the checksum data frame during data transmission. To address these challenges, this paper proposes a parallel CRC computation method based on precomputed seed values for bit-width normalization (named PSV-WN-CRC). The algorithm selects the corresponding primitive seed value according to the length of the data frame tail and converts the CRC computation with arbitrary bit-width to the CRC computation with fixed bit-width, thus adapting to the case of the indefinite length of the data frame tail. Based on this algorithm, this paper designs an efficient parallel CRC circuit on FPGA to reduce the consumption of resources. The experimental results show that the CRC algorithm and circuit proposed in this paper implemented on Virtex UltraScale+ FPGAs with 1024-bit wide CRC consumes only 5981 LUTs and achieves a maximum throughput of 392.2 Gbps. The method effectively reduces the resource consumption and improves the maximum throughput as compared to three advanced works.

Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection

Long-term and effective detection of epileptic seizures is a crucial aspect of epilepsy monitoring and treatment. Addressing the resource overhead issue of wearable epilepsy detection devices, this paper proposes a lightweight hardware implementation scheme for epilepsy detection based on a reusable architecture empirical mode decomposition (EMD) and K-Nearest Neighbors (KNN). Firstly, EMD is used to extract epileptic features from electroencephalogram (EEG), optimized through a reusable architecture design and sawtooth transform to reduce hardware resource usage. Subsequently, a KNN classifier with similarity judgment mechanism is designed to improve the recognition efficiency. Implemented on TSMC 65 nm process, the circuit area is 1.91 mm2, operates at 1 V and 20 MHz, with a power consumption of 4.034 mW. Evaluation on the Bonn EEG dataset yielded a classification accuracy of 96 %, sensitivity of 98 %, and a single detection delay of 1.51 ms. The hardware design offers a simple structure, high accuracy, and low resource consumption, making it suitable for wearable epilepsy detection devices.

Application of Quasi-Continuous Waveform Coding in Spaceborne Synthetic Aperture Radar

Quasi-continuous wave radar is an attempt to give consideration to the performance of pulse and continuous wave radar signals. However, it also has the shortcomings of both. This paper aims to add a new quasi-continuous-wave coding method to the spaceborne synthetic aperture radar (SAR) system. The technology of improving spaceborne SAR imaging performance by coding quasi-continuous-wave pulses is studied, and some shortcomings of this algorithm are improved. Firstly, the application of quasi-continuous-wave radar in the SAR system is studied, and the coding and reconstruction scheme is provided so that this technology can be successfully applied in spaceborne SAR. Secondly, the effects of different quasi-continuous-wave coding methods on SAR imaging performance are evaluated, including signal-to-noise ratio, resolution, and integration time. Then, several coding schemes are given, and the characteristic changes of the signal after quasi-continuous-wave coding are analyzed. The transmit–receive conversion loss function and azimuth Doppler ambiguity function of the design scheme are analyzed, which proves the advantages of the scheme. Finally, we design the hardware implementation scheme and carry out the practical test.

The grid simulation device for photovoltaic power generation

Solar photovoltaic power generation is the solar radiant energy directly into electricity method, namely the sun radiant energy by solar cells is converted into electrical energy, again through energy storage, control, and transformation, and into people’s dc or ac power that can be used directly. The so-called grid-connected network is simply said to be realized by using the principle of simultaneous operation of voltage, phase, phase sequence, and frequency. The simulation device of its inverter grid-connected is designed, the scheme of simulating grid-connected is given, the drive control system and filter system are designed, and the implementation scheme of the drive control system is introduced in detail. The design and parameter selection of the main circuit and the filter system are given in detail. The hardware and software implementation scheme and circuit structure of the system are given based on DSP. The entire system can meet the requirements of microgrid simulation operation.

FPGA Implementation for Finite-Time and Fixed-Time Neurodynamic Algorithms in Constrained Optimization Problems

In this paper, two neurodynamic algorithms and the corresponding Field-Programmable-Gate-Array (FPGA) implementation scheme are presented, respectively. Firstly, based on Lagrange programming neural networks (LPNN) and sliding mode control technique, an algorithm with finite-time convergence and an algorithm with fixed-time convergence is proposed and used to solve constrained optimization problems. Then, the Update module, the Control module, the Gradient module, the finite-time processing (FTP) module, and the fixed-time processing (FxTP) module are designed to form an FPGA hardware implementation of neurodynamic optimization algorithms. The LPNN-based FPGA reconfigurable circuit framework can be structured by invoking the Update module, the Control module, and the Gradient module. The FTP module or the FxTP module can be called into the above framework to form the finite-time or fixed-time stable FPGA reconfiguration framework. Finally, the effectiveness and practicality of the proposed FPGA hardware implementation scheme is verified through example simulations implemented on the Vivado 2019.1 platform.

Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication

This work presents a lightweight, FPGA-based hardware implementation for polynomial multiplication, which is the major bottleneck in the NTRU public-key cryptographic scheme. NTRU is a quantum-resilient, lattice-based key exchange cryptosystem, and is currently a finalist in the ongoing National Institute of Standards and Technology post-quantum cryptography standardization. It is challenging to fit these quantum-resilient schemes into Internet of Things (IoT) sensor nodes due to the strict resource constraints (smaller area, less memory, and lower energy budgets) and the limited computational capabilities in embedded devices. We undertake this compact implementation for polynomial multiplication with two motivations: 1) constant-time implementation ensuring inherent security against timing side-channel attacks and 2) optimized hardware consumption to make it suitable for IoT applications. A single-step multiplexer-based iterative architecture is proposed to achieve both goals simultaneously. Compared to the architectures presented in the literature, our proposed work eliminates the utilization of a modular arithmetic unit and replaces it with the correct selection of input followed by an accumulator, which can help to save substantial device resources. Experimental results with an FPGA show that our proposed architecture achieves an area reduction of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.86 \times $ </tex-math></inline-formula> and the throughput increase up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.23 \times $ </tex-math></inline-formula> compared to the state-of-the-art implementation strategies, providing comparable latency along with an inherent-timing attack resilience that is absent in several NTRU hardware implementation schemes.

Memristor-Based Light-Weight Transformer Circuit Implementation for Speech Recognizing

Transformer network (TN) is a promising model widely used for natural language processing (NLP), computer vision (CV), and audio processing (AP). However, the large number of multiples and additions (multi-adds) in TN leads to a massive number of parameters in the TN model, causing an increasing number of hardware resource overhead and thus making it difficult to deploy the TN model to edge devices. To alleviate this problem, this paper proposes a circuit implementation scheme for a memristor-based lightweight transformer network (MLTN). In addition, the speech recognition task based on the speech command dataset is implemented through the modular hardware design approach, which provides an effective lightweight hardware implementation scheme for the edge devices. Further, the retention, noise immunity, variability, and stability of the designed circuit are analyzed by simulation experiments with LTSPICE. The results show that the proposed MLTN circuit not only has a lighter network model but also has significant recognition accuracy with different hardware scales. Specifically, MLTN-40 can achieve 96.18% simulation accuracy, while the energy overhead is only 3.8% of the ARM framework, which is commonly used for edge devices, and 39.9% of the traditional server (GPU), making it a promising solution for implementing speech recognition on edge devices.

Memristive Residual CapsNet: A hardware friendly multi-level capsule network

Capsule network is a promising network architecture in computer vision that integrates feature information and feature relationships of images. However, the original capsule network performs poorly with complex datasets, and the network is computationally intensive, which is not conducive to deployment in end-side devices. In this paper, a novel hardware-friendly capsule network named MRCapsNet is proposed to improve the performance of the capsule network and make it deployable in end-side devices. In the proposed network, the multi-level residual capsule block is constructed to extract features with multi-granularity from images. Moreover, a novel reconstruction subnetwork is designed to facilitate network training. Experiments show that MRCapsNet achieved competitive results on the CIFAR-10 (90.34%) and SVHN (96.59%) datasets compared with other variants of CapsNet. Further, the hardware implementation scheme of MRCapsNet based on memristor crossbars is designed to provide a nano-scale, low-power capsule network deployment scheme. Finally, the power consumption of the core computing unit built by memristor elements is analyzed and calculated, and the maximum power consumption of a memristive neuron is only 6.4μW during the inference of the network, which is significantly less than the CMOS-based circuit.

Implementation of White Rabbit Time Synchronization System in State Acquisition System of High-energy Physics Experimental Device

Abstract The state acquisition system of high energy physics experimental device has very high requirements for the clock synchronization accuracy of each node. The White Rabbit (WR) distributed synchronous timing technology can realize multi node sub nanosecond clock distribution within several kilometers, and meet the requirements of clock synchronization accuracy of the system. This paper presents an implementation of WR timing system with ZYNQ 7045 as the core in the state acquisition system. This paper introduces the hardware design and implementation scheme of collector node, the implementation scheme of WR node, and the statistical data of WR-PTP time synchronization experiment results. The test results show that this method can realize the time synchronization between the nodes of the state collector, and the accuracy is better than 1 nanosecond. It can provide high-precision time synchronization function for the multi node signal acquisition system of high-energy physics experiment.

Flash Memory Array for Efficient Implementation of Deep Neural Networks

The advancement of artificial intelligence applications is promoted by developing deep neural networks (DNNs) with increasing sizes and putting forward higher computing power requirements of the processing devices. However, due to the process scaling of complementary metal–oxide–semiconductor technology approaches to the end and the bottleneck of data transmission in the von‐Neumann architecture, traditional processing devices are increasingly challenging to meet the requirements of deeper and deeper neural networks. In‐memory computing based on nonvolatile memories has emerged as one of the most promising solutions to overcome the bottleneck of data transmission in the von‐Neumann architecture. Herein, systematic implementation of the novel flash memory array‐based in‐memory computing paradigm for DNNs from the device level to the architecture level is presented. The methodology to construct multiplication‐and‐accumulation units with different structures, hardware implementation schemes of various neural networks, and the discussion of reliability are included. The results show the hardware implementations of the flash memory array‐based in‐memory computing paradigm for DNN own excellent characteristics such as low‐cost, high computing flexibility, and high robustness. With these advantages, in‐memory computing paradigms based on flash memory arrays show significant benefits to achieve high scalability and DNNs’ energy efficiency.

8-Bit NCL Asynchronous Multiplier based on Radix-4 Booth Algorithm

Multiplier is one of the key modules in signal processing circuit and processor, and its robustness is especially important in the complex environment. Due to the lack of robustness of single-rail logic, a Null Convention Logic (NCL) Multiplier based on the Radix-4 Booth 8-bit fast parallel structure is proposed in this paper. The Radix-4 Booth algorithm reduces the number of partial products to lower the computing time, and the “sign generate” algorithm simplifies sign extension bitcomputation. In order to demonstrate the effectiveness of the proposed hardware implementation scheme, we implement an improved 8-bit NCL multiplier on vivado platform, the speed of which is 14% higher than that of the traditional Wallace NCL 8bit multiplier.

Real-time online monitoring and protection control system for automobile generator based on artificial intelligence

This paper mainly introduces the shortcomings of the traditional automobile generator control system and the improvement of the defects of the traditional automobile generator control system. This article is divided into seven chapters to describe the design background, design ideas, implementation plans and test results of the intelligent detection and protection system for automotive generators. The first chapter mainly introduces the domestic and international research on the intelligent detection and protection system of automobile generators and the design significance of the intelligent detection and protection system of automobile generators. The second chapter briefly describes the overall design ideas and plans of the intelligent detection and protection system for automobile generators, and proposes the general design direction of the overall system. The third chapter puts forward the hardware implementation scheme of the intelligent detection and protection system of automobile generators. The fourth chapter mainly summarizes the design ideas and design methods of the main software of the system. The fifth chapter mainly sets the parameters of the intelligent detection and protection system of the automobile generator, and reduces the error to the allowable range. The sixth chapter is mainly about the experience and summary of this research topic.

Design of Broadband Micro-Power Wireless Communication Test System Based on TTCN-3

In order to optimize the network architecture, narrowband micro-power wireless communication technology is developing towards broadband. In order to ensure the conformance of the functions and protocol standards of the developed broadband micro-power wireless communication module and the interconnection of different manufacturers, it is particularly important to test the products. Based on TTCN-3 and Titan platform, a conformance testing system for broadband micro-power wireless communication protocol is designed. The hardware and software implementation scheme of the conformance testing system is given, and the implementation mechanism and key technologies of each part of the system are described. An interoperability testing platform is constructed to realize the integrated distribution network testing and interoperability testing. Protocol conformance testing cases are designed by using black box testing method. It provides a test basis for the research of broadband micro-power wireless communication.

Resource‐efficient FPGA implementation of perspective transformation for bird's eye view generation using high‐level synthesis framework

Bird's eye view (BEV) generation from front-looking video stream is considered an important pre-processing task in various computer vision applications such as driver assistance systems. In this work, hardware implementation of this process using high-level synthesis in Simulink environment has been considered for rapid prototyping under real-time constraints. Traditionally, researchers have employed lookup table-based approaches to circumvent the exorbitant cost of implementing arithmetic modules associated with the perspective transformation. The hardware implementation scheme proposed here, however, demonstrates that a polynomial approximation over the limited domain of the involved operands not only saves precious hardware resources but also provides better fixed-point precision. Synthesis results on Zynq-7000 FPGA show that the proposed circuit reduces the block memory utilisation by 9% compared to the lookup table-based built-in Simulink Vision HDL block. The proposed design evaluates the results in fixed-point format which is essential for subsequent bilinear interpolation to produce high-fidelity output frame, albeit at the cost of 4% increase in DSP48E utilisation. The approximation error of the proposed solution is less than quarter-pixel on average. The proposed hardware has been integrated as an IP core in a hardware-software co-design system. The whole framework is publicly available to facilitate practitioners and researchers.

Hardware Implementation of Energy Efficient Deep Learning Neural Network Based on Nanoscale Flash Computing Array

AbstractDeep learning neural network (DNN) can provide efficient approaches to process the increasing unstructured data, such as images, audio, and video. To improve the computing power and the energy efficiency of data processing in DNN, a universal and reconfigurable computing paradigm with the hardware implementation scheme including the convolution, pooling, and fully connected layers is developed based on nanoscale flash computing arrays, which can be massively fabricated. Via precisely tuning the threshold voltage, the fabricated 65 nm nanoscale flash cells can exhibit 16 levels (four bits) of storage states. To confirm the feasibility of the computing paradigm, an exemplary five‐layer DNN is simulated based on the measured data from the nor‐type (NOR) flash memory and exhibits 97.8% recognition accuracy of Modified National Institute of Standards and Technology (MNIST) handwritten digit database with the speed of 4.2 × 105 fps at 104 MHz operating frequency. The proposed paradigm with low energy and chip cost shows great promise for future energy efficient and massively parallel data processing of DNN.

Compressed sensing imaging system based on improved theoretical model and its weighted iterative strategy

Based on the characteristic analysis of the traditional block-based compressed sensing system, an improved compressed sensing theory model is proposed in this paper, and its hardware implementation scheme and the overall system workflow are specified according to the model requirements. Compared with the traditional block-based compressed sensing system, the linear array detector is used instead of the area array detector in the system, and the one-dimensional encoding is adopted instead of the two-dimensional encoding to simplify the encoding process. The experimental results show that the system proposed by this paper can significantly improve the image quality compared with the block-based compressed sensing system under the same system conditions, and eliminate the block effect that is common in the block-based compressed sensing system. On the basis of the proposed system, a weighted iterative restoration strategy based on frequency estimation is proposed. By adaptively adjusting the restoration process and optimizing the distribution of computing resources, the image quality is further improved.

Design and Implementation of Wireless Network Control System for Briquette Production

With the implementation of the sustainable development strategy, the control system of industrial production also needs to be kept up with the pace of environmental protection and energy conservation.This paper discusses the design and implementation of wireless network transformation of briquette control system in chemical production. The hardware and software implementation scheme is designed for industrial wireless network control functions. The brief solution and the corresponding network architecture are designed. The security, routing and control performance of the network are tested. The results show that the system has good fault tolerance and real-time performance.

Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory

Embedded memory is a critical component in today’s mobile video processing systems, increasingly dominating power consumption and shortening battery life of mobile devices. Traditional hardware-level power optimization techniques usually come with significant implementation overhead to solve the memory failure problem during low-voltage operations. This paper presents a novel mobile video memory to exploit the power saving opportunities provided by a viewer experience under environmental visual interference. The viewing contexts, in particular the ambient luminance, significantly influence the quality of the viewer experience, and in the context with higher luminance levels, mobile users have higher tolerance to the video degradation. Accordingly, the memory failures can be introduced adaptively to achieve power savings without influencing the viewer experience. To meet the silicon area constraint in mobile devices, a simple but an efficient hardware implementation scheme is developed to minimize area overhead. The experimental results based on a 45-nm CMOS technology show that, as compared with the conventional memory design, the proposed technique can achieve up to 48% power savings with good perceivable quality and negligible implementation overhead.

A memory efficient implementation scheme of Gauss error function in a Laguerre-Volterra network for neuroprosthetic devices.

Cognitive neural prosthesis is a manmade device which can be used to restore or compensate for lost human cognitive modalities. The generalized Laguerre-Volterra (GLV) network serves as a robust mathematical underpinning for the development of such prosthetic instrument. In this paper, a hardware implementation scheme of Gauss error function for the GLV network targeting reconfigurable platforms is reported. Numerical approximations are formulated which transform the computation of nonelementary function into combinational operations of elementary functions, and memory-intensive look-up table (LUT) based approaches can therefore be circumvented. The computational precision can be made adjustable with the utilization of an error compensation scheme, which is proposed based on the experimental observation of the mathematical characteristics of the error trajectory. The precision can be further customizable by exploiting the run-time characteristics of the reconfigurable system. Compared to the polynomial expansion based implementation scheme, the utilization of slice LUTs, occupied slices, and DSP48E1s on a Xilinx XC6VLX240T field-programmable gate array has decreased by 94.2%, 94.1%, and 90.0%, respectively. While compared to the look-up table based scheme, 1.0×1017 bits of storage can be spared under the maximum allowable error of 1.0×10-3. The proposed implementation scheme can be employed in the study of large-scale neural ensemble activity and in the design and development of neural prosthetic device.

Design and efficient hardware implementation schemes for non-Quasi-Cyclic LDPC codes

The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic (NQC) Low-Density Parity-Check (LDPC) codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing (MOMP) algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing (OMP) technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-dB coding gain for Binary PhaseShift Keying (BPSK) in an Additive White Gaussian Noise (AWGN) channel, the decoder with the proposed scheme achieves a 23.8%-52.6% reduction in logic utilization per Mbps and a 29.0%-90.0% reduction in message-memory bits per Mbps.