Resource‐efficient FPGA implementation of perspective transformation for bird's eye view generation using high‐level synthesis framework

Abstract

Bird's eye view (BEV) generation from front-looking video stream is considered an important pre-processing task in various computer vision applications such as driver assistance systems. In this work, hardware implementation of this process using high-level synthesis in Simulink environment has been considered for rapid prototyping under real-time constraints. Traditionally, researchers have employed lookup table-based approaches to circumvent the exorbitant cost of implementing arithmetic modules associated with the perspective transformation. The hardware implementation scheme proposed here, however, demonstrates that a polynomial approximation over the limited domain of the involved operands not only saves precious hardware resources but also provides better fixed-point precision. Synthesis results on Zynq-7000 FPGA show that the proposed circuit reduces the block memory utilisation by 9% compared to the lookup table-based built-in Simulink Vision HDL block. The proposed design evaluates the results in fixed-point format which is essential for subsequent bilinear interpolation to produce high-fidelity output frame, albeit at the cost of 4% increase in DSP48E utilisation. The approximation error of the proposed solution is less than quarter-pixel on average. The proposed hardware has been integrated as an IP core in a hardware-software co-design system. The whole framework is publicly available to facilitate practitioners and researchers.