Filter Hardware Research Articles

Validation of a wireless dry electrode system for electroencephalography

BackgroundElectroencephalography (EEG) is a widely used neuroimaging technique with applications in healthcare, research, assessment, treatment, and neurorehabilitation. Conventional EEG systems require extensive setup time, expensive equipment, and expertise to utilize and therefore are often limited to clinical or laboratory settings. Technological advancements have made it possible to develop wireless EEG systems with dry electrodes to reduce many of these barriers. However, due to the lack of homogeneity in hardware, electrode evaluation, and methodological procedures the clinical acceptance of these systems has been limited.MethodsIn this investigation the validity of a wireless dry electrode system compared to a conventional wet electrode system was assessed, while addressing methodological limitations. In Experiment 1, the signal output of both EEG systems was examined at Fz, C3, Cz, C4, and Pz using a conductive head model and generated test signals at 2.5 Hz, 10 Hz, and 39 Hz. In Experiment 2, two-minutes of eyes-closed and eyes-open EEG data was recorded simultaneously with both devices from the adjacent electrode sites in a sample of healthy adults.ResultsBetween group effects and frequency*device and electrode*device interactions were assessed using a mixed ANOVA for the simulated and in vivo signal output, producing no significant effects . Bivariate correlation coefficients were calculated to assess the relationship between electrode pairs during the simultaneous in vivo recordings, indicating a significant positive relationship (all p's < .05) and larger correlation coefficients (r > ± 0.5) between the dry and wet electrode signal amplitude were observed for theta, alpha, beta 1, beta 2, beta 3, and gamma in both the eyes-closed and eyes-open conditions.ConclusionsThis report demonstrates preliminary but compelling evidence that EEG data recorded from the wireless dry electrode system is comparable to data recorded from a conventional system. Small correlation values in delta activity were discussed in relation to minor differences in hardware filter settings, variation in electrode placement, and participant artifacts observer during the simultaneous EEG recordings. Study limitations and impact of this research on neurorehabilitation were discussed.

A Method based on H.264 to de-block Filter Hardware System

A Method based on H.264 to de-block Filter Hardware System

An improved criterion for peak-to-peak realization of direct-form interfered digital filters employing saturation nonlinearities

Purpose– The purpose of this paper is to present a criterion for global asymptotic stability of state-space direct-form digital filters employing saturation arithmetic.Design/methodology/approach– An elegant use of inducedl∞approach (also known as a peak-to-peak approach) is made to develop a criterion for the overflow stability of state-space direct-form digital filters.Findings– The criterion not only guarantees asymptotic stability but also reduces the effect of external interference. The presented method yields better interference attenuation level as compared to a recently reported method. Numerical examples are given to illustrate the effectiveness of the proposed method.Practical implications– Digital filters are important dynamical systems in signal processing which are used for the processing of discrete signals. During the implementation of higher-order digital filter in hardware or software, introduction of external interference is unavoidable. Therefore, stability analysis of digital filters in the presence of external interference is of much practical importance.Originality/value– The main result of the paper is reported for the first time and it is useful to establish the asymptotic stability of digital filters in the presence of external disturbances.

The Development and Implementation of a Low-Cost Integrated Control System for Aerial Survey

This paper presents the development of a low-cost integrated control system for aerial survey based on pan-tilt and multi-sensor data fusion. The design of aerial vehicle route planning, pan-tilt mechanical structure and attitude estimation are discussed in detail. A route planning file containing flight paths and automatic exposure points is firstly derived by the route plan software to control the whole aerial photography task. As for the most challenging task, accurate attitude estimation, a custom Kalman filtering hardware module based on FPGA is introduced. The introduced module invokes the build-in multipliers of FPGA to achieve Kalman filtering hardware implementation, which leads to a rapid attitude estimation. After that mechanical structure of a specialized pan-tilt is designed and fabricated to adjust the camera attitude to the vertical direction of the ground plane. The practice aerial survey is also conducted to evaluate the accuracy and performance of designed control system. Our studies indicates that with the designed control system, it would be feasible to configure an aerial survey system while cooperate with professional aerial camera or some other civil cameras, which will make it easier to focusing on evaluation of aerial survey concepts and approaches.

The Design of Wireless Monitoring System Based on the High-Speed Rotating Fan of the STM32

In view of the traditional measurement system is not easy to install and design shortcomings, such as volume and requires a lot of wiring, This system used STM32 microprocessor and CC2530 ZigBee wireless technology to achieve the acquisition of High-speed rotating strain, high-speed storage, wireless monitoring system. This system can be used to replace manual operation, make the test more intelligent, more convenient and more accurate. This article used the STM32F103 chips as the main control system chip, implement the collection and storage function, CC2530 ZigBee protocol implemented wireless transmission function. Acquisition module used the high-speed AD transform chip ADS1274, Four-way synchronization acquisition, which convert digital signal transmit to the main control chip, the main control chip collected data which stored in the high capacity SD card. When need data, the system get the data from the SD card by zigbee wireless transmission to the monitor software. This system used the hardware filter and software filter, join the manning window, which reduced the influence of noise and improved the system accuracy. This paper had solved the monitoring question of the high-speed acquisition structure, implemented the function which data collection, storage and remote control for the integration, according to testing, the various technical indexes reach the system requirements[1].

A new strategy of image denoising using multiplier-less FIR filter designed with the aid of differential evolution algorithm

Due to the rapid development of one-dimensional signal processing in last few decades, it has spread out its wings in the field of multi-dimensional signal processing too. This has mainly been dominated by the proposition and implementation of robust algorithms which have focused on efficient storage and reliable transmission of digital images of various kinds. During the transmission through wired or wireless medium, digital images often encountered different types of channel noise which can significantly distort its appearance. As a matter of fact, filtering operation of digital images forms one of the most important tasks to be performed at the receiving end. In this paper, we have proposed a novel design strategy of two-dimensional (2-D) low-pass filter by means of a powerful evolutionary optimization technique called Differential Evolution (DE) algorithm. Mask coefficients of the proposed filter are constrained to assume values as sum of powers-of-two, thus making the filter hardware friendly. Experimental results have demonstrated the power of the algorithm in reducing the effect of Gaussian noise from digital image in terms of various performance parameters like peak signal-to-noise ratio (PSNR), structural similarity index measure (SSIM), image enhancement factor (IEF) and image quality index (IQI) and so on. A number of test images have been taken into our consideration for the purpose of establishing our proposition. Simulation results have confirmed the superiority of the proposed DE-based filter over the conventional low-pass filtering method.

Improvement of the Analog Data Acquisition Accuracy Based on the Oversampling Technology

Unmanned aerial vehicle (UAV) flight control system often needs the acquisition of sensor signal in analog form. In that case, the accuracy of the analog signal acquisition has a very important influence on the UAV flight control system. During the collection of analog signal, noise can have a negative effect on the accuracy of this collection, so we need to filter out the noise. However, some kinds of noise cannot be filtered out with hardware filters, which makes it necessary to combine oversampling technology and digital filters. In this paper, we make use of own-designed circuit to discuss some relative problems about the improvement of the analog data acquisition accuracy with oversampling technology which Verify the effectiveness of the oversampling method by comparing the traditional sampling method and the oversampling technology.

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

BLDC Motor Sensorless Control System Based on ADSP-BF548

In this thesis , the control strategy based on sensorless BLDCM(Brushless DC Motor) has been researched.A control system for BLDCM operating on ADSP-BF548 has been given. we focus on studying the control strategy of sensorless BLDC motor based on back-EMF detection, and present a control system for BLDC motor based on ADSP-BF548 special for motor control. The calculation method of back EMF in BLDC motor was deduced and the hardware circuit of line voltage detecting was designed. A pre-position starting tactics based on back EMF detection and a tactics of phase converting by postponing back-emf-zero-crossing detecting was designed. The signal wave was filtered by postponing back-emf-zero-crossing detecting when back-emf-zero-crossing had been detected. To release the phase delay caused by hardware filtering, a phase compensation algorithm has been designed. The PID adjusting algorithm and other strategy are designed in this program. Experimental results show that the control system has good speed adjusting performance and runs stably.

Suppressing PD’s Narrow Band Noise in the PD Monitoring Frequency Band Using Complex Wavelet Packet Transform

By combining the method of construct wavelet packet and complex wavelets, complex wavelets packet is constructed with the same amplitude-frequency characteristics of corresponding real wavelet packet and the same phase spectrum of corresponding complex wavelets, and then give the specific method of constructing complex wavelets packet, evaluate the effect of original PD simulative signals direct reconstruction after decomposition by using Normalized Correlation Coefficient (NCC) and Variational Trend Parameter (VTP) also and the relative error of the amplitude, verify the capability of restore Non-stationary Oscillating Partial Discharge Signals effectively and the correctness of the complex wavelets packets construction. At last, complex wavelets packet is used to denoise PD admixture simulative and measured signals with different frequency and strength noises, overcome the difficults of more loss using hardware filter and bad effect using wavelets packet transformation when narrow band noise in the monitoring frequency band.

Spur Mitigation in High-Sensitivity GNSS Receivers

The presence of spurious tones in a Global Navigation Satellite Signal (GNSS) receiver's RF and analog front-end signal spectrum leads it to compute receiver's position erroneously. Addressing spurs is crucial in modern multiconstellation GNSS receivers as their wide bandwidth and coexistence on a shared chip or board with other radios and processors make them highly susceptible to corruption by dynamically varying spurs. Proposed here is a solution to mitigate a large number of spurs in GNSS receivers using a combination of limited number of frequency-tracked digital hardware filters, fast Fourier transform-based spur detectors, and a firmware algorithm predicting and weeding out potentially corrupt satellite measurements. Laboratory validation results from an experimental GNSS receiver in a CMOS system-on-chip are shown to demonstrate its effectiveness.

Design and Construction of a Brain-Like Computer: A New Class of Frequency-Fractal Computing Using Wireless Communication in a Supramolecular Organic, Inorganic System

Here, we introduce a new class of computer which does not use any circuit or logic gate. In fact, no program needs to be written: it learns by itself and writes its own program to solve a problem. Gödel’s incompleteness argument is explored here to devise an engine where an astronomically large number of “if-then” arguments are allowed to grow by self-assembly, based on the basic set of arguments written in the system, thus, we explore the beyond Turing path of computing but following a fundamentally different route adopted in the last half-a-century old non-Turing adventures. Our hardware is a multilayered seed structure. If we open the largest seed, which is the final hardware, we find several computing seed structures inside, if we take any of them and open, there are several computing seeds inside. We design and synthesize the smallest seed, the entire multilayered architecture grows by itself. The electromagnetic resonance band of each seed looks similar, but the seeds of any layer shares a common region in its resonance band with inner and upper layer, hence a chain of resonance bands is formed (frequency fractal) connecting the smallest to the largest seed (hence the name invincible rhythm or Ajeya Chhandam in Sanskrit). The computer solves intractable pattern search (Clique) problem without searching, since the right pattern written in it spontaneously replies back to the questioner. To learn, the hardware filters any kind of sensory input image into several layers of images, each containing basic geometric polygons (fractal decomposition), and builds a network among all layers, multi-sensory images are connected in all possible ways to generate “if” and “then” argument. Several such arguments and decisions (phase transition from “if” to “then”) self-assemble and form the two giant columns of arguments and rules of phase transition. Any input question is converted into a pattern as noted above, and these two astronomically large columns project a solution. The driving principle of computing is synchronization and de-synchronization of network paths, the system drives towards highest density of coupled arguments for maximum matching. Memory is located at all layers of the hardware. Learning, computing occurs everywhere simultaneously. Since resonance chain connects all computing seeds, wireless processing is feasible without a screening effect. The computing power is increased by maximizing the density of resonance states and bandwidth of the resonance chain together. We discovered this remarkable computing while studying the human brain, so we present a new model of the human brain in terms of an experimentally determined resonance chain with bandwidth 10−15 Hz (complete brain with all sensors) to 10+15 Hz (DNA) along with its implementation using a pure organic synthesis of entire computer (brain jelly) in our lab, software prototype as proof of concept and finally a new fourth circuit element (Hinductor) based beyond Complementary metal-oxide semiconductor (CMOS) hardware is also presented.

Hardware filtering of non-intended frames for energy optimisation in wireless sensor networks

Communication is responsible for the majority of energy consumption in typical wireless sensor networks WSNs. While transmission energy can be controlled at each node, reception energy is outside the control of the nodes because they usually do not know the arrival time of their packets and they cannot avoid overhearing packets directed to the other nodes in range. Energy-aware MAC protocols apply duty-cycling which keeps the radio module off for most of the time and wakes it up periodically, but they suffer from overhearing which has been addressed so far either by means of preambles or by means of separate wake-up channels. This paper proposes a complementary approach which exploits the hardware frame filtering capabilities provided by state-of-the-art radio transceivers. Extensive experiments performed on VirtualSense motes show that hardware frame filtering saves more than 50% of the energy spent in the reception of non-intended packets.

Filtering Design and Analysis of Clamp-On Pressure Signals of High Pressure Fuel Pipe

Measuring the clamp-on pressure of high pressure fuel pipe is a shortcut for obtaining injection parameters and fault diagnosis of the fuel injection pumps [1,. Based on the analysis of the fuel injection process of fuel injection pump, analyzed the differences of practical injection process and geometric injection process, and obtained the theory waveform feature points of diesel engine high pressure pipe fuel injection process. In order to obtain the clamp-on pressure waveform which feature points consistent with the theoretical waveform, designed the hardware filter based on MAX293. Considering the clamp-on pressure signal sometimes must also meet the requirements of no delay, designed frequency domain filter. Two filtering methods have reached the expected results.

Multi-Standards Deblocking Filter Based SIMD Technology

Due to real-time video decoding requirements, hardware accelerators for video deblocking filtering has gradually become a research hotspot in recent years. Compared with the traditional deblocking filter hardware accelerators which support only single video coding standard, this paper implemented a deblocking filter structure, which filtering algorithm can be configured to support multiple video coding standards; Using SIMD technology to make filtering data fully parallel computing. This structure is a multi-standard deblocking filter accelerator, supports H264, AVS, VP8 to, RealVideo, four kinds of video coding standards. The clock frequency is 200MHz, and it can be used for real-time filtering of multi-standard HD video processing. Deblocking Filter Algorithm

A high performance deblocking filter hardware for high efficiency video coding

The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. Therefore, in this paper, the first HEVC deblocking filter hardware in the literature is proposed. Two parallel datapaths are used in the proposed hardware in order to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is verified to work correctly on an FPGA board. The proposed HEVC deblocking filter hardware can code 30 full HD (1920x1080) video frames per second. Therefore, it can be used in consumer electronics products that require a real-time HEVC encoder or decoder.

Design of 50 Hz notch filter circuits for better detection of online ECG

Technological evolution in bio-signal processing has enabled computer-based analysis of ECG which is an adjunct to the doctor in terms of feature extraction and diagnosis. However, acquisition and reliable parameter extraction of ECG signals using a computer based system is extremely susceptible to power line interference. 50 Hz active analogue notch filter is used to trim down hum in such applications. An attempt has been made to design various 50 Hz active notch-filter topologies in P-spice. Based on their amplitude and phase response, add-on notch filter hardware is developed and used with real-time computer based ECG system. The amplifier system includes biosensors, cascaded amplifiers, right leg drive circuits, active filters and 50 Hz notch filters. Analogue output of amplifier system is interfaced to the computer for recording and analysis. Thus a computer based compact and enhanced signal acquisition system is developed that yields online ECG of greatest clinical use.

Fast True RMS Algorithm Using in the High-Voltage General Inverter

The high-voltage general inverter which has the advantage of the structure， has become the key equipment to saving energy in recent years. The inverter output current is the key variable of overload protection, over current protection and V/F control compensation, so the real-time accurate measurement of its RMS is extremely important. In this paper, the output current signals preprocess by hardware filter firstly, and then find the RMS of the current signal in the period of the waveform. Meanwhile, this algorithm belong to true RMS algorithm category, which suitable for testing harmonic current signal, and can avoid mean filter to reduce the computation time. By using this algorithm, the inverter control system provides accurate reference for overload protection reduces the systematic disoperation rate and sets the more accurate security allowance to ensure the safe operation of equipment.

A lightweight sensing method of tooth-touch sound for disabled person using remote controller

To support disabled people to use remote controllers, several biological signals are used. The tooth-touch is one of desirable biological signals. This is because it is the simple and natural human behavior. However, a sophisticated signal processing to extract only the tooth-touch sound is needed since the tooth-touch sound is mixed with the voice sound. This paper proposes a lightweight sensing method extracting the tooth-touch without a sophisticated signal processing to eliminate only voice sound from the sound wave in which tooth-touch and voice are mixed. Instead of the audible sound wave, proposal uses a shock wave (i.e., ultrasonic wave) which is generated when the upper tooth and the lower tooth hit each other. Using the shock wave generated to detect the tooth-touch, a trivial high-pass filter can eliminate only voice sound in the lower frequency domain than in the ultrasonic domain including the tooth-touch. Through a preliminary experiment that uses a conventional microphone and well-known digital high-pass filter, we show that the used electret microphone can sense the tooth-touch as ultrasonic wave and the high-pass filter can extract only tooth-touch. Then, we show some robustness of our method by using the sound waves including the voice and tooth-touch. In addition, we design the filtering hardware to implement a small and cheap system-on-chip achieving a real-time operation. Through the implementation of Field Programmable Gate Array, and the simulation, we show that our hardware is small and performs well for a real-time operation.

The Research of Technology of Bloom Filter Realization in Hardware

Bloom filter is a space-efficient data with a certain probability of false positive . We present a reusable hardware implementation framework, define a module interface to provide users with a customize module, and introduce the constraints of hardware resources in the analysis of false positive rate against the traditional Bloom filter hardware design and analysis of the Bloom filter false positives. Finally, we make verification and analysis of our design combined with the the NetMagic platform.