Hardware Feasibility Research Articles

Anatomical, blood oxygenation level‐dependent, and blood flow MRI of nonhuman primate (baboon) retina

The goal of this study was to demonstrate high-resolution anatomical, blood oxygenation level-dependent, and blood flow MRI on large nonhuman primate retinas using a 3-Tesla clinical scanner as a first step toward translation. Baboon was chosen because of its evolutionary similarity to human. Anesthetized preparation, free of eye-movement artifacts, was used to evaluate clinical scanner hardware feasibility and optimize multimodal protocols for retinal MRI. Anatomical MRI (0.1×0.2×2.0 mm3) before contrast-agent injection detected three alternating bright-dark-bright layers. The hyperintense inner strip nearest to the vitreous was enhanced by an intravascular contrast agent, which likely included the ganglion and bipolar cell layer and the embedded retinal vessels. The hypointense middle strip showed no contrast enhancement, which likely included the avascular outer unclear layer and photoreceptor segments. The hyperintense outer strip showed contrast enhancement, which likely corresponded to the choroid vascular layer. In the posterior retina, the total thickness including the choroid was 617±101 μm (±standard deviation, n=7). Blood oxygenation level-dependent functional MRI (0.3×0.6×2.0 mm3) of oxygen inhalation relative to air increased the signals by 6.5±1.4%. Basal blood flow (2×2×2 mm3) was 83±30 mL/100 g/min (air), and hypercapnia increased blood flow by 25±9% (P<0.05). This study demonstrates multimodal MRI to image anatomy, physiology, and function on large nonhuman primate retinas using a clinical scanner, offering encouraging data to explore human applications.

Guest Editorial: Special Issue on SoC for Multimedia Networking (SiPS 2007)

This special issue focuses on “SoC for Multimedia Networking,” the theme of the 2007 IEEE Workshop on Signal Processing Systems (SiPS 2007) held in Shanghai, China in October 2007. This issue consists of highest quality papers selected from SiPS 2007 presentations with three major emphases centered on multimedia, networking, and architecture/SoC. For SiPS 2007, we were very pleased to receive a record number of 299 paper submissions from 36 countries. After a rigorous review and selection process, the final technical program consisted of 130 papers (43.48% acceptance rate) representing 25 different countries. These papers were arranged into nine lecture and 10 poster sessions (one special session), and the threeday technical program also included a student paper contest. The highlights of the workshop were the three keynote presentations by Magdy Bayoumi, Liang-Gee Chen, and Lajos Hanzo, each of them addressing state-ofthe-art and future direction in these emerging areas. To select high quality papers for publication in this special issue, authors of the papers that received high review scores were invited to submit expanded version of their papers to include more in-depth research work. Each of the papers was again carefully reviewed by at least three reviewers and the final decision for each was reached after careful discussion among the four guest editors. Finally, only seven papers passed through this rigorous process and were eventually accepted. They address some contemporary design and implementation issues in “SoC for Multimedia Networking” applications. In multimedia communication, it is always challenging to achieve high received video quality under coding and communication constraints. Guo et al. presents a fast multihypothesis motion compensated filter for video denoising. The authors utilize a number of hypotheses (temporal predictions) to estimate the current pixel which is corrupted with noise. Song et al. proposes an adaptive pixel interpolation technique for spatial error concealment in block-based coding system, where a missing pixel in a corrupted block can be derived from four neighborhoods of the block through interpolation using a multiple prediction strategy. The design works effectively in consecutive block loss situation which is common in real-time video. Pantoja et al. addresses the use of super-resolution algorithm based on irregular sampling for video transcoding with resolution conversion. This is because in transcoding, quantization and other techniques could result in lower video output quality. The proposed method was applied to VC-1 to H.264 transcoding to show video quality improvement. The paper also includes a hardware feasibility study. In system-on-chip designs, recent research have migrated from fairly simple single processor and memory designs to relatively complicated systems with multiple processors, onchip memories, standard peripherals, and other functional blocks. Communication between these blocks becomes the dominant critical system path and performance bottleneck of system-on-chip designs. Network-on-chip architectures emerged as solutions for future system-on-chip communication architecture designs. Wang et al. presents a novel network-onchip architecture, pipelining multi-channel central caching, to address the cost and communication latency/throughput of existing architectures. By embedding a central cache into every switch of the network, blocked head packets can be removed from the input buffers and stored in the caches temporally, thus alleviating the effect of head-of-line and X. Yang :W. Zhang Shanghai Jiao Tong University, Shanghai, China

Transcoding with Resolution Conversion Using Super-Resolution and Irregular Sampling

In transcoding, quantization and other techniques could result in lower video output quality. To address this problem a novel super-resolution (SR) algorithm based on irregular sampling (IS) is presented in this paper. The high-resolution (HR) frame is obtained as an interpolation of one or more previous frames; the resulting interpolated frame has samples non-uniformly spaced in the areas where movement happened. To reconstruct the irregular sampled frame we use a well-known irregular sampling algorithm modified to perform in 2-D space. Moreover, because SR algorithms are in general computationally expensive, we also present a hardware feasibility study. The proposed solution does not target any specific application but we have specifically tested the algorithm in a transcoding environment. In particular, we have applied it to VC-1 to H.264 transcoding and applied down/up sampling. Experimental results show that the proposed algorithm improves video quality significantly.

Area-efficient pixel rasterization and texture coordinate interpolation

In this paper, new pixel rasterization and texture coordinate interpolation algorithms are presented to reduce silicon area. The proposed pixel rasterization based on the characteristics of edge function saves silicon area in terms of gate count by 38.9% and 35.3% compared to the previous centerline and scanline algorithms, respectively. The proposed texture coordinate interpolation combines the benefits of division and midpoint iteration in order to reduce silicon area without performance loss in computing the fraction part of texture coordinates, which is required for texture filtering. The proposed texture coordinate interpolation architecture uses less silicon gates than the architecture using dividers, and the gate count reduction ratios are 25.2% and 37.0% for 16- and 32-bit texture coordinates, respectively. The hardware feasibility of the proposed architecture is proved by implementation into a three-dimensional (3D) graphics SoC.

Model-Based Ionized-PVD-Source Scaling and Performance: Hardware-Feasibility Study

The ionized physical vapor deposition (IPVD) has been utilized in semiconductor processing for metallization and is still promising to extend coverage performance and combined with atomic layer deposition up to submicrometer technology. To aid further development of the hardware and process and address the extendability of IPVD technology to future nanoscale fabrication, the plasma fluid 2-D model was developed and used to study the impact of the geometry and the characteristics of the inductively coupled-plasma source incorporated in the IPVD system. The model comprises the 2-D axisymmetric equipment simulation code considering a Cu+Ar collisional mechanism, including charge exchange and Penning ionization, and a gas heating with rarefaction effect. An empirically based variable ion-mobility approach has been implemented to achieve convergency of the model solutions. The mechanism of the sputtered-metal thermalization was estimated by an analytical approach and incorporated into fluid model. The initial simulation results were validated and calibrated through experimental measurements of the plasma characteristics in the baseline IPVD system. The model outputs were related to the various geometrical configurations and used to investigate the hardware feasibility for qualitative (processlike) upscaling of the baseline IPVD system. In the process of the investigations, the novel solutions were obtained (segmented antenna and "bridged-slot" deposition baffle) and experimentally verified and tested. Hardware-feasibility study confirmed and predicted the technical potential of the scaling-up high-density plasma source integrated into IPVD system. A ground for more complex codes and virtual experiments utilizing 3-D models has been validated and established.

Scalable Online Feasibility Tests for Admission Control in a Java Real-Time System

In the Komodo project a real-time Java system based on a multithreaded Java microcontroller has been developed. A main scheduling policy realized by hardware in the microcontroller core is a new scheme called Guaranteed Percentage (GP) scheduling. This scheme assigns each thread a guaranteed percentage of the processor power thus providing a strict isolation of the threads on the processor. To prevent processor overload in the dynamic Java environment, fast online feasibility tests are necessary before a new thread is allowed to enter the microcontroller. Starting with the well known Processor Demand Analysis, a new test based on the periodic transformation of the processor workload is developed. This is a sufficient (but not necessary) scalable test, where the number of feasible thread sets found can be controlled by the costs. Furthermore, this test can be stopped, if a given cost or time limit is reached. We additionally propose a modified version of this test, which further reduces the costs and allows an online hardware feasibility test with a polynomial complexity of O(n(n + 1)/2). An evaluation shows, that the tests proposed here are able to find more than 90% of the feasible thread sets and all non-feasible thread sets with costs suitable for online testing.

A Self-Reconfigurable Modular Robot: Reconfiguration Planning and Experiments

In this paper we address a reconfiguration planning method for locomotion of a homogeneous modular robotic system and we conduct an experiment to verify that the planned locomotion can be realized by hardware. Our recently developed module is self-reconfigurable. A group of the modules can thus generate various three-dimensional robotic structures and motions. Although the module itself is a simple mechanism, self-reconfiguration planning for locomotion presents a computationally difficult problem due to the many combinatorial possibilities of modular configurations. In this paper, we develop a two-layered planning method for locomotion of a class of regular structures. This locomotion mode is based on multi-module blocks. The upper layer plans the overall cluster motion called flow to realize locomotion along a given desired trajectory; the lower layer determines locally cooperative module motions, called motion schemes, based on a rule database. A planning simulation demonstrates that this approach effectively solves the complicated planning problem. Besides the fundamental motion capacity of the module, the hardware feasibility of the planning locomotion is verified through a self-reconfiguration experiment using the prototype modules we have developed.

A Self-Reconfigurable Modular Robot: Reconfiguration Planning and Experiments

In this paper we address a reconfiguration planning method for locomotion of a homogeneous modular robotic system and we conduct an experiment to verify that the planned locomotion can be realized by hardware. Our recently developed module is self-reconfigurable. A group of the modules can thus generate various three-dimensional robotic structures and motions. Although the module itself is a simple mechanism, self-reconfiguration planning for locomotion presents a computationally difficult problem due to the many combinatorial possibilities of modular configurations. In this paper, we develop a two-layered planning method for locomotion of a class of regular structures. This locomotion mode is based on multi-module blocks. The upper layer plans the overall cluster motion called flow to realize locomotion along a given desired trajectory; the lower layer determines locally cooperative module motions, called motion schemes, based on a rule database. A planning simulation demonstrates that this approach effectively solves the complicated planning problem. Besides the fundamental motion capacity of the module, the hardware feasibility of the planning locomotion is verified through a self-reconfiguration experiment using the prototype modules we have developed.

A pipelined architecture for image segmentation by adaptive progressive thresholding

A special purpose VLSI architecture for the real-time segmentation of endoscopic images is proposed in this paper. The architecture is based on pipelined implementation of a new algorithm named adaptive progressive thresholding (APT) that segments the darkest region of an endoscopic image representing the gastrointestinal lumen. This segmentation process is an extension of a comprehensive statistical technique based on linear discriminant analysis for partitioning the image. The APT algorithm is mapped onto a linear pipelined array of simple processing elements with each element of a particular segment communicating with its neighbours. The APT architecture is partitioned based on various sequential functions involved in the segmentation process and these functional modules are organised in a pipelined fashion according to their hardware feasibility. Currently, a prototype of the VLSI architecture for an image size of 256×256 is designed and built. The functional simulation results obtained in the APT architecture are encouraging.

A realtime hardware system for stereoscopic videoconferencing with viewpoint adaptation 1The work described herein was performed within the ACTS PANORAMA project, funded by the European Commission under grant AC092. 1

This paper describes a hardware system and the underlying algorithms that were developed for realtime stereoscopic videoconferencing with viewpoint adaptation within the European PANORAMA project. The goal was to achieve a true telepresence illusion for the remote partners. For this purpose, intermediate views at arbitrary positions must be synthesized from the views of a stereoscopic camera system with rather large baseline. The actual viewpoint is adapted according to the head position of the viewer, such that the impression of motion parallax is produced. The whole system consists of a disparity estimator, stereoscopic MPEG-2 encoder, disparity encoder and multiplexer at the transmitter side, and a demultiplexer, disparity decoder, MPEG-2 decoder and interpolator with viewpoint adaptation at the receiver side. For transmission of the encoded signals, an ATM network is provided. In the final system, autostereoscopic displays will be used. The algorithms for disparity estimation, disparity encoding and disparity-driven intermediate viewpoint synthesis were specifically developed under the constraint of hardware feasibility.

An object-based system for stereoscopic viewpoint synthesis

This paper describes algorithms that were developed for a real-time stereoscopic videoconferencing systems with viewpoint adaptation. The goal is a real telepresence illusion, which is achieved by synthesis of intermediate views from a stereoscopic camera shot with a rather large baseline. The actual viewpoint will be adapted according to the head position of the viewer, such that the impression of motion parallax is produced. The object-based system first identifies foreground and background regions and applies disparity estimation to the foreground object. A hierarchical block matching algorithm is employed for this purpose which takes into account the position of high-activity feature points and the object/background border positions. Using the disparity estimator's output, it is possible to generate arbitrary intermediate views by projections from the left- and right-view images. For this purpose, we have also developed an object-based interpolation algorithm, taking into account a very simple convex-surface model of a person's face and body. Though the algorithms had to be held rather simple under the constraint of hardware feasibility, we obtain a good quality of the intermediate-view images. Finally, we describe the hardware concept for the disparity estimator, which is the most complicated part of the algorithm.

Madet—A machine-description table based instruction scheduler in TH-RISC for exploiting instruction level parallelism

This paper presents a parameterized instruction scheduling algorithm based on machine description table for TH-RISC system, having a (3–5) stages pipeline structure. It would provide considerable flexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. And, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analyzed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem, the improvement of instruction level parallelism (ILP) and speed-up results are given. The algorithm complexity isO(n 2).

Progress in European CELSS activities

The European CELSS ∗ ∗ Controlled Ecological Life Support System, CELSS activities started in the late 1970's with system analysis and feasibility studies of Biological Life Support Systems (BLSS). Since then the European efforts have continued in two major directions: as a series of individual development tasks like the Environmental Life Support System and the Solar Plant Growth Facility, and in parallel hereto as overall coordination and planning activities for life support system long term needs definition and payload definition for COLUMBUS utilization. The early initiations for CELSS came from the industry side in Europe, but since then planning and hardware feasibility analyses have been initiated also from customer/agency side. Despite this, it is still to early to state that a “CELSS- programme” as a “concerted” effort has been agreed upon in Europe. However, the general CELSS objectives have been accpeted as planning and possible development goals for the European effort for manned space activities, and as experimental planning topics in the life sciences community for the next decades.

Digital portable transceiver using GMSK modem and ADM codec

Digital mobile radio transmission techniques and integrated circuit devices have been developed for application to a digital portable transceiver utilizing narrow-band GMSK modulation and ADM voice coding. Design and performance of a quadrature type GMSK modulator and a single-chip coherent demodulator as the GMSK modem are described. To overcome slow fading, encountered in portable applications, switching diversity using a jitter detection type sensor is proposed and shown to be effective. An experimental portable transceiver, developed to demonstrate hardware feasibility, is also described.

Digital Portable Transceiver Using GMSK Modem and ADM Codec

Digital mobile radio transmission techniques and integrated circuit devices have been developed for application to a digital portable transceiver utilizing narrow-band GMSK modulation and ADM voice coding. Design and performance of a quadrature type GMSK modulator and a single-chip coherent demodulator as the GMSK modem are described. To overcome slow fading, encountered in portable applications, switching diversity using a jitter detection type sensor is Proposed and shown to be effective. An experimental Portable transceiver, developed to demonstrate hardware feasibility, is also described.

Techniques for residue-to-analog conversion for residue-encoded digital filters

Recent papers have reported that the use of residue number coding in digital filters can result in better speed/cost ratios when compared to filters designed with conventional adders and multipliers. This paper presents two approaches to the design of residue-to-analog converters to be used with residue number filters. The first approach, based on the associated mixed radix number system, is particularly useful when it is desired to translate the residue samples directly into analog form. The second approach, based on the Chinese remainder theorem, is a more direct method for translating from residue to weighted binary representation. A hardware feasibility model is described that was constructed to demonstrate the conversion principles.