Hardware Fault Tolerance Research Articles

Machine learning without a processor: Emergent learning in a nonlinear analog network

Standard deep learning algorithms require differentiating large nonlinear networks, a process that is slow and power-hungry. Electronic contrastive local learning networks (CLLNs) offer potentially fast, efficient, and fault-tolerant hardware for analog machine learning, but existing implementations are linear, severely limiting their capabilities. These systems differ significantly from artificial neural networks as well as the brain, so the feasibility and utility of incorporating nonlinear elements have not been explored. Here, we introduce a nonlinear CLLN-an analog electronic network made of self-adjusting nonlinear resistive elements based on transistors. We demonstrate that the system learns tasks unachievable in linear systems, including XOR (exclusive or) and nonlinear regression, without a computer. We find our decentralized system reduces modes of training error in order (mean, slope, curvature), similar to spectral bias in artificial neural networks. The circuitry is robust to damage, retrainable in seconds, and performs learned tasks in microseconds while dissipating only picojoules of energy across each transistor. This suggests enormous potential for fast, low-power computing in edge systems like sensors, robotic controllers, and medical devices, as well as manufacturability at scale for performing and studying emergent learning.

Enhanced Compiler Technology for Software-based Hardware Fault Detection

Software-Implemented Hardware Fault Tolerance (SIHFT) is a modern approach for tackling random hardware faults of dependable systems employing solely software solutions. This work extends an automatic compiler-based SIHFT hardening tool called ASPIS, enhancing it with novel protection mechanisms and overhead-reduction techniques, also providing an extensive analysis of its compliance with the non-trivial workload of the open-source Real-Time Operating System FreeRTOS. A thorough experimental fault-injection campaign on an STM32 board shows how the system achieves remarkably high tolerance to single-event upsets and a comparison between the SIHFT mechanisms implemented summarises the trade-off between the overhead introduced and the detection capabilities of the various solutions.

Fault Tolerant Brushless DC Motor Drive for Aerospace Applications

This article brings out a Fault-tolerant BLDC motor drive for aerospace applications using the redundancy concept. In a way, it brings out a fault-tolerant strategy that can be used to continue the regular operation of a BLDC motor drive even after the occurrence of faults. As BLDC motors are used in critical and dangerous control areas like military services and space vehicles, a fault-tolerant drive is essential to maintain drive operation and provide desirable output. This article compares fault simulation results in the software model of a BLDC motor drive to those of fault simulation results in hardware for three main types of faults. Fault simulation is carried out for three types of faults, viz. inverter device open circuit fault, motor winding open circuit fault, and rotor position sensor (hall sensor) open-circuited fault. Fault tolerance is ensured by introducing a redundant drive (drive-2), which operates the complete drive at the advent of any of the faults mentioned above in the main (healthy) drive-1. A fault-tolerant (redundant) hardware comprising dual stator BLDC motor and redundant controllers is realized and operationalized. Fault simulation is carried out in this hardware, and these results are validated with the results of fault simulation in the MATLAB SIMULINK model. Software and hardware results are comparable and form a basis for developing fault-tolerant electro-mechanical actuation systems for high-reliability, high-cost applications, mainly aerospace.

Rust-Shyper: A reliable embedded hypervisor supporting VM migration and hypervisor live-update

Traditional embedded hypervisors usually focus on resource utilization and performance while neglecting the reliability requirements. On the one hand, the reliability issues result from the use of C language that may introduce memory safety bugs. On the other hand, most existing embedded hypervisors lacks run-time fault tolerance and dynamic bug-fixing mechanisms in deployed embedded system. To address the above challenges, in this paper, we propose Rust-Shyper, an embedded type-1 hypervisor built with Rust, which has both high performance and high reliability. We make full use of the Rust language features in terms of code safety to reduce the number of bugs within the embedded hypervisor. Furthermore, we have proposed low-overhead VM migration and hypervisor live-update mechanisms to enable our embedded hypervisor to tolerate hardware faults at runtime and dynamically fix hypervisor bugs. To the best of our knowledge, we are the first work to propose live-update mechanisms for embedded hypervisor. We have systematically evaluated the performance and reliability of Rust-Shyper, and the results show that Rust-Shyper can significantly improve memory safety without compromising performance. Furthermore, the VM migration and hypervisor live-update mechanisms only incur a small performance overhead.

Software Fault Tolerance in Real-Time Systems: Identifying the Future Research Questions

Tolerating hardware faults in modern architectures is becoming a prominent problem due to the miniaturization of the hardware components, their increasing complexity, and the necessity to reduce costs. Software-Implemented Hardware Fault Tolerance approaches have been developed to improve system dependability regarding hardware faults without resorting to custom hardware solutions. However, these come at the expense of making the satisfaction of the timing constraints of the applications/activities harder from a scheduling standpoint. This article surveys the current state-of-the-art of fault tolerance approaches when used in the context of real-time systems, identifying the main challenges and the cross-links between these two topics. We propose a joint scheduling-failure analysis model that highlights the formal interactions among software fault tolerance mechanisms and timing properties. This model allows us to present and discuss many open research questions with the final aim to spur future research activities.

Leveraging Small-Scale Quantum Computers with Unitarily Downfolded Hamiltonians

A quantum unitary downfolding formalism that works on noisy and fault-tolerant hardware is proposed and tested on several challenging chemical problems, offering a viable approach for estimating molecular properties with chemical accuracy.

Research on fault adaptive fault tolerant control of distributed wind solar hybrid generator

Due to the poor accessibility, poor operating conditions, high failure rate, long maintenance time, and difficult maintenance of wind hybrid generators, the economic loss is huge once the failure stops. To this end, the fault adaptive fault-tolerant control of distributed wind and wind hybrid generators is studied, the historical operation data of offshore wind and wind hybrid generators and onshore wind and wind hybrid generators are counted and compared, and the fault characteristics of key components of offshore wind and wind hybrid generators are analyzed. The generator sets are summarized, and the common electrical faults of wind turbines and their impacts on the system are analyzed. This paper summarizes the current research status of fault-tolerant operation of existing offshore wind and wind complementary generators in terms of software fault tolerance and hardware fault tolerance, summarizes the current fault tolerance schemes for offshore wind and wind complementary generators, and analyzes the application feasibility of existing fault tolerance schemes. In addition, the main problems of fault-tolerant offshore wind and solar complementary generator sets are pointed out, and future research hotspots are foreseen.

Formal Verification of Fault-Tolerant Hardware Designs

Formal Verification of Fault-Tolerant Hardware Designs

Practical quantum advantage in quantum simulation.

The development of quantum computing across several technologies and platforms has reached the point of having an advantage over classical computers for an artificial problem, a point known as 'quantum advantage'. As a next step along the development of this technology, it is now important to discuss 'practical quantum advantage', the point at which quantum devices will solve problems of practical interest that are not tractable for traditional supercomputers. Many of the most promising short-term applications of quantum computers fall under the umbrella of quantum simulation: modelling the quantum properties of microscopic particles that are directly relevant to modern materials science, high-energy physics and quantum chemistry. This would impact several important real-world applications, such as developing materials for batteries, industrial catalysis or nitrogen fixing. Much as aerodynamics can be studied either through simulations on a digital computer or in a wind tunnel, quantum simulation can be performed not only on future fault-tolerant digital quantum computers but also already today through special-purpose analogue quantum simulators. Here we overview the state of the art and future perspectives for quantum simulation, arguing that a first practical quantum advantage already exists in the case of specialized applications of analogue devices, and that fully digital devices open a full range of applications but require further development of fault-tolerant hardware. Hybrid digital-analogue devices that exist today already promise substantial flexibility in near-term applications.

A review of fault diagnosis and fault-tolerant control of vehicular polymer electrolyte membrane fuel cell power system

Proton exchange membrane fuel cell (PEMFC) is a promising vehicle power because of its high energy conversion efficiency and pollution-free reactant. However, the complex structure of multi-system coordination makes the correlation between parameters strong, the fault rate is high and the control is difficult. Timely and accurate fault diagnosis and effective fault-tolerant control are of great significance to the stable output and durability of PEMFC system. Firstly, this paper classifies different faults and describes the applicable scenarios of each classification method. Then, the fault diagnosis methods based on experiment, model and data are summarized, and their advantages and disadvantages are compared. Then, the methods and characteristics of hardware fault tolerance and software fault tolerance are analyzed from the point of redundancy, and the application of fault tolerance control in maintaining the stability of PEMFC system is summarized. Finally, the improvement direction and development prospect of fault diagnosis related technology of vehicle PEMFC system are proposed.

REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance

Safety-critical embedded systems may either use specialized hardware or rely on Software-Implemented Hardware Fault Tolerance (SIHFT) to meet soft error resilience requirements. SIHFT has the advantage that it can be used with low-cost, off-the-shelf components such as standard Micro-Controller Units. For this, SIHFT methods apply redundancy in software computation and special checker codes to detect transient errors, so called soft errors, that either corrupt the data flow or the control flow of the software and may lead to Silent Data Corruption (SDC). So far, this is done by applying separate SIHFT methods for the data and control flow protection, which leads to large overheads in computation time. This work in contrast presents REPAIR, a method that exploits the checks of the SIHFT data flow protection to also detect control flow errors as well, thereby, yielding higher SDC resilience with less computational overhead. For this, the data flow protection methods entail duplicating the computation with subsequent checks placed strategically throughout the program. These checks assure that the two redundant computation paths, which work on two different parts of the register file, yield the same result. By updating the pairing between the registers used in the primary computation path and the registers in the duplicated computation path using the REPAIR method, these checks also fail with high coverage when a control flow error, which leads to an illegal jumps, occurs. Extensive RTL fault injection simulations are carried out to accurately quantify soft error resilience while evaluating Mibench programs along with an embedded case-study running on an OpenRISC processor. Our method performs slightly better on average in terms of soft error resilience compared to the best state-of-the-art method but requiring significantly lower overheads. These results show that REPAIR is a valuable addition to the set of known SIHFT methods.

Cost-aware reliability task scheduling of automotive cyber-physical systems

New generation of automotives has become a typical Cyber-Physical System, including various sensors, complex communication networks and distributed computing devices. Manufacturers pay great attention to functional safety and cost control of automotive. High-end computing devices such as electronic control units (ECU) that can perform multiple tasks bring higher reliability and also lead to soaring costs. In this paper, we propose an efficient scheduling algorithm that satisfies cost and functional reliability constraints under multifunctional mixed-criticality task replication execution scenarios. Using the proposed fault-tolerant hardware cost-aware multifunctional safety assurance (FT_HCMSA) algorithm can reduce the deadline miss ratio (DMR) of high-criticality function significantly while meeting the autumotive functional safety and hardware cost constraints. FT_HCMSA uses a fine-grained ECU replacement strategy to optimize task allocation. Our experiments validate that FT_HCMSA can reduce the DMR of high-criticality level functions while meet the requirements of safety and cost.

Neural Network-based Inherently Fault-tolerant Hardware Cryptographic Primitives without Explicit Redundancy Checks

Fault injection-based cryptanalysis is one of the most powerful practical threats to modern cryptographic primitives. Popular countermeasures to such fault-based attacks generally use some form of redundant computation to detect and react/correct the injected faults. However, such countermeasures are shown to be vulnerable to selective fault injections. In this article, we aim to develop a cryptographic primitive that is fault tolerant by its construction and does not require to compute the same value multiple times. We utilize the effectiveness of Neural Networks (NNs), which show “some degree” of robustness by functioning correctly even after the occurrence of faults in any of its parameters. We also propose a novel strategy that enhances the fault tolerance of the implementation to “high degree” (close to 100%) by incorporating selective constraints in the NN parameters during the training phase. We evaluated the performance of revised NN considering both software and FPGA implementations for standard cryptographic primitives like 8×8 AES SBox and 4×4 PRESENT SBox. The results show that the fault tolerance of such implementations can be significantly increased with the proposed methodology. Such NN-based cryptographic primitives will provide inherent resistance against fault injections without requiring any redundancy countermeasures.

QCOR

Quantum computing (QC) is an emerging computational paradigm that leverages the laws of quantum mechanics to perform elementary logic operations. Existing programming models for QC were designed with fault-tolerant hardware in mind, envisioning stand-alone applications. However, the susceptibility of near-term quantum computers to noise limits their stand-alone utility. To better leverage limited computational strengths of noisy quantum devices, hybrid algorithms have been suggested whereby quantum computers are used in tandem with their classical counterparts in a heterogeneous fashion. This modus operandi calls out for a programming model and a high-level programming language that natively and seamlessly supports heterogeneous quantum-classical hardware architectures in a single-source-code paradigm. Motivated by the lack of such a model, we introduce a language extension specification, called QCOR , which enables single-source quantum-classical programming. Programs written using the QCOR library–based language extensions can be compiled to produce functional hybrid binary executables. After defining QCOR’s programming model, memory model, and execution model, we discuss how QCOR enables variational, iterative, and feed-forward QC. QCOR approaches quantum-classical computation in a hardware-agnostic heterogeneous fashion and strives to build on best practices of high-performance computing. The high level of abstraction in the language extension is intended to accelerate the adoption of QC by researchers familiar with classical high-performance computing.

Improving the Accuracy of IR-Level Fault Injection

Fault injection (FI) is a commonly used experimental technique to evaluate the resilience of software techniques for tolerating hardware faults. Software-implemented FI can be performed at different levels of abstraction in the system stack; FI performed at the compiler&#x2019;s intermediate representation (IR) level has the advantage that it is closer to the program being evaluated and is hence easier to derive insights from for the design of software fault-tolerance mechanisms. Unfortunately, it is not clear how accurate IR-level FI is vis-a-vis FI performed at the assembly code level, and prior work has presented contradictory findings. In this article, we perform a comprehensive evaluation of the accuracy of IR-level FI across a range of benchmark programs and compiler optimization levels. Our results show that IR-level FI is as accurate as assembly-level FI for silent data corruption (SDC) probability estimation across different benchmarks and optimization levels. Further, we present a machine-learning-based technique for improving the accuracy of <i>crash</i> probability measurements made by IR-level FI, which takes advantage of an observed correlation between program crash probabilities and instructions that operate on memory address values. We find that the machine learning technique provides comparable accuracy for IR-level FI as assembly code level FI for program crashes.

Using Approximate Computing and Selective Hardening for the Reduction of Overheads in the Design of Radiation-Induced Fault-Tolerant Systems

Fault mitigation techniques based on pure software, known as software-implemented hardware fault tolerance (SIHFT), are very attractive for use in COTS (commercial off-the-shelf) microprocessors because they do not require physical modification of the system. However, these techniques cause software overheads that may affect the efficiency and costs of the overall system. This paper presents a design method of radiation-induced fault-tolerant microprocessor-based systems with lower execution time overheads. For this purpose, approximate computing and selective fault mitigation software-based techniques are used; thus it can be used in COTS devices. The proposal is validated through a case study for the TI MSP430 microcontroller. Results show that the designer can choose among a wide spectrum of design configurations, exploring different trade-offs between reliability, performance, and accuracy of results.

Optical Rectifying Linear Units for Back-Propagation Learning in a Deep Holographic Convolutional Neural Network

We present the design for a bidirectional coherent optical Rectifying Linear Unit (ReLU) device capable of phase thresholding and appropriately rectifying forward-propagating optical-neuron activity and gating optically back-propagating error that will enable the construction of an all-optical deep learning system. The ReLU device can be fabricated in large arrays using high-speed liquid-crystal-on-Silicon (LCoS) smart-pixel technology capable of implementing arrays of feature planes needed for convolutional neural networks. Interferometric detection of the phase of a split-off fraction of the forward-propagating neuron input is used to set the state of the bidirectional switch and gate both the rest of the forward-propagating neuron input as well as the back-propagating error signals. We show how the array of convolutional adaptive interconnections needed for deep learning can be physically implemented and learned in an all-optical multistage dynamic holographically-interconnected architecture using lenslet arrays addressing thick Fourier-plane dynamic holograms. This optical architecture is self-aligned, phase-calibrated, and aberration compensated by using phase-conjugate mirrors to record the dynamic-holographic interconnections in each layer. This system has the potential to achieve a computational throughput approaching that of supercomputer clusters at a much lower energy cost by synergistically combining the analog computational properties of coherent Fourier optics with the hardware fault-tolerance provided by error-driven deep-learning algorithms.

Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network Architecture

With the continuous development of computer and electronics, the idea of artificial intelligence has been integrating into the fault tolerance research. As a valuable and prospective intelligent fault tolerance technique in high reliability and high safety applications, the evolvable hardware fault tolerance technique is becoming an important and widely applicable method. However, this technique confronts two difficult problems: evolved circuit scale and evolution efficiency. Toward these problems, we present a programmable architecture called neural network architecture-based virtual reconfigurable circuit (NNA-VRC), and an evolutionary fault tolerance method based on this programmable architecture. The NNA-VRC-based evolution method simplifies the structure and configuration of programmable architecture, avoids illegal interconnections during the circuit evolution, and implements high level (module level) evolution. The experiments of this paper show that a function module scale circuit is evolved efficiently. Furthermore, NNA-VRC-based evolution method can recovery from many injected fault patterns, behaving a strong feature of fault tolerance.

Leto: verifying application-specific hardware fault tolerance with programmable execution models

Researchers have recently designed a number of application-specific fault tolerance mechanisms that enable applications to either be naturally resilient to errors or include additional detection and correction steps that can bring the overall execution of an application back into an envelope for which an acceptable execution is eventually guaranteed. A major challenge to building an application that leverages these mechanisms, however, is to verify that the implementation satisfies the basic invariants that these mechanisms require---given a model of how faults may manifest during the application's execution. To this end we present Leto, an SMT-based automatic verification system that enables developers to verify their applications with respect to an execution model specification. Namely, Leto enables software and platform developers to programmatically specify the execution semantics of the underlying hardware system as well as verify assertions about the behavior of the application's resulting execution. In this paper, we present the Leto programming language and its corresponding verification system. We also demonstrate Leto on several applications that leverage application-specific fault tolerance

Simulation model of dependability of redundant computer systems with recurrent information recovery

Today’s digital nanotechnology-based information management systems are especially sensitive to highly-energized particles during operation in irradiated areas. This sensitivity is most often manifested in the form of intermittent soft errors, i.e. distortion of information bits in the system’s memory elements with no hardware failure. The cause is in the afterpulses at the output of the logical elements that occur as the result of ionization of the gate area of the transistor’s semiconductor after it is exposed to a highly-energized particle. In order to counter soft errors the system is equipped with self-repair mechanisms that ensure regular replacement of distorted data with correct data. If this approach to design is employed, the significance of dependability analysis of the system under development increases significantly. Since regular occurrence of soft errors is essentially normal operating mode of a system in conditions of increased radiation, dependability analysis must be repeatedly conducted at the design stage, as that is the only way to duly evaluate the quality of the taken design decisions. The distinctive feature of fault-tolerant hardware and software systems that consists in the presence of nonprobabilistic recovery process limits the applicability of the known methods of dependability analysis. It is difficult to formalize the behaviour of such systems in the form of a dependability model in the context of the classic dependability theory that is geared towards the evaluation of hardware structure. As it has been found out, the application of conventional methods of dependability analysis (such as the Markovian model or probabilistic logic) requires making a number of assumptions that result in unacceptable errors in the evaluation results or its inapplicability.Aim. Development of the model and methods of dependability analysis that would allow evaluating the dependability of hardware and software systems with periodic recovery.Results. A simulation model was developed that is intended for dependability evaluation of complex recoverable information management systems. The model is a network of oriented state graphs that allows describing the behaviour of a recoverable system subject to the presence of computation processes and recovery processes that operate according to non-stochastic algorithms. Based on the simulation model, a software tool for dependability analysis was developed that enables probabilistic estimation of dependability characteristics of individual system units and its overall structure by means of computer simulation of failures and recoveries. This tool can be used for comprehensive dependability evaluation of hardware and software systems that involves the analysis of recoverable units with complex behaviour using the developed simulation model, and their operation along with simple hardware components, such as power supplies and fuses, using conventional analytical methods of dependability analysis. Such approach to dependability evaluation is implemented in the Digitek Reliability Analyzer dependability analysis software environment.Practical significance.The application of the developed simulation model and dependability analysis tool at the design stage enables due evaluation of the quality of the produced fault tolerant recoverable system in terms of dependability and choose the best architectural solution, which has a high practical significance.