Hardware Description Language Research Articles

A Field-Programmable Gate Array-Based Quasi-Cyclic Low-Density Parity-Check Decoder with High Throughput and Excellent Decoding Performance for 5G New-Radio Standards

This work presents a novel fully parallel decoder architecture designed for high-throughput decoding of Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes within the context of 5G New-Radio (NR) communication. The design uses the layered Min-Sum (MS) algorithm and focuses on increasing throughput to meet the strict needs of enhanced Mobile BroadBand (eMBB) applications. We incorporated a Sub-Optimal Low-Latency (SOLL) technique to enhance the critical check node processing stage inherent to the MS algorithm. This technique efficiently computes the two minimum values, rendering the architecture well-suited for specific Ultra-Reliable Low-Latency Communication (URLLC) scenarios. We design the decoder to be reconfigurable, enabling efficient operation across all expansion factors. We rigorously validate the decoder’s effectiveness through meticulous bit-error-rate (BER) performance evaluations using Hardware Description Language (HDL) co-simulation. This co-simulation utilizes a well-established suite of tools encompassing MATLAB/Simulink for system modeling and Vivado, a prominent FPGA design suite, for hardware representation. With 380,737 Look-Up Tables (LUTs) and 32,898 registers, the decoder’s implementation on a Virtex-7 XC7VX980T FPGA platform by AMD/Xilinx shows good hardware utilization. The architecture attains a robust operating frequency of 304.5 MHz and a normalized throughput of 49.5 Gbps, marking a 36% enhancement compared to the state-of-the-art. This advancement propels decoding capabilities to meet the demands of high-speed data processing.

An Advanced Hardware Implementation of the Trial Division Algorithm for Dividers Utilizing RISC-V ISA

In this paper, we try to design a divider based on RISC-V instruction set architecture (ISA). Since the hardware design of the divider in the ALU is very important for the CPU to implement the arithmetic function. In view of the advantages of the trial division method in the division algorithm and the popularity of the RISC-V ISA, this paper attempts to design a trial division divider utilizing the RISC-V ISA. In this design, the principle of trial division, flow chart, state diagram, RISC-V instructions of division, whole divider module and logic will be designed in detail. To test the function and feasibility, the hardware description is carried out in the Verilog hardware description language (HDL). In this description, four division RISC-V instructions are integrated. Modelsim is used to verify and test the functionality of the divider. The test waveform is used as a result to verify the feasibility of the divider.

Design and Implementation of a Synchronous AHB to APB Bridge in System-on-Chip Applications

The requirement of effectively combining key units in an integrated system is proliferating. SoC system is developed to provide a chip-level integration, which become the inevitable trend of integrated circuit development and is widely used in smartphones, industrial applications, and microcontrollers. The ARM AMBA protocol works as a universally adopted way of interaction between various parts of the system. In AMBA architecture, the AHB to APB bridge significantly contributes to combining the high-performance AHB bus and low-power APB bus in the SoC system. This project is to implement an AHB to APB bridge using Verilog, enabling stable data transfer between these two buses. The proposed AHB to APB bridge is intended to fit different read or write strategies and ensure the proper working of the peripherals on the APB bus. The bridge has been implemented via Verilog Hardware description language (HDL). A test bench was created with a virtual AHB host and an optimized SRAM as the high-speed APB peripheral. Verdi simulation shows the bridge completely meets the design intention.

Design and Implementation of a 7-Person Voting Device based on Quartus

As the complexity of digital system design continues to increase, efficient and precise decision support systems have become increasingly important. This paper presents the design and implementation of a 7-voter decision system based on Altera’s Quartus software. The voter is applied in the core decision-making process to ensure the accuracy and efficiency of decisions. The study begins by outlining the design principles of the 7-voter decision system, using a design philosophy that minimizes timing delays and optimizes hardware resource utilization. A complex majority voting logic circuit is implemented using high-level hardware description languages (VHDL/Verilog), ensuring the advanced nature and applicability of the voting circuit. In terms of the logical implementation of the voting circuit, the paper conducts an in-depth analysis of the optimization of combinational and sequential logic and standardizes the input and output to enhance the signal stability and the system’s resistance to interference. On the Quartus platform, the design process of the voting system is elaborated in detail, with careful consideration given to boundary conditions and hardware compatibility. The implementation of the voter has undergone rigorous simulation and testing. Strict parameter setting for simulations and waveform analysis confirm the correctness of the circuit, and fault simulation tests further confirm its reliability. Performance indicators such as response time and percentage of resource utilization have been quantitatively analyzed and meet the design objectives set beforehand. Overall, this research not only realizes a highperformance 7-voter decision system but also provides an effective case study for applications on the high-performance Quartus design platform. Future research can build on the current work to further optimize algorithms and hardware, explore the potential for the application of the voter in a broader range of fields, and adapt to the new features of the Quartus platform to achieve more powerful decision support functions.

Design and Implementation of Digital Integrated Circuit Based CPU

This paper presents a simplified 16-bit CPU design and its implementation using digital integrated circuits developed with Verilog hardware description language, while emphasizing simulation through the EDA tool. This design puts more emphasis on the critical roles played by the data path and the control unit, executing key instructions including arithmetic operations such as addition, subtraction, bitwise logic, and conditional jumps. This structurally modular CPU is both functioning and stable in nature, allowing support for future enhancements and enhancements as well, thereby serving as an effective model towards an understanding of the principles of CPU design. The execution of these basic instructions puts the core of the CPU under test and reaffirms its proper operation in respect of the detailed instruction set, while its extensibility design confirms further improvement possibilities for future complex instructions as well as finite-state machine optimization for the control unit. The present work not only proves the possibility of creating a fully working CPU, using readily available bare minimum resources to implement a prototype, but is also a breakthrough in future research with CPU architecture. The obtained results will shed light on CPU functionality optimization and extension, being the ground for building more powerful and effective processors in the future.

DeLoSo: Detecting Logic Synthesis Optimization Faults Based on Configuration Diversity

Logic synthesis tools are the core components of digital circuit design, which convert programs written in hardware description languages into gate-level netlists, and optimize the netlists. However, the netlist optimization is complex, with numerous optimization parameters to be configured. Any minor optimization faults in logic synthesis tools may cause circuit diagrams to significantly deviate from the original design, posing risks in target systems. We propose DeLoSo, the De tector of Lo gic S ynthesis o ptimization faults, the first method specifically designed to identify potential faults in the optimization processes of logic synthesis tools. DeLoSo relies on netlist differences and parameter variations to guide the generation of diverse Logic Synthesis Optimization Configuration (LSOC) combinations to thoroughly test the optimization process. DeLoSo consists of three components: LSOC generator, which generates diverse LSOC combinations through configuration recombination and mutation; LSOC diversity evaluator, which assesses the diversity of optimization configurations; and LSOC validator, which validates the generated LSOC combinations to discover optimization faults. DeLoSo identified 19 faults in two established logic synthesis tools (i.e., Vivado and Yosys); 15 of them have been fixed by vendors. Particularly, the community maintainers of Yosys have considered incorporating DeLoSo into Yosys’ existing test suite.

Hardware-accelerated neural network model for early prediction of sudden cardiac arrest based on heart rate variability metrics

AbstractSudden Cardiac Arrest (SCA) constitutes a dire medical condition, marked by the abrupt cessation of effective blood circulation due to the heart's failure to contract properly. This leads to acute circulatory collapse, often culminating in loss of consciousness within an hour and potentially resulting in fatality within minutes if left unattended. Heart rate variability (HRV) serves as a critical biometric, derived from electrocardiogram (ECG) signals with ventricular depolarization waves to further calculate the R-R Intervals (RRIs). These intervals provide the basis for extracting various characteristics of cardiac rhythm, encompassing time-domain, frequency-domain, and nonlinear features. This study presents a neural network-based classification algorithm that leverages HRV metrics to categorize patients into SCA and Normal Sinus Rhythm (NSR) cohorts. The proposed neural network (NN) model showcased impressive results, achieving an accuracy of 96.23%, a sensitivity of 94.35%, and a specificity of 98.12% in detecting SCA, as evaluated through leave-one-subject-out analysis. In order to harness the benefits of hardware acceleration, the algorithm is implemented on a Field-Programmable Gate Array (FPGA). Its computational efficiency is subsequently benchmarked against traditional software-based methodologies. The hardware-level implementation is made possible in Verilog hardware description language (HDL) and was verified successfully with expected performance by register-transfer level (RTL) simulation via Vivado 2020.2.

Increasing the speed of digital devices using the ASMD-FSMD method using non-blocking operators

The ASMD-FSMD method for designing digital devices is considered, which consists of constructing a block diagram of an algorithmic state machine with a data path (ASMD), which describes the behavior of the device, and creating project code in Verilog in the form of a finite state machine with a data processing path. (finite state machine with datapath – FSMD). One of the directions for the development of the ASMD-FSMD methodology is the use of features of the hardware description language (HDL). A hypothesis has been put forward: in the ASMD-FSMD technique, it is possible to apply several non-blocking assignment operators to the same variable in one synchronization cycle, which will lead to an increase in device performance. The hypothesis put forward was investigated in the design of synchronous multipliers that implement the classical multiplication algorithms c and d. Experimental studies have confirmed the validity of the put forward hypothesis, while the speed of the multipliers increases two to three times, and the cost of implementation in most cases decreases compared to the traditional approach.

UART IP core Design and Verification using WISHBONE Interface

The organization of communication between the devices is greatly aided by the communication protocol. These protocols have a clear set of guidelines that have been agreed upon by the tools needed for effective communication. A popular protocol for serial communication is UART. The hardware description language for the SV/Verilog UART functional module is designed in this paper. The serial connection capabilities offered by this UART IP CORE enable interaction with modems and other external devices. The Universal Verification Technique is used to undertake functional verification of the UART. By comparing the collected response to the intended response via the scoreboard mechanism, the reusable UVM test bench architecture is meant to push the randomized stimuli to the unit under test to assess the functional correctness. This core is made to be as compatible as possible with commercially accepted designs. The WISHBONE INTERFACE WITH 8-BIT OR 32-BIT SELECTABLE DATA BUS MODES is one of this design's primary characteristics. Interface debugging in 32-bit data bus mode. Functionality and register-level compatibility. FIFO procedure. The UVM methodology is used to validate the design. For optimal functional coverage, the test bench is written with regression test cases. The overall execution time will be shortened if the stimulus may be reused.

An efficient XOR-free implementation of polar encoder for reconfigurable hardware

— This paper presents a novel approach to implementing an XOR-Free architecture of the non-systematic polar encoder (NSPE) for 5G radio. The optimization of XOR logic for hardware (HW) implementation is essential to reduce delay and power consumption. The proposed architecture for NSPE replaces XOR operations with combinational logical patterns, and some redundant patterns are removed with the help of bit manipulation to make it more efficient. The design infers multiplexers (2:1 or 4:1) and inverters as its functional units, making the design adequate and effective in alleviating HW complexity. The XOR-Free encoder performs the same functionality as the XOR-based conventional encoder. We have written a MATLAB script that generates Verilog hardware description language (HDL) code for fully or partially parallel polar encoders tailored to specific code lengths (N) and degrees of parallelism (M). A comparative analysis of various fully and partially parallel encoders with the XOR-Free algorithm is presented. The implementation results show that the proposed architectures are more efficient in terms of HW cost, power consumption, throughput, and latency.

Generic FPGA Pre-Processing Image Library for Industrial Vision Systems.

Currently, there is a demand for an increase in the diversity and quality of new products reaching the consumer market. This fact imposes new challenges for different industrial sectors, including processes that integrate machine vision. Hardware acceleration and improvements in processing efficiency are becoming crucial for vision-based algorithms to follow the complexity growth of future industrial systems. This article presents a generic library of pre-processing filters for execution in field-programmable gate arrays (FPGAs) to reduce the overall image processing time in vision systems. An experimental setup based on the Zybo Z7 Pcam 5C Demo project was developed and used to validate the filters described in VHDL (VHSIC hardware description language). Finally, a comparison of the execution times using GPU and CPU platforms was performed as well as an evaluation of the integration of the current work in an industrial application. The results showed a decrease in the pre-processing time from milliseconds to nanoseconds when using FPGAs.

FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively.

Hardware circuit implementation of transmitter and receiver based on UART protocol

In today's information age, the amount of data as an important information carrier is growing at an explosive rate. The importance of its transmission rate, stability, accuracy and other properties is gradually becoming more and more important. UART as a communication protocol is widely used in embedded and IoT systems. It is simpler and more direct than SP2 and I2C, which can greatly simplify the complexity of digital circuits and become one of the key directions to improve the performance of data transmission. In this paper, a digital circuit based on the transmitter and receiver side of the UART protocol has been constructed using the hardware description language of Verilog HDL to implement the function of receiving and transmitting data based on a clock signal of 50 MHz and a baud rate of 115200 bps as well as the use of an RS232 asynchronous serial interface. The simulation was carried out using Quartus II.

HDLRuby: A Ruby Extension for Hardware Description and Its Translation to Synthesizable Verilog HDL

HDLRuby is a new hardware description language defined as an extension of the Ruby programming language aiming to improve circuit design productivity. HDLRuby allows to model digital circuits at the register transfer level while supporting high-level paradigms comprising object-oriented programming, genericity, metaprogramming, and reflection. By construction, HDLRuby can also execute any code in Ruby and supports all of its libraries. Yet, even if high-level features are beneficial for design productivity, such advantages can be negated if the design tools are not efficient enough for producing in reasonable time quality hardware. This article investigates this issue by presenting the techniques used for compiling HDLRuby descriptions and by evaluating their performance. In detail, it explains how the language has been implemented and how it is translated to synthesizable Verilog HDL. Experiments are then presented for confirming the productivity gain of using HDLRuby and for evaluating the performance of the translation, the size of the resulting code, and the time required by a commercially available synthesis tool to produce an FPGA configuration from it. The HDLRuby descriptions used for the experiments include a set of repetitive designs for single construct evaluations and the implementation of generic convolution neural networks for real-life applications. For these evaluations, the translation time proves to be more than 10 times shorter than the synthesis time.

Field-programmable gate array implementation of efficient deep neural network architecture

Deep neural network (DNN) comprises multiple stages of data processing sub-systems with one of the primary sub-systems is a fully connected neural network (FCNN) model. This fully connected neural network model has multiple layers of neurons that need to be implemented using arithmetic units with suitable number representation to optimize area, power, and speed. In this work, the network parameters are analyzed, and redundancy in weights is eliminated. A pipelined and parallel structure is designed for the fully connected network information. The proposed FCNN structure has 16 inputs, 3 hidden layers, and an output layer. Each hidden layer consists of 4 neurons and describes how the inputs are connected to hidden layer neurons to process the raw data. A hardware description language (HDL) model is developed for the proposed structure and the verified model is implemented on Xilinx field-programmable gate array (FPGA). The modified structure comprises registers, demultiplexers, weight registers, multipliers, adders, and read-only memory lookup table (ROM/LUT). The modified architecture implemented on FPGA is estimated to reduce area by 87.5% and improve timing by 3x compared with direct implementation methods.

Design of digital frequency meter based on FPGA

Frequency measurement is one of the key technicals of the electronic measurement field, and the digital frequency meter is an indispensable measuring tool for measuring technology engineering personnel. Nowadays, digital frequency meters are indispensable components in daily appliances such as televisions, refrigerators, washing machines, and other smart home appliances. Therefore, the measurement range of digital frequency meters is becoming wider, and their design structures are becoming increasingly complex. Digital frequency meters play a crucial role in developing electronic products as a whole. Use the Very High-speed Hardware Description Language (VHDL) in Electronic Design Automation(EDA)technology to simulate and verify the digital frequency meter. Through simulation analysis, design the measurement circuit of the digital frequency meter and verify its accuracy. In the design process of a digital frequency meter, its function is to measure SIN signals, unit pulse signals, and the frequency range of various signals, achieved by collecting physical quantities within a unit of time.

The application of Verilog in the development of casual games

Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and intelligence in modern society. As digital technology continues to advance across various industries, the need for effective and dependable digital circuit design languages is also increasing. This paper delves into the complex process of recreating the timeless arcade classic Pac-Man on the Spartan 3E FPGA platform using hardware description and digital circuit techniques and the Verilog programming language. Through a comprehensive review of existing literature and research, this study investigates the fusion of traditional game design principles with state-of-the-art hardware programming methods, demonstrating the seamless integration of software-driven game mechanics with hardware-based implementation. Through careful design and coding strategies, Pac-Man's basic functionality, such as maze traversal, ghost AI, and pellet consumption, is faithfully replicated using Verilog modules customized for the Spartan 3E FPGA board. By bridging the realms of game development and hardware engineering, this paper not only showcases the versatility of Field Programmable Gate Array (FPGA) technology in entertainment applications but also underscores the interdisciplinary nature of modern computing endeavours.

Automated design of embedded digital signal processing systems on SOC platform

The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The aim of the study is to develop models and procedures for determining the possibilities of a compromise distribution of signal processing algorithm computations in the cycle of computer-aided design on the SoC technology platform in terms of performance and the feasibility of using hardware and software algorithms realization. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of system-on-chip systems; development of procedures for computer-aided design and analysis of signal processing systems using programming languages and hardware description languages for the implementation of embedded systems. The following methods are being used: implementation of digital signal processing algorithms in the C programming language and high-level synthesis tools for realizing IP blocks, diagnostic experiment by generating test signal patterns, and analysis of the processing results at the system output. The results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of the audio spectrum signal processing system is designed. The practical implementation was performed based on the Vivado/Vitis/Vitis HLS CAD tool stack. The proposed model was verified using a programmable test signal generator and analyzing the obtained characteristics of digital filters at the system output. Conclusions. The article analyzes the principles of designing embedded information processing systems implemented in system-on-chip. The principles of building and analyzing digital signal processing systems based on system-on-chip containing programmable logic and processor parts are considered. The developed methods have been tested on the algorithms of CIC and FIR filters on the technological platform of SoC FPGA of the ZYNQ-7000 family of Xilinx company.

FPGA in hardware description language based digital clock alarm system with 24-hr format

Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.