Hardware Blocks Research Articles

A Vector Quantization-Based Spike Compression Approach Dedicated to Multichannel Neural Recording Microsystems.

Implantable high-density multichannel neural recording microsystems provide simultaneous recording of brain activities. Wireless transmission of the entire recorded data causes high bandwidth usage, which is not tolerable for implantable applications. As a result, a hardware-friendly compression module is required to reduce the amount of data before it is transmitted. This paper presents a novel compression approach that utilizes a spike extractor and a vector quantization (VQ)-based spike compressor. In this approach, extracted spikes are vector quantized using an unsupervised learning process providing a high spike compression ratio (CR) of 10-80. A combination of extracting and compressing neural spikes results in a significant data reduction as well as preserving the spike waveshapes. The compression performance of the proposed approach was evaluated under variant conditions. We also developed new architectures such that the hardware blocks of our approach can be implemented more efficiently. The compression module was implemented in a 180-nm standard CMOS process achieving a SNDR of 14.49[Formula: see text]dB and a classification accuracy (CA) of 99.62% at a CR of 20, while consuming 4[Formula: see text][Formula: see text]W power and 0.16[Formula: see text]mm2 chip area per channel.

Anemia Diagnostic System Based on Impedance Measurement of Red Blood Cells.

Anemia is a condition in which red blood cells or the hemoglobin in the blood is lower than in healthy people. Red blood cells transport and supply oxygen needed to various organs in the human body. Anemia is caused by hypoxemia due to the lack of red blood cells and causes other serious health problems, such as heart problems, pregnancy complications, severe fatigue, or death. There are many causes of anemia, and it can be diagnosed by measuring hematocrit or hemoglobin levels in the blood. Even though there are various diagnostic devices on the market, these devices are inconvenient because their systems are bulky, heavy, expensive, or inaccurate. This study proposed a new anemia diagnostic system based on the impedance measurement of red blood cells. The proposed system consists of a test strip that collects a blood sample from the finger and a hemoglobin meter that measures the impedance of the blood and converts it into the concentration of hemoglobin. The proposed test strip that does not contain enzymes or reagents was designed in accordance with class 1 approval by the Food and Drug Administration (FDA). The hemoglobin meter was designed to include a hardware block, an algorithm block and a calibration block through empirical work. We also compared it to reference impedance to prove the accuracy of the hemoglobin meter. The experimental results with human blood indicated the superiority of the anemia diagnostic system. As a result, the overall standard deviation of impedance measurements was less than 1%, and the coefficient of variance of the proposed system was 1.7%, which was better than that of other commercial systems.

Image processing using a reconfigurable platform: Pre-processing block hardware architecture

<p class="CM12">Real time image processing is a challenging task in which fetching the sub image requires offset memory access apart from core processing needs. This paper aims at overcoming the offset needs for memory addressing in pre-processing blocks. Another feature of this present work is to appending the image data with customized algorithmic reequipments viz duplicating, zero padding. For KxK kernel size, the proposed hardware architecture can be programmed to fetch K pixels in one cycle, reducing the data access time. Results have been compared with software-based processing for KxK spatial filtering. performance indicates significant timing improvement using proposed pre-processing hardware block.</p>

Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC

FPGA-SoCs are heterogeneous embedded computing platforms consisting of reconfigurable hardware and high-performance processing units. This combination offers flexibility and good performance for the design of embedded systems. However, allowing the sharing of resources between an FPGA and an embedded CPU enables possible attacks from one system on the other. This work demonstrates that a malicious hardware block contained inside the reconfigurable logic can manipulate the memory and peripherals of the CPU. Previous works have already considered direct memory access attacks from malicious logic on platforms containing no memory isolation mechanism. In this work, such attacks are investigated on a modern platform which contains state-of-the-art memory and peripherals isolation mechanisms. We demonstrate two attacks capable of compromising a Trusted Execution Environment based on ARM TrustZone and show a new attack capable of bypassing the secure boot configuration set by a device owner via the manipulation of Battery-Backed RAM and eFuses from malicious logic.

Software for Calculating Deformations of the Earth's Surface using Satellite Radar Data

The article presents a description of a software package for calculating displacement rates and detecting displacements of the earths surface over areas of intensive coal mining. The complex is built on the basis of the microservice architecture Docker Swarm in integration with the system of massively parallel execution of tasks Apache Spark, as a high-level tool for organizing container-type computations with orchestration of hardware resources. In the software package, the container is used as an element of the sequence of calculation stages of the mathematical model of interferometric processing, presented in the form of a managed service. The service itself is built on the basis of a microkernel of the specified operating system, with support for multitasking of process identifiers and network protocols. Due to the use of containerization of executor objects, the independence of calculations is achieved both within one pool of jobs and between different pools initialized in multi-user mode. The use of the cluster resource manage­ment system and YARN job scheduling made it possible to abstract all the computing resources of the cluster from the specific launch of jobs and to provide dispatching of distributed processing applications. The use in the program code based on the Sentinel-1 Toolbox of the possibility of storing the intermediate results of the operation of procedures in the schemes for calculating the displacement rates makes it possible to carry out calculations with various parameters, and parallelization provides a reduction in the calculation time in comparison with commercial software products. The combination of Docker Swarm and Apache Spark technologies in one software package made it possible to implement the idea of a high-performance computing system based on open source software and cross-platform programming languages Java and Python using low-budget hardware blocks, including those made in Russia.

Intelligent support of logistics missions in medical institutions by mobile service robots AMUR-307

Technologies of missions’ generation for the mobile robots (MR) Amur-307 by the parallelized automatic scheduler and their implementation by the integration software (SW) with the hardware block (HB) on 6 power channels (6x30A), with the branched sensorics are considered. The program generator is forming the tasks in the PDDL language based on the route map in vector graphic format, parameters of objects moved by robots, and equipment installed on robots. The developed plan is implemented by the HB and the navigation control program, based on topological information extracted from the map, based on passive oriented visual markers installed in the walls. The robot can work both in real and in virtual environments, using the Webots emulator and/or relying on its own original developments.

Graceful Degradation of Reconfigurable Scan Networks

Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible access to these instruments is offered by reconfigurable scan networks (RSNs), e.g., IEEE Std. 1687. As RSNs themselves can become faulty, there is a need to exclude and bypass faulty parts so that remaining instruments can be used. To avoid keeping track and updating description languages for each individual IC, we propose an on-chip hardware block that makes adjustments according to the fault status of a particular IC. We show how this block enables test for faulty scan chains, localization of faulty scan chains, and repair by excluding faulty scan chains. We made implementations and experiments to evaluate the overhead in terms of transported data and area.

Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy

Approximate computing trades off computation accuracy against energy efficiency. The extent of approximation tolerance, however, significantly varies with a change in input characteristics and applications. We propose a novel cross-layer approach for the synthesis of runtime accuracy-configurable hardware that minimizes energy consumption at area expense. To that end, first, we explore instantiating multiple hardware blocks in the architecture with different fixed approximation levels. These blocks can be selected dynamically and thus allow to configure the accuracy during runtime. They benefit from having fewer transistors and also synthesis relaxations in contrast to state-of-the-art gating mechanisms that only switch off a group of paths of the circuit. Our cross-layer approach combines instantiating such blocks in the architecture with area-efficient gating mechanisms that reduce toggling activity, creating a fine-grained design-time knob on energy versus area. We present a systematic methodology to explore this joint design space and find energy-area optimal solutions as a function of required accuracies, their utilization in the workload, together with hardware parameters: dynamic power savings, area of the hardware block, and leakage of the technology. Examining total energy savings for a range of circuits under different workloads and accuracy tolerances shows that our method finds Pareto-optimal solutions providing up to 32% and 60% energy savings compared to state-of-the-art accuracy-configurable gating mechanism and an exact hardware block, respectively, at 2× area cost.

Архитектура программного обеспечения для задач взаимодействия контроллера вывода на экран и операционной системы

Article describes solutions for developing programs that provide interaction between Linux operating system and multiple display controller hardware blocks (outputs), that use one clock generation IP-block with phase-locked loop (PLL). There is no API for such devices in Linux, thus new software model was developed. This model is based on official Linux GPU developer driver model, but was modified to cover case described earlier. Article describes three models for display controller driver development – monolithic, component and semi-monolithic. These models cannot cover case described earlier, because they assume that one clock generator should be attached to one output. A new model was developed, that is based on component model, but has additional mechanics to prevent race condition that can happen while using one clock generator with multiple outputs. Article also presents modified model for bootloaders graphics drivers. This model has been simplified over developed Linux model, but also has component nature (with less components) and race prevention mechanics (but with weaker conditions). Hardware interaction driver components that are developed using provided software models are interchangeable between Linux and bootloader.

Evaluation of semi-frozen semi-fixed neural network for efficient computer vision inference

Deep neural networks have been utilized in an increasing number of computer vision tasks, demonstrating superior performance. Much research has been focused on making deep networks more suitable for efficient hardware implementation, for low-power and low-latency real-time applications. In [1], Isikdogan et al. introduced a deep neural network design that provides an effective trade-off between flexibility and hardware efficiency. The proposed solution consists of fixed-topology hardware blocks, with partially frozen/partially trainable weights, that can be configured into a full network. Initial results in a few computer vision tasks were presented in [1]. In this paper, we further evaluate this network design by applying it to several additional computer vision use cases and comparing it to other hardware-friendly networks. The experimental results presented here show that the proposed semi-fixed semi-frozen design achieves competitive performanc on a variety of benchmarks, while maintaining very high hardware efficiency.

An Analysis on Low Cost and Performance of Hardware and Software Oriented Lightweight Block Ciphers for IoT Applications

The number of equipment or devices that are connected to the internet for data sharing/ storage analysis increases abundantly with the advancement in the field of Internet-of-Things, where security, especially the confidentiality of sensitive data shared by the resource constrained devices is one of the major concerns. Lightweight cryptography is currently evolving as the major security field for low energy devices. This paper made an analytical survey on various hardware and software-oriented lightweight block ciphers with respect to their cost and performance, security aspects of lightweight ciphers are not considered. The evaluation metrics used for analysis are throughput, area, cycles per block, energy, and power consumption. As per the analysis SPECK and SIMON are assessed as the best cipher in in terms of throughput. Whereas the lightweight encryption algorithms SPECK and GIFT shows increased efficiency with respect to low-cost analysis.

DESIGN OF A LOW LATENCY ROUTER FOR ON-CHIP NETWORKS

A problem with long on-chip wires is the resulting delays, and repeater insertion becomes essential to mitigate this problem. Point-to-point wiring leads to an increase in the area and repeater insertion leads to an increase in power consumption. The complexity of System-on-Chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. The properties of our OCN are now reviewed. The OCN provides reliable communication. This is achieved by ensuring that data dropping is not allowed. On-Chip Network’s (OCN’s) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router. We present a prototype design of a 5-input, 5-output, scalable router. The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN.

Design, Implementation, and Analysis of High-Speed Single-Stage N-Sorters and N-Filters

There is strong interest in developing high-performance hardware sorting systems which can sort a set of elements as quickly as possible. The fastest of the current FPGA systems are sorting networks, in which sets of 2-sorters operate in parallel in each series stage of a multi-stage sorting process. A 2-sorter is a single-stage hardware block which sorts two values, so any list with more than 2 values must be sorted with a series network of 2-sorters. A primary contribution of this work is to provide a general methodology for the design of stable single-stage hardware sorters which sort more than 2 values simultaneously. This general methodology for $N$ -sorter design, with $N{>}2$ , is then adapted for use in modern FPGAs, where it is shown that single-stage 3-sorters up to 9-sorters have speedup ratios from 2.0 to 3.5 versus the comparable state-of-the-art 2-sorter networks. A design system modification is shown to produce even faster single-stage $N$ -max and $N$ -min filters. When used for max pooling 32-bit data in the fastest analyzed FPGA, a single 9-max filter will process 500 million 9-pixel groups per second (4K:3840x2160 at 500 frames/second). The single-stage 9-median filter using this design methodology, useful in image processing, is shown to have speedup ratios of 3.0 to 4.1 versus state-of-the-art FPGA network implementations, even though its resource usage is comparable to, often better than, the network implementations. Ten 8-bit 9-median filters operating in parallel in the fastest FPGA will process over 5.4 billion pixels/sec (4K at over 600 frames/second).

RNNFast

Recurrent Neural Networks (RNNs) are an important class of neural networks designed to retain and incorporate context into current decisions. RNNs are particularly well suited for machine learning problems in which context is important, such as speech recognition and language translation. This work presents RNNFast, a hardware accelerator for RNNs that leverages an emerging class of non-volatile memory called domain-wall memory (DWM). We show that DWM is very well suited for RNN acceleration due to its very high density and low read/write energy. At the same time, the sequential nature of input/weight processing of RNNs mitigates one of the downsides of DWM, which is the linear (rather than constant) data access time. RNNFast is very efficient and highly scalable, with flexible mapping of logical neurons to RNN hardware blocks. The basic hardware primitive, the RNN processing element (PE), includes custom DWM-based multiplication, sigmoid and tanh units for high density and low energy. The accelerator is designed to minimize data movement by closely interleaving DWM storage and computation. We compare our design with a state-of-the-art GPGPU and find 21.8× higher performance with 70× lower energy.

Automating Analogue AI Chip Design with Genetic Search

Optimization of analogue neural circuit designs is one of the most challenging, complicated, time‐consuming, and expensive tasks. Design automation of analogue neuromemristive chips is made difficult by the need to design chips at low cost, ease of scaling, high‐energy efficiency, and small on‐chip area. The rapid progress in edge AI computing applications generates high demand for developing smart sensors. The integration of high‐density analogue computing AI chips as coprocessing units to sensors is gaining popularity. This article proposes a hardware–software codesign framework to speed up and automate the design of analogue neuromemristive chips. This work uses genetic algorithms with objective functions that take into account hardware nonidealities such as limited precision of devices, the device‐to‐device variability, and device failures. The optimized neural architectures and hyperparameters successfully map with the library of relevant neuromemristive analogue hardware blocks. The results demonstrate the advantage of proposed automation to speed up the analogue circuit design of large‐scale neuromemristive networks and reduce overall design costs for AI chips.

Analysis of Intelligent Pick-up Terminal Based on Mobile Internet

Given the problems of low work efficiency, misplaced delivery and pick-up time, difficulty to build brand image, etc. in the logistics industry, a design scheme for intelligent pick-up terminal based on the mobile Internet is proposed. Firstly, the current status of the last mile delivery in the logistics industry is introduced. Various problems in the distribution are identified. Subsequently, the system architecture, hardware block diagram, and software flowchart of the design are described. The design has implemented intelligent distribution, which can improve logistics distribution efficiency and establish the brand image effectively.

Deep Convolutional Neural Network based Detection System for Real-time Corn Plant Disease Recognition

Corn is one of the most popular food grains in the India and crop loss due to diseases substantially affects the Indian economy and threatens the food availability. Recent access of smart devices can be utilized to provide automatic diagnosis of corn diseases and prevent severe crop losses. This paper presents a real time method based on deep convolutional neural network for corn leaf disease recognition. Deep neural network performance is improved by tuning the hyper-parameters and adjusting the pooling combinations on a system with GPU. Further, the number of parameters of the developed model is optimized to make it suitable for real time inference. The pre-trained deep CNN model was deployed onto raspberry pi 3 using Intel Movidius Neural Compute Stick consisting dedicated CNN hardware blocks. During the recognition of corn leaf diseases, the deep learning model achieves an accuracy of 88.46% demonstrating the feasibility of this method. The presented corn plant disease recognition model is capable of running on standalone smart devices like raspberry-pi or smart-phone and drones.

Transverse horizontal vibrations of contact network wires for monitoring their tension during operation

The paper describes the structure of a hardware and software complex for monitoring and diagnostics of the contact network, provides information about the hardware blocks of the complex, considers its implementation in Matlab/Simulink, describes the regularities of change of vibration frequency under different values of tension and the linear mass of wires.

A novel majority based imprecise 4:2 compressor with respect to the current and future VLSI industry

Imprecising the arithmetic hardware blocks is well known as one of the brilliant approaches that increase the performance of digital signal processors (DSP) at the cost of imposing some acceptable errors. Making a trade-off between the performance and the enormous results of a given system is a challenge which has attracted the interest of many researchers in recent years. In this paper, we focus on the design of an imprecise 4:2 compressor which lies at the heart of inexact multipliers. The proposed imprecise 4:2 compressor by utilizing only one majority gate brings significant efficiency in implementation of today's technologies like FinFET and future majority based emerging technologies such as QCA. The evaluation results in both of aforesaid technologies demonstrate the remarkable improvement of the proposed design compared to related works. In addition, employing the proposed imprecise 4:2 compressor in an image processing application confirms the qualitative acceptability of the proposed design.

A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders

A cross-layer design space exploration (DSE) method based on a proposed co-simulation technique is presented herein. The proposed method is demonstrated evaluating the impacts on both coding efficiency and power dissipation of applying distinct approximate logic operators in a s $\mu {\mathrm{ m}}$ of absolute differences (SAD) kernel that accelerates an H.265/HEVC (high-efficiency video coding) encoder. The proposed method simulates the gate-level circuit dynamically inside the application, with realistic results of the impact of the adder-tree approximate logic implementation on both quality and encoder bit-rate results. A comprehensive DSE is shown herein, with 13 types of 6 classes of approximate adders in the SAD accelerator hardware blocks. Over 3,000 logic variants of approximations at gate-level were developed. Actual video sequences as inputs to the x265 software encoder are co-simulated, to dynamically capture the video motion-estimation (ME) behavior in the presence of logic approximations. While the prior art that only estimates the impact of the approximate logic on power, area, and quality on static designs with statistical assumptions, which are agnostic to the actual algorithm data-dependent behavior in the application, our method explores accurately the trade-off between power dissipation and coding efficiency dynamically over the entire HEVC encoding. Our approach shows that the lower-part-or and error-tolerant adder I approximate adders, as well as truncation-to-zero deliver better compression-power trade-offs, with substantial differences from the static analysis.