Hardware Blocks Research Articles

Investigating Applications in Health Care [Book\Software Reviews

This book explains the multiple directions in which RF/microwave technologies are heading toward healthcare and biosensing applications, the achievements that have been made so far, and the challenges for researchers to solve in the near future. It consists of seven chapters by 15 authors, many of whom are active on the IEEE Microwave Theory and Techniques Society (MTT-S) Technical Coordinating Committee MTT-10, Biological Effects and Medical Applications. Apart from the first two chapters (which are tutorials on microwave technology and the dielectric properties of tissue), the book consists of five chapters that review different applications of RF/microwave energy to health care and biosensing. This book provides essential theories and solutions for the transmitter and receiver hardware block. The solutions offered are very practical for a circuit system designer. Whether the particular applications of RF/microwaves discussed in this volume will ever pass muster and enter the realm of evidence-based medicine remains to be seen. In their focus on the nuts and bolts of engineering, the authors of this otherwise meritorious volume are telling only a small part of the story about developing medical technology.

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

Designing and Implementing a Novel Single IFFT Scrambling PAPR Reduction Scheme in OFDM Systems Using FPGA with Hardware Co-simulation

This paper presents a novel low complexity technique for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on field programmable gate array. In this technique, the output of inverse fast Fourier transforms (IFFT) is partitioned into M subblocks, which are subsequently interleaved. Then, a new optimization scheme is introduced in which only a single two phase sequence need to be applied. Unlike the conventional partial transmit sequence (C-PTS) which needs M-IFFT blocks and $$W^{M-1}$$ iterations, the proposed technique requires only a single IFFT block and M iterations. These features significantly reduce processing time and less computation that leads to reduced complexity. Simulation results demonstrate that the new technique can effectively reduce the complexity up to 99.95% compared with the conventional PTS (C-PTS) technique and yields good PAPR performance. The good PAPR performance arises from the effect of both the data interleaving and the new optimization technique. Through the comparison of performance between simulation and hardware, it is distinctly illustrated that the designed hardware block diagram is as workable as the simulation, and the difference of the result is only 0.1 dB.

Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure

In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during standby operations, the value of which depends on the threshold voltage of the CMOS devices in a power-gated design (PGD). It does not require any distributed sensors, because the virtual-power-network is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal standby operations and a processing block for estimating the BTI aging status of the PGD according to collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating minimum idle time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than $1.3\times $ and $1.45\times $ the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65 nm CMOS technology.

Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip

In this paper, experimental methods are emphatically described for measuring the proton single event effects (SEE) in Xilinx Zynq-7010 system-on chip. Experimental data are presented showing that low energy (3MeV≤Energy≤10MeV) proton irradiation can cause single event effects in different hardware blocks of Xilinx Zynq-7010 SoC, including D-Cache, programmable logic (PL), arithmetic logical unit (ALU), float point unit (FPU) and direct memory access (DMA). Moreover, the sensitivities of different hardware blocks to single event effects are different. Finally, the Stopping and Range of Ions in Matter (SRIM) software calculations show the possible reasons for this difference.

Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA

This paper presents a novel low-complexity technique for reducing the Peak-to-Average Power Ratio (PAPR) in Orthogonal Frequency Division Multiplexing (OFDM) systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on a Field Programmable Gate Array (FPGA). In this technique, each subblock is interleaved with the others, and a new optimisation scheme is introduced in which the number of iterations is equal only to the number of subblocks, which results in reduced processing time and less computation that, in turn, leads to reduced complexity. Furthermore, the proposed method focuses on simplifying the required hardware resources. Thus, it can be easily combined with other simplified techniques. The simulation results demonstrate that the new technique can effectively reduce the complexity up to 98.22% compared with the new existing Partial Transmit Sequence (PTS) techniques and yield a good Bit Error Rate (BER) performance. Through the comparison of performance between simulation and hardware, it is distinctly illustrated that the designed hardware block diagram is as workable as the simulation and the difference of the result is only 0.1 dB.

Modelling of Algorithms for Solar Panels Control Systems

The best way to maximize the production of solar energy systems is implementing control systems with effective sun tracking algorithms. The article deals with the hardware implementation of algorithms for moving solar panels. Algorithm's analyse was conducted, as well as the effectiveness of the method of the controller maximum points. The algorithm hardware block realized in hardware description language Verilog submitted. Received decisions are supposed to be used in the knowledge base of intelligent solar batteries control system.

Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA

This paper presents a novel low-complexity technique for reducing the Peak-to-Average Power Ratio (PAPR) in Orthogonal Frequency Division Multiplexing (OFDM) systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on a Field Programmable Gate Array (FPGA). In this technique, each subblock is interleaved with the others, and a new optimisation scheme is introduced in which the number of iterations is equal only to the number of subblocks, which results in reduced processing time and less computation that, in turn, leads to reduced complexity. Furthermore, the proposed method focuses on simplifying the required hardware resources. Thus, it can be easily combined with other simplified techniques. The simulation results demonstrate that the new technique can effectively reduce the complexity up to 98.22% compared with the new existing Partial Transmit Sequence (PTS) techniques and yield a good Bit Error Rate (BER) performance. Through the comparison of performance between simulation and hardware, it is distinctly illustrated that the designed hardware block diagram is as workable as the simulation and the difference of the result is only 0.1 dB.

Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware

Radiation-induced single bit upsets (SBUs) and multi-bit upsets (MBUs) are more prominent in Field Programmable Gate Arrays (FPGAs) due to the presence of a large number of latches in the configuration memory (CM) of FPGAs. At the same time, SBUs and MBUs in the CM can permanently or temporarily affect the hardware circuit implemented on FPGA. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from permanent faults arising due to such SBUs and MBUs. Different existing techniques used to mitigate the effect of soft errors in FPGA have high overhead and their implementations are also quite complex. In this paper, we have proposed efficient single bit as well as multi-bit error correcting methods to correct errors in the CM of FPGAs using simple parity equations and Erasure code. These codes are easy to implement, and the needed decoding circuits are also simple. Use of Dynamic Partial Reconfiguration (DPR) along with a simple hardware scheduling algorithm based download manager helps to perform the error correction in the CM without suspending the operations of the other hardware blocks. We propose a first of its kind methodology for novel transient fault correction using efficient error correcting codes with hardware scheduling for FPGAs. To validate the design we have tested the proposed methodology with Kintex FPGA. We have also measured different parameters like fault recovery time, power consumption, resource overhead and error correction efficiency to estimate the performance of our proposed methods.

Universal Verification Methodology Based Register Test Automation Flow.

In today's SoC design, the number of registers has been increased along with complexity of hardware blocks. Register validation is a time-consuming and error-pron task. Therefore, we need an efficient way to perform verification with less effort in shorter time. In this work, we suggest register test automation flow based UVM (Universal Verification Methodology). UVM provides a standard methodology, called a register model, to facilitate stimulus generation and functional checking of registers. However, it is not easy for designers to create register models for their functional blocks or integrate models in test-bench environment because it requires knowledge of SystemVerilog and UVM libraries. For the creation of register models, many commercial tools support a register model generation from register specification described in IP-XACT, but it is time-consuming to describe register specification in IP-XACT format. For easy creation of register model, we propose spreadsheet-based register template which is translated to IP-XACT description, from which register models can be easily generated using commercial tools. On the other hand, we also automate all the steps involved integrating test-bench and generating test-cases, so that designers may use register model without detailed knowledge of UVM or SystemVerilog. This automation flow involves generating and connecting test-bench components (e.g., driver, checker, bus adaptor, etc.) and writing test sequence for each type of register test-case. With the proposed flow, designers can save considerable amount of time to verify functionality of registers.

CNC system of the 5-axis hybrid robot for milling

The paper presents architecture and a FPGA based implementation of the dedicated CNC system for5-axes milling machine. The hybrid structure of the machine, consisting of the parallel manipulator and the tilt rotary table, required development of a specialised controller, called CNC system. TheCNC system is composed of the two main parts: Human-Machine Interface (HMI) andNumerical Control Kernel (NCK). The NCK consists two soft-processor units, equipped with coprocessor's instructions, performing calculations on floating point numbers, and a dedicated hardware block, which integrates the system. The priority functional requirement is the sampling frequency of10kHz for all modules. Another aspect of the paper is the realization of coprocessor algorithms for arithmetic, trigonometric and other functions. The paper shows results of computing test efficiency and the maximum calculation error for a trajectory generated from G-codes. Theresults prove fulfilling all requirements. Finally, the conclusions and directions of future works are presented.

Performance evaluation of SD – cards by "system-on-chip" technology

Subject matter. We propose the hardware and software block for performing write or read operation and testing the performance of different SD-cards using the technology of "system-on-chip" in integrated environment by Altera. This task is relevant for the design of high-performance parallel systems on a chip, where the lower limit for writing speed (and/or reading) is critical and significant. Method. The proposed approach is based on three items. First, schemes are used with programmable logic to create a compact hardware and software unit as part of video system on chip. Secondly, reprogrammable structures are applied that support serial and parallel modes of exchange. Thirdly, the increment of data bus width is possible, via the serial transfer and the parallel connection of multiple units simultaneously. Main Results. The analysis of test results of different memory cards has shown that the speed of writing and reading for all cards differs from the declared one by manufacturer, and the error rate of writing (and reading) of data is 30...50% (for reading ~30%). A maximum download speed of memory cards is possible by increasing the number of cascade-connected blocks. The results show that the simplest implementation of this hardware-software unit requires resources of the order of 2000-2500 elementary logic cells. Each cell implements the logical operation "AND-OR with memory", while the resource ЕР3С25F256C8 of the popular chip family Cyclone III consists of 5976 (26%) of these cells with the chip price equal to $5-10 apiece. Practical Relevance. The authors believe that the proposed hardware-software unit can be regarded as the cheapest specialized component in the ECB domestic microelectronics industry to create video information in real time systems.

128 bit Unsigned Multiplier Design and Implementation Using an Efficient SQRT-CSLA

In Digital systems like digital signal processors, FIR filters and micro processors etc, Multiplier is one of the main hardware blocks. Generally, the performance of system is determined by the multiplier performance because the multiplier is generally the slowest element in the whole system and also it is occupying more area. In the multiplier, we use adder circuit repeatedly. So, an efficient adder circuit will be used in multipliers, it gives better performance. In the proposed work placing the new Carry Select Adders (CSLA) to enhance the multiplier performance. Carry Select Adder (CSLA) provides better performance with respect to speed and area. Previously a binary to excess one converter (BEC) based Square Root Carry Select Adder is designed but in that data dependency is very high, it gives some speed penalty. An efficient CSLA design is obtained using improved logic units to eradicate the data dependency and redundant logic operations. In this proposed work, the intended efficient Square Root Carry Select Adder is compared with BEC based CSLA of respective architectures, after having comparison the proposed CSLA is efficient with respective to area and delay is used in Multiplier design. This work gives better results regarding to the performance parameters such as delay and area of designed multiplier using new efficient square root carry select adder compared to BEC based CSLA multiplier.

A High-Performance FPGA-Based Image Feature Detector and Matcher Based on the FAST and BRIEF Algorithms

Image feature detection and matching is a fundamental operation in image processing. As the detected and matched features are used as input data for high-level computer vision algorithms, the matching accuracy directly influences the quality of the results of the whole computer vision system. Moreover, as the algorithms are frequently used as a part of a real-time processing pipeline, the speed at which the input image data are handled is also a concern. The paper proposes an embedded system architecture for feature detection and matching. The architecture implements the FAST feature detector and the BRIEF feature descriptor and is capable of establishing key point correspondences in the input image data stream coming from either an external sensor or memory at a speed of hundreds of frames per second, so that it can cope with most demanding applications. Moreover, the proposed design is highly flexible and configurable, and facilitates the trade-off between the processing speed and programmable logic resource utilization. All the designed hardware blocks are designed to use standard, widely adopted hardware interfaces based on the AMBA AXI4 interface protocol and are connected using an underlying direct memory access (DMA) architecture, enabling bottleneck-free inter-component data transfers.

COMMUNICATION CO-PROCESSOR DESIGN BY COMPOSITION OF PARAMETERIZED CELLS

We deal with hardware block interconnection in Systems-on-Chip. The cost of writing the glue code grows together with the complexity of such systems. To write such code manually is time consuming. We present a method of communication co-processor generation for multi-processor SoCs. The method is based on composition of the parameterized library cells. The cells are parameterized using external macro language. The parameterization and decomposition of the CC allows decreasing the size of the library, increases code reuse and testability of the components without loss of performance and flexibility. We present a VDSL application as a case study for our approach.

Universal block for simple design of FPGA based controller in anthropomorphous robot configuration

This paper is a description of universal block created for the purpose of simplifying realization of control structure for anthropomorphous robots on FPGA chip. Block is realized in Matlab with installed DSP Builder used for programming Altera FPGA chips with FPGA Real Time Toolbox. In the paper are also provided prerequisites and control structure for robot PUMA 560, as well as simulation results of the chosen algorithm realized in Matlab with Robotics Toolbox. In the end of the paper are provided experimental results verified on robot PUMA 560. Matching between experimental and simulation results validates the concept of the realized controller hardware and universal block.

Guest Editorial

Guest Editorial

Design of Adaptive Filter for Laser Gyro

According to the filtering of laser gyro output signal of low precision, slow speed of dynamic response, the research and implementation of a new method of laser gyro filtering process, the scheme using LMS adaptive filtering algorithm, the dither feedback signal as the iterative filter data input, the dither signal, random noise, white noise as the reference signal filter, digital filter and the external control using FPGA, give the filter algorithm and hardware block diagram. Experimental results show that the filtering module with filter with high precision and wide dynamic response range, can meet the requirements of speed and precision of laser gyro demodulation aerospace fields.

SIFT Hardware Implementation for Real-Time Image Feature Extraction

This paper introduces a high-speed all-hardware scale-invariant feature transform (SIFT) architecture with parallel and pipeline technology for real-time extraction of image features. The task-level parallel and pipeline structure are exploited between the hardware blocks, and the data-level parallel and pipeline architecture are exploited inside each block. Two identical random access memories are adopted with ping-pong operation to execute the key point detection module and the descriptor generation module in task-level parallelism. With speeding up the key point detection module of SIFT, the descriptor generation module has become the bottleneck of the system's performance; therefore, this paper proposes an optimized descriptor generation algorithm. A novel window-dividing method is proposed with square subregions arranged in 16 directions, and the descriptors are generated by reordering the histogram instead of window rotation. Therefore, the main orientation detection block and descriptor generation block run in parallel instead of interactively. With the optimized algorithm cooperating with pipeline structure inside each block, we not only improve the parallelism of the algorithm, but also avoid floating data calculation to save hardware consumption. Thus, the descriptor generation module leads the speed almost 15 times faster than a recent solution. The proposed system was implemented on field programmable gate array and the overall time to extract SIFT features for an image having 512×512 pixels is only 6.55 ms (sufficient for real-time applications), and the number of feature points can reach up to 2900.

ENHANCED LOW POWER, FAST AND AREA EFFICIENT CARRY SELECT ADDER

Adder being the basic hardware block of any arithmetic operation, the major constraint in the field of signal processors, data processors to perform any operations is highly dependent on the adder performance of the circuit. The gate level implementation of the carry select adder (CSLA) and modified carry select adder has significantly reduced the area and power consumption which replaced the ripple carry adder (RCA) used in modified CSLA with MUX based Full Adder (MUX-FA) block has further reduced the power consumption by efficiently utilizing the area with faster performance.