Guardband Reduction Research Articles

Real-time optical spectrum monitoring in filterless optical metro networks

Filterless optical networks (FONs) have been proposed as a feasible solution for optical metro networks. In addition, as a result of the shorter distance compared to core optical networks, direct detection optical transmission systems can be used in metro FONs, which reduces costs, as compared to coherent detection systems. In this work, we present two optical signal tracking approaches for FONs that allow to detect small frequency laser drift problems and enable safely reducing channel spacing. Additionally, we study the most proper resolution for optical spectrum analyzers continuously scanning the whole C-band. Proposed approaches are: (1) feature-based tracking and (2) residual-based tracking. Experiments are carried out to compare the performance of the approaches for both direct detection and coherent detection systems, in the case of a single optical signal with no neighboring signals nearby in the spectrum, as well as in the case of a group of optical signals closely allocated in the spectrum. The results show that the residual-based approach enriched with contextual information enables to better track and correct the wavelength drifts before they reach their limits (e.g., ± 2.5 GHz), leading to the guard band reduction for what concerns wavelength drifts.

Guard Band Reduction for 5G and Beyond Multiple Numerologies

The existence of inter-numerology interference (INI) is a major drawback for the flexible multi-numerology frame structure proposed for the upcoming fifth generation New Radio (5G-NR). Insertion of a guard band (GB) between adjacent numerologies has been widely used in the literature as one of the effective ways to reduce the INI. However, the conventional way of implementing GBs is inefficient in terms of spectrum usage. In this letter, we exploit the inherent INI characteristics of the scalable multi-numerology structure to propose a more spectrally efficient way of implementing GBs. It is shown through simulations that the proposed GB insertion technique enhances the GB utilization up to 50% while achieving the same bit error rate performance as the conventionally implemented GB.

An All-Digital Fused PLL-Buck Architecture for 82% Average V dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microprocessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level

Variability is one of the major challenges for CMOS in the nano era. Manufacturers test each circuit sample to ensure that samples that do not meet the desired specification are discarded. However, testing is only effective for variability, which is observable right after manufacturing, such as geometric variations, work function, and random dopant fluctuation. This is in contrast to time-dependent variability (TDV), i.e., differences in the defects of transistors, which is not macroscopically observable immediately after manufacturing. In fact, defects are electrically neutral until they capture a carrier [with mechanisms called bias temperature instability (BTI) and random telegraph noise (RTN)] and thus become observable through their induced degradation. Therefore, transistors which are characterized identically after manufacturing will drift apart during their lifetime, as their susceptibility to effects such as BTI and RTN is different. In this paper, we model for the first time TDV from a defect-centric physical perspective all the way to the circuit level. Our novel defect-centric transistor reliability specification provides a fast, yet accurate method to estimate an upper bound for TDV on the transistor level, while our novel worst cell (WCL) and worst value (WVL) libraries allow for fast evaluation of the impact of TDV on the timing of circuits. Our approach is fully compatible with existing EDA tool flows, allowing us to model and optimize complex circuits like full microprocessors. By evaluating the impact of TDV with our reliability specification and variability-aware cell libraries, we are able to model TDV, which allowed us to reduce the required defect variability guardband by 46%. In addition, we provide design optimization strategies on each abstraction level such as limiting continuous stress, transistor hardening, and implement a novel variability-aware synthesis to achieve up to 57% additional guardband reduction.

Increasing the Spectral Efficiency of DDO-CE-OFDM Systems by Multi-Objective Optimization

A multi-objective optimization was implemented to increase the spectral efficiency of direct-detection optical orthogonal frequency division multiplexing (OFDM) systems with constant-envelope (CE) signals. Based on a genetic algorithm, the optimization procedure evaluates the impact of fiber injection power in the reduction of the guard band between the optical carrier and the CE-OFDM signals, optimizing important parameters such as electrical phase modulation and optical modulation indices of the denominated DDO-CE-OFDM system. Simulation results show that a guard-band reduction around 40% was achieved in a 4 Gbps optimized DDO-CE-OFDM system with 16-QAM subcarrier mapping and -7 dBm fiber input power. Results obtained in an experimental proof-of-concept conducted to validate the optimization procedure show that this reduction can reach 66% according to a power penalty of ≈2 dB demanded by the inherent spectral broadening of CE-OFDM signals, after propagation over 40 km of standard single-mode fiber.

An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects

Circuit reliability due to Bias Temperature Instability, BTI, has become an important concern in scaled-down complex electronic systems. Even more, current silicon technologies are severely affected by the combined impact of BTI-induced device’s aging and Process-induced device’s parameters variations. The conventional worst-case guardbanding to deal with reliable circuit operation is not longer an efficient approach as the circuit performance is significantly penalized. This paper presents a gate-sizing optimization me-thodology to reduce the worst-case guardbanding considering the combined effects of aging due to BTI and process variations. The proposed methodology allows to trade-off the reduction of guardbanding and the area cost. The proposed methodology uses multiple workload-aware aging analysis procedures to identify a realistic workload condition that causes maximum degradation to each potential critical paths of the circuit. In such a way, classic worst-BTI assumptions that lead to over-design are avoided. New gate-sizing metrics are proposed to identify the most beneficial gates to resize in the delay optimization process. In order to compute the gate sizing metrics efficiently, it is proposed a fast approximation for the sensitivity of the statistical delay of a path with respect to a change in the size of a gate. Also, the criticality, slack-time and area penalization are considered in the metric. A heuristic is proposed to guide the iterative delay optimization process. Some key conditions are identified in the workload analysis, metric evaluation and the heuristic to reduce the computational cost. The results show clearly the benefits of using multiple workload-aware aging analysis and the proposed gate-sizing metrics. It is shown that the proposed gate-sizing metrics are more efficient than others available in the literature since they provide a better area-guardband reduction trade-off. The proposed methodology results in more reliable designs at low area overhead, and it is suitable to guarantee the stringent quality requirements of modern circuits.

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating

In high volume manufacturing, conventional approach to deal with inverse-temperature dependence (ITD) and aging is to add a postsilicon flat voltage guard band to all dies based on testing a small random sample of dies. Although this scheme guarantees error-free operation, it significantly degrades energy efficiency, as it penalize all dies for the maximum delay degradation due to ITD and aging as seen by the worst case die, while also assuming maximum aging condition. In this paper, a graphics execution core implemented in 22 nm trigate process uses per-die tunable replica circuit (TRC) to monitor delay degradation due to ITD and actual aging conditions. TRC triggers adaptive voltage scaling to dynamically adjust $V_{\mathrm {CC}}$ as needed during run time to maintain correct operation at minimum additional voltage. Measured data show up to 33% (14%) energy savings at 0.4 V (0.8 V) compared with baseline scheme. The TRC is also utilized in a dynamic power gating (DPG) scheme to lower energy overhead due to fast droop guard band. DPG introduces a load line effect during normal operation, thus saving energy, while deactivating this load line upon droop detection by the TRC to maintain ISO performance as baseline. Silicon data show that DPG can improve energy efficiency by 14.5% (7%) at 0.8 V (0.6 V).

Impact of Optical Power in the Guard-Band Reduction of an Optimized DDO-OFDM System

A multiobjective optimization on the parameters of direct-detection optical orthogonal frequency division multiplexing (DDO-OFDM) systems in short-range links is proposed. Based on genetic algorithms, the optimization process takes into account the influence of optical power in the guard-band reduction of such multicarrier systems with 4- and 16-quadratic-amplitude modulation (QAM) subcarrier mapping and for propagation in $40$ km of standard single-mode fiber (SSMF). Simulation results show that the parameters optimization is responsible for a gain of approximately $2.5$ dB [ $\approx 1.8$ dB] in the required optical power for bit-error-rate ${\le }10^{-3}$ , for DDO-OFDM system transmission over $40$ km of uncompensated SSMF, with a guard band $B_G$ equals to $50\%$ of the signal bandwidth $B_w$ and 16-QAM [4-QAM] subcarrier mapping. For an extremely reduced guard band of only $1\%$ of $B_w$ , the gain reduced to $\approx 0.5$ dB and $\approx 1.5$ dB for 16- and 4-QAM mapping, respectively. The optimization process is experimentally validated under the transmission of the optimized DDO-OFDM systems in optical back-to-back (B2B) configuration and $40$ km of uncompensated SSMF. A fair performance comparison is discussed in the experimental results considering $B_G/B_w=0.5$ and $B_G/B_w=0.01$ in the range of the optimized optical powers. It is shown that a maximum optical power penalty of approximately $2$ dBm is registered according to a guard-band reduction from $50\%$ to $1\%$ of the useful bandwidth, for transmission over the 40 km of SSMF, considering 16-QAM subcarrier mapping.

Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach

The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap (available: http://public.itrs.net). Our work gives the first-ever quantification of the impact of model guardband reduction on outcomes from the synthesis, place and route (SP&R) implementation flow. We assess the impact of model guardband reduction on various metrics of design cycle time and design quality, using open-source cores and production (specifically, ARM/TSMC) 90- and 65-nm libraries and technologies as well as an industrial embedded processor core implemented in 45 nm. Our experimental data clearly shows the potential design quality and turnaround time benefits of model guardband reduction. For example, in our open-source cores, on average we observe 13% standard-cell area reduction, 12% routed wirelength reduction, 13% dynamic power reduction and 19% leakage power reduction as the consequence of a 40% reduction in library model guardband; 40% is the amount of guardband reduction reported by IBM for a variation-aware timing methodology. For the embedded processor core we observe up to 8% standard-cell area reduction, 7% routed wirelength reduction, 5% dynamic power reduction, and 10% leakage power reduction at 30% guardband reduction. We also report a set of fine-grain SPICE simulations that accurately assesses the impact of process guardband reduction, as distinguished from overall guardband reductions, on yield. We observe up to 4% increase in number of good dies per wafer at 27% process guardband reduction (i.e., with fixed voltage and temperature). Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices.