Guard Ring Research Articles

Separation of planar and edge contributions to total capacitance for accurate doping concentration determination in square silicon photodiodes

Accurately determining the doping concentrations of silicon photodiodes (PDs) is crucial for optimizing their performance in various applications. This study presents a methodology for separating the planar and edge contributions to the total capacitance of square silicon PDs with guard rings. Through capacitance-voltage measurements, we distinguished planar capacitance, which reflects the bulk properties of the silicon PD, from edge capacitance, influenced by device geometry and fringing fields. We demonstrated that the fabricated PDs with guard rings surrounding the active area could be effectively modeled using a coxial-like structure to estimate edge capacitance. Doping concentrations, depletion widths, and resistivities were determined through linear fitting of the inverse square of the measured capacitance per unit area as a function of the reverse bias voltage. All parameters obtained from the full depletion voltage Vd , determined by the intersection of the linear fits for V < Vd and V > Vd , demonstrated agreement within 1σ. Our results underscore the importance of accounting for edge effects to accurately determine doping concentrations from 1/C 2 vs. V plots.

Non-invasive method to measure bulk electrical resistivity of spruce wood – influence of moisture content and anatomical direction

ABSTRACT The correlation between electrical resistance and moisture content (MC) of wood has been studied for many years and is the basis for an important method for determining wood MC in practice. This study presents a non-invasive set-up using plate electrodes with a guard ring covered with silver foam and gold leaves to measure the direct-current (DC) electrical resistivity of spruce wood. The design ensures good electrical contact at a pressure of 0.68 MPa, without impairing the wood surface. Measurements were conducted across various moisture contents up to the fiber saturation point (FSP) for the three anatomical directions at a temperature of 21°C. The regression parameters between electrical resistivity and moisture content were determined with high coefficients of determination (R² = 0,97–0.98). The effect of MC on the electrical resistance was significantly more pronounced in the radial direction, and the electrical resistance in the axial direction was lower than in the radial and tangential direction. Those findings support the basic understanding of the electrical properties of spruce wood and provide a basis for non-invasive volume resistivity measurements of wood.

Enhancing Gamma-Ray Spectral Resolution in Perovskite CsPbBr3 Detectors through Dark Current Reduction with Guard Ring Electrodes

Enhancing Gamma-Ray Spectral Resolution in Perovskite CsPbBr₃ Detectors through Dark Current Reduction with Guard Ring Electrodes

Measurements and TCAD simulations of guard-ring structures of thin silicon sensors before and after irradiation

The developing of high performing silicon detectors for particle tracking in the next generation of high-energy physics experiments at future colliders (e.g., HL-LHC, FCC) able to operate efficiently up to very high fluence (∼1⋅10171MeVneq/cm2) is of the utmost importance. In order to sustain high voltage values with minimum leakage current injection into the core region of the sensor, the design and optimisation of the Guard-Ring (GR) protection structure is crucial, especially when small substrate thicknesses are used. In a recent R&D batch produced at Fondazione Bruno Kessler (FBK) in the framework of the “eXFlu” project - INFN CSN5 grant for Young Researchers, different optimisation studies of GR structures for thin substrates (45, 30, 20 and 15μm) up to high fluence (2.5⋅10151MeVneq/cm2) have been addressed. These have been enabled thanks to ad-hoc advanced Technology CAD (TCAD) modelling of different GR design strategies, accounting for the comprehensive bulk and surface radiation-induced damage effects, and an extensive test campaign on such GR structures, both before and after irradiation. In this paper the validation of the development framework of the various GR design options before and after irradiation is presented.

Field management in NiO x /β-Ga2O3 merged-PIN Schottky diodes: simulation studies and experimental validation

In recent years, p-type NiO x has emerged as a promising alternative to realize kilovolt-class β-Ga2O3-based PN junction diodes. However, only a handful of studies could realize β–Ga2O3-based unipolar diodes using NiO x as a guard ring or floating rings. In this work, we investigate the device design of NiO x /β-Ga2O3 unipolar diodes using the technology computer aided design simulations and experimental validations. We show that a systematic electric field management approach can potentially lead to NiO x /β-Ga2O3 heterojunction unipolar diode and offer enhanced breakdown characteristics without a severe compromise in the ON-state resistance. Accordingly, the NiO x /β-Ga2O3 heterojunction diode in the merged-PIN Schottky configuration is shown to outperform the regular Schottky diode or junction barrier Schottky diode counterpart. The analysis performed in this work is believed to be valuable in the device design of β-Ga2O3-based unipolar diodes that use a different p-type semiconductor candidate as guard rings and floating rings.

Barrier height enhancement in β-Ga2O3 Schottky diodes using an oxygen-rich ultra-thin AlOx interfacial layer

Schottky barrier height (SBH) enhancement directly translates into increased breakdown voltage (VBR) of β-Ga2O3 Schottky barrier diodes (SBDs). In this work, ultra-thin (5, 10, and 15 Å) oxygen-rich AlOx interfacial layers (ILs), deposited using plasma-enhanced atomic layer deposition, are shown to enhance the SBH of post-metallization oxygen annealed Pt/AlOx/β-Ga2O3 SBDs by up to 0.8 eV resulting in a maximum VBR of nearly 500 V (2× gain) on 2–4 × 1016 cm−3 doped substrates, without compromising the specific on-resistance. The SBH and VBR enhancement is observed on (2¯ 01) as well as (001) surfaces. X-ray photoelectron spectroscopy (XPS) analysis shows that excess oxygen interstitial concentration in 5 Å AlOx films decreases (increases) with increasing thickness (oxygen anneal), making them more stoichiometric. The decreasing (increasing) trend in SBH and VBR with increasing IL thickness (oxygen anneal) is consistent with the XPS-derived O/Al ratio of the films and the formation of an AlOx/β-Ga2O3 interfacial dipole due to a difference in oxygen areal densities. The AlOx deposition can be easily integrated with field management methods such as field plates and guard rings that can further enhance β-Ga2O3 SBD performance.

A 4H-SiC JFET with a monolithically integrated temperature sensor

In this paper, we present a monolithically integrated temperature sensor for a 4H-SiC JFET. This uses a lateral resistor formed by the P+ gate implant. The sensor resistance is dependent on the number of ionized dopants, which increases with temperature. Drift-diffusion simulations considering device self-heating have been carried out, which show the JFET exhibits a breakdown voltage of 1480 V and a nominal threshold voltage (Vth) of −4.3 V. We show that the sensor has a high degree of linearity (R2) of 0.996 between 25–150∘C. Breakdown voltage of the JFET with the integrated sensor is found to reduce as the spacing (S) between the gate junction, the adjacent floating guard ring (FGR) and the sensor junction increases. However, it is found that a large variation in sensor current (ΔIsens) is experienced in the off-state if S is small. An optimum value of S = 0.95 µm was found to maintain 90% of the JFET breakdown voltage, whilst only exhibiting ΔIsens= 3.4%. The impact of contact resistance to the total sensor resistance is ≤1%. In addition, the sensor robustness during switch-off is good, due to the high doping in the P+ layer. The proposed sensor can be integrated into 4H-SiC JFET without any modification of existing process flows, or additional mask layers to provide real-time temperature monitoring with high accuracy.

Wehnelt photoemission in an ultrafast electron microscope: Stability and usability

We tested and compared the stability and usability of three different cathode materials and configurations in a thermionic-based ultrafast electron microscope: (1) on-axis thermionic and photoemission from a custom 100 μm diameter LaB6 source with a graphite guard ring, (2) off-axis photoemission from the Ni aperture surface of the Wehnelt electrode, and (3) on-axis thermionic and photoemission from a custom 200 μm diameter polycrystalline Ta source. For each cathode type and configuration, including the Ni Wehnelt aperture, we illustrate how the photoelectron beam-current stability is deleteriously impacted by simultaneous cooling of the source following thermionic heating. Furthermore, we demonstrate usability via collection of parallel- and convergent-beam electron diffraction patterns and by formation of the optimum probe size. We find that usability of the off-axis Ni Wehnelt-aperture photoemission is at least comparable to on-axis LaB6 thermionic emission, as well as to on-axis photoemission [the heretofore conventional approach to ultrafast electron microscopy (UEM) in thermionic-based instruments]. However, the stability and achievable beam currents for off-axis photoemission from the Wehnelt aperture were superior to that of the other cathode types and configurations, regardless of the electron-emission mechanism. Beam-current stability for this configuration was found to be ±1% (one standard deviation from the mean) for 70 min (longest duration tested), and steady-state beam current was reached within the sampling-time resolution used here (∼1 s) for 15 pA beam currents (i.e., 460 electrons per packet for a 200 kHz repetition rate). Repeatability and robustness of the steady-state condition were also found to be within ±1% of the mean. We discuss the implications of these findings for UEM imaging and diffraction experiments, for pulsed-beam damage measurements, and for practical switching between optimum conventional TEM and UEM operation within the same instrument.

Microcracking in On-Chip Interconnect Stacks: FEM Simulation and Concept for Fatigue Test

The semiconductor industry is continuing the scaling down of both device and on-chip interconnect features, for performance and economic reasons. This trend has implications for the design of guard ring structures, i.e. metallic non-functional structures in the back-end-of-line (BEoL) stack designed to be efficient to stop microcracks. In this work, we present a sample design for an in situ experiment to study mechanical degradation and failure mechanisms of crack stop structures in the BEoL stack, to ensure the mechanical robustness of microchips for future technology nodes. Additional finite element method (FEM) simulations provide supplementary understanding of the crack kinetics. To examine the effects of mechanical loading on crack stop elements of the BEoL stack, a novel sample geometry for an in situ fatigue experiment using x-ray microscopy was developed. The x-ray microscope (ZEISS Xradia 800 Ultra) enables high-resolution imaging of the 3D-patterned sample structures and defects such as microcracks. The tailored sample geometry allows the application of a tensile load to a BEoL specimen by a lever mechanism. The feasibility of the sample design is shown by mode-I loading of a pure interconnect sample. Post-mortem analysis by scanning electron microscopy (SEM), confirming planar microcrack propagation from the notch through the dielectric layer with small deflections of the crack path near cone shaped copper vias. FEM simulations focusing on the stress-strain fields around a crack tip indicate the beginning of copper plasticity as major mechanism starting the redirection of cracks due to resulting material compression in front of the obstacle.

Investigation of the directional Faraday cup and improvement of the comparison between direct and indirect thrust measurements of a magnetic nozzle ECR thruster

The thrust of an electric propulsion device estimated from electrostatic probe measurements may be different from direct thrust measurements. In order to reduce this discrepancy for electron cyclotron resonance thrusters (ECRT), a new diagnostic is presented: the directional Faraday cup (FCDi). Thanks to a peculiar design, it assesses the angular distribution of ion current density in the plume of plasma thrusters. First, a theoretical model of the angular selectivity of the FCDi is introduced. It is validated with both simulations and experiments. Guidelines are given to use the FCDi in the plume of ECRT. Second, the observed discrepancies between direct thrust measurements made on a thrust stand and indirect ones are reduced when using the FCDi instead of a planar Faraday probe with a guard ring (FPGR). Relative errors come down to 10% with the FCDi, which are compared to 20%–30% observed with the FPGR. An analysis demonstrates that it is not due to the effect of local ion trajectories but comes from the magnitude of the ion current measured. A large sheath in front of the negatively biased FPGR seems to be the cause of this phenomenon. The grounded opening of the FCDi reduces this phenomenon and improves the ion flux measurement accuracy. This new probe, with angular selectivity characteristics, allows for the comparison of the ion flux ejection direction with the magnetic field line and contributes to a better description of ion population dynamic in the magnetic nozzle of the thruster.

Ultra-large scale array silicon pixel sensors with uniform and low leakage current for advanced X-ray light sources

The development of silicon pixel sensors (SPS) with high operating voltage, low leakage currents, and large arrays can contribute to improving the energy and spatial resolution of advanced X-ray light source detection systems. The Future Detection System comprises a hybrid-pixel detector with a collective resolution of 2048 × 2048 pixels, each measuring 100 μm× 100 μm. It consists of 16 p-i-n SPSs, where each sensor has an array size of 1024× 256 pixels. In this paper, the design of the pixel and guard rings is optimized to achieve uniform and ultra-low pixels leakage currents under high operating voltage. The high leakage current uniformity of the designed sensor is demonstrated through several tests conducted on small scale array SPS. The leakage current of the tested pixels is in the range of 0.50–0.55 pA at room temperature with less than 5% leakage deviation on the whole array. It is accompanied by breakdown voltages greater than 1000 V. The optimized 256× 128 pixel SPS showcases uniform leakage currents below 0.6 pA per pixel at room temperature, as evidence in both the edge and central pixels. The 1024× 256 pixels SPS is then manufactured based on the optimized design results. The obtained results show that the breakdown voltage is greater than 1000 V and the leakage current of the pixel is less than 2.5 pA. In addition, the interpixel capacitance of the sensor also reach an ultra-low level of 16 fF. This study paves the way for the development of a robust semiconductor device solution for applications where ultra-fast and large panel-pixel detectors in advanced X-ray light source detection systems are required.

Experimental study of Ni/TiO2/β-Ga2O3 metal–dielectric–semiconductor diodes using p-NiO junction termination extension

This work demonstrates TiO2/β-Ga2O3 metal–dielectric–semiconductor (MDS) diodes with an average breakdown field beyond the material limits of SiC and GaN. These MDS diodes have lower conduction losses and higher breakdown voltage (Vbk) than the cofabricated Schottky barrier diodes (SBDs), simultaneously improving both on- and off-state parameters that are typically in competition with each other. With further optimized field management using p-NiO guard rings (GRs), the Ni/TiO2/β-Ga2O3 MDS diodes present a path to realistically utilize the high critical field of Ga2O3 without large forward conduction losses from a high-barrier junction. MDS diodes showed a lower Von (0.8 V) than the SBDs (1.1 V) from linear extrapolation of the current density-voltage (J-V) curve. The MDS diode had higher Vbk of 1190 V (3.0 MV/cm) compared to 685 V (2.3 MV/cm) for the SBD, and the MDS diode with the p-NiO guard ring saw further improvement with Vbk of 1776 V (3.7 MV/cm) compared to 826 V (2.5 MV/cm) for GR SBD. The BFOM (Vbk2/Ron,sp) of 518 MW/cm2 for the GR HJD is competitive with other literature results. A new figure of merit that includes the impact of turn on voltage is also proposed and demonstrated in this paper, which highlights how diodes perform in a practical high-power operation. This full paper is derived from the proceeding abstract of Willams et al. [IEEE Device Research Conference, Santa Barbara, CA, 25-28 June 2023 (IEEE, New York, 2023)].

Breakdown performance of guard ring designs for pixel detectors in 150 nm CMOS technology

Silicon pixel sensors manufactured using commercial CMOS processes are promising instruments for high-energy particle physics experiments due to their high yield and proven radiation hardness. As one of the essential factors for the operation of detectors, the breakdown performance of pixel sensors constitutes the upper limit of the operating voltage. Six types of passive CMOS test structures were fabricated on high-resistivity wafers. Each of them features a combination of different inter-pixel designs and sets of floating guard rings, which differ from each other in the geometrical layout, implantation type, and overhang structure. A comparative study based on leakage current measurements in the sensor substrate of unirradiated samples was carried out to identify correlations between guard ring designs and breakdown voltages. TCAD simulations using the design parameters of the test structures were performed to discuss the observations and, together with the measurements, ultimately provide design features targeting higher breakdown voltages.

Investigation of high resistivity [formula omitted]-type FZ silicon diodes after 60Co [formula omitted]-irradiation

In this work, the effects of 60Co γ-ray irradiation on high resistivity p-type diodes have been investigated. The diodes were exposed to dose values of 0.1, 0.2, 1, and 2MGy. Both macroscopic (I–V, C–V) and microscopic investigations, by means of Thermally Stimulated Current (TSC) and Deep Level Transient Spectroscopy (DLTS) techniques, were conducted to characterize the radiation-induced changes. The investigated diodes were manufactured on high resistivity p-type Float Zone (FZ) silicon and were further classified into two types based on the isolation technique between the pad and guard ring: p-stop and p-spray. After irradiation, the macroscopic results of current–voltage and capacitance–voltage measurements were obtained and compared with existing literature data. Additionally, the microscopic measurements focused on the development of the concentration of different radiation-induced defects, including the Boron interstitial-Oxygen interstitial (BiOi) complex, the Carbon interstitial-Oxygen interstitial (CiOi) defect, the H40K, and the so-called IP∗.To investigate the thermal stability of induced defects in the bulk, isochronal annealing studies were performed in the temperature range of 100°C to 300°C. These annealing processes were carried out on diodes irradiated with doses of 1 and 2MGy. Furthermore, in order to investigate the unexpected results observed in the C–V measurements after irradiation with high dose values, the surface conductance between the pad and guard ring was measured as a function of both dose and annealing temperature.

A Fully Differential CMOS Current Memory Cell for Space-Embedded Analog-to-Digital Converters

This paper presents a radiation-hardened high-resolution current memory cell (CMC) that can be used to implement current-mode analog-to-digital converters (ADCs) for space-embedded, charge-coupled device processors. This CMC is based on a fully differential structure and on the Miller effect to reduce charge-injection errors. Using a commercial 0.35-μm 3.3-V complementary metal-oxide-semiconductor (CMOS) process, the radiation tolerance of this CMC has been enhanced by designing enclosed n-channel MOS transistors, using p-channel MOS switches only, and introducing guard rings wherever necessary. Results show that the CMC accuracy is 10 bits and that its estimated linearity error is &3x000B1;50 nA for a [-200 μA; 200 μA] dynamic input current range. Experimental results point out that signal-dependent charge injections are divided 23 times at least, which improves the CMC accuracy by approximately 4 bits. The measured acquisition time for a 200-μA input step transition to achieve a 10-bit settling accuracy is 50 ns. The active chip area and the power consumption of the proposed CMC are 0.042 mm 2 and 6 mW, respectively.

A Novel DTSCR Structure with High Holding Voltage and Enhanced Current Discharge Capability for 28 nm CMOS Technology ESD Protection.

To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology.

(Invited) Recent Progress in Medium-Voltage Vertical GaN Power Devices

Vertical gallium nitride (GaN) power devices continue to garner interest in multiple power conversion applications requiring a medium-voltage (1.2 – 20 kV) capability. Currently, silicon carbide (SiC) is addressing this voltage range, however, with a comparable critical electric field and superior mobility, GaN is expected to offer advantages in applications where fast switching and avalanche breakdown response times are desired. While uses in electric vehicles, solid-state transformers, and renewable energy conversion are being actively explored, the potential of a vertical GaN device for electric grid protection in the form of an electromagnetic pulse arrestor is a unique proposition that requires very fast transient capabilities (<1 µs pulse widths with rise-times on the order of 10 ns). However, vertical GaN devices are significantly less mature than present SiC offerings. Specifically, low-doped, thick epitaxial growth of GaN via metal-organic chemical vapor deposition (MOCVD) still presents many challenges, and advancements in processing, manufacturability, and failure analysis are needed.In this work, we describe our efforts to address the above issues and advance the state-of-the-art in vertical GaN PN diode development. We have successfully demonstrated an MOCVD-grown, 50 µm thick, low-doped (<1015 cm-3) drift region on a GaN substrate that was processed into relatively large-area (1 mm2) PN diodes capable of achieving a 6.7 kV breakdown. Temperature-dependent breakdown was observed, consistent with the avalanche process. The devices consisted of a 4-zone step-etched junction termination extension (JTE), where the breakdown region was visualized via electroluminescence (EL) imaging. Ongoing work aims to scale the current capability of the medium-voltage diodes through a parallel interconnect design that negates defective or poor performing diodes. Further investigation of edge termination structures was explored using a bevel approach, where we studied the relationship between the bevel angle and p-doping. It was found that a very shallow angle of only 5° accompanied by a 500 nm p-region consisting of 3×1017 cm-3 Mg concentration resulted in a consistent 1.2 kV breakdown for an 8 µm thick, 1.6×1016 cm-3 doped drift region. EL imaging confirmed uniform breakdown, and temperature dependence was demonstrated. The bevel approach was then implemented on a diode structure with a 20 µm thick drift region capable of 3.3 kV breakdown, where an unclamped inductive switching (UIS) test was performed to evaluate the impact of a field plate design on avalanche uniformity and ruggedness.A parallel effort to establish a foundry process for vertical GaN devices has been underway. Initially, this focus was on comprehensive studies of GaN wafer metrology using capacitance-voltage (C-V) mapping, optical profilometry, and x-ray diffraction (XRD) mapping. A machine learning algorithm was implemented to identify defective regions and produce a yield prediction for each GaN wafer prior to processing. A hybrid edge termination structure consisting of implanted guard rings (GR) and JTEs was developed in coordination with a controlled experiment that varied the anode thickness, and therefore the remaining p-GaN after implantation. It was observed that thinner p-GaN regions under the JTE/GR region resulted in a significant (>100x) reduction in leakage current under reverse-bias conditions. This process has resulted in 1.2-kV-class devices with up to 18 A forward current for a 1 mm2 device with a specific on-resistance of 1.2 mOhm-cm2. The foundry effort has since been extended to 3.3-kV-class devices that utilize 25 µm thick drift layers with ~2-4×1015 cm-3 doping. These devices have demonstrated up to 3.8 kV breakdown with leakage currents <1 nA up to 3 kV. More than 40 wafers have been processed to date, resulting in >20,000 devices. Statistical variations in I-V and C-V characteristics will be discussed. Packaging process development and analysis are underway to develop electrical stress procedures and identify fundamental failure mechanisms. Finally, a pulse arrested spark discharge (PASD) setup, capable of up to 15 kV pulsed operation in 100 V steps, was implemented to quantify the time response of avalanche breakdown. Initial results on a packaged 800 V device showed a ~1 ns response time during breakdown, which reinforces the potential EMP grid protection applicability. This work was supported by the ARPA-E OPEN+ Kilovolt Devices Cohort directed by Dr.Isik Kizilyalli. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy of the United States Government.

Numerical analysis of aerodynamic and structure characteristics of an autonomous unmanned flying car for high-rise building rescue operations in urban area

Using numerical commercial software, this article presents a type of autonomous unmanned flying car capable of saving people in burning high-rise buildings in urban areas. This kind of flying vehicle is maneuverable and fast, and it has the ability to anchor to the building balconies to receive people in distress. Initial, a computational simulation is performed to investigate the aerodynamic properties of the propeller without and with a guard ring. A full-scale model evaluation based on Buckingham-Pi theory is then performed to evaluate the aerodynamic and structural characteristics of the proposal. Numerical simulation results show that the proposed design is feasible.

Ultra-low turn-on voltage (0.37 V) vertical GaN-on-GaN Schottky barrier diode via oxygen plasma treatment

In this work, vertical gallium nitride (GaN) Schottky barrier diodes (SBDs) with an ultra-low turn-on voltage VON (0.37 V) were demonstrated. Due to the process of O2 plasma treatment, GaON was formed on the surface of GaN and further modified the surface potential of the material surface, which made the VON decrease from 0.62 to 0.37 V. Spin-on-glass was deposited on top of devices to form the floating guard ring, which was used to improve the breakdown voltage to 681 V (at J = 1 A/cm2) by reducing the electric field distribution. The vertical GaN SBDs exhibit a specific on-resistance (RON) of 2.6 mΩ cm2. Deterioration of the device under different stress time changes slightly showed great stability of the devices.

The influence of the structure of guard rings on the dark currents of silicon p-i-n photodiodes

The article examines the influence of the guard rings (GR) system structure on the dark currents of responsive elements (RE) and the actual guard rings of silicon 4-element p-i-n photodiodes (PD). The samples were made on the basis of p-silicon by planar technology. Samples with one, two, and three GR were produced. It was found that increasing the amount of n+-GRs does not reduce the dark current of the REs. But with an increase in the number of n+-GRs, the probability of an edge breakdown of the n+-p-junction in the regions of the exit of the hetero-junction of the GR to the surface increases. It is possible to reduce the levels of dark current of REs and GR by combining n+- and p+- guard regions, where p+-GR is a region of restriction of dark current leakage channels, isotypic with the substrate material. PD was made with p+-GR on the periphery of the crystal in the form of a concentric ring, as well as with a p+- region on the entire periphery of the crystal. This makes it possible to reduce the level of of dark current of n+- GR due to the reduction of the area of collection of charge carriers from the surface. But a significant decrease in the dark current of REs was not observed in such cases. We proposed to carry out boron diffusion in the gaps between REs and between REs and n+-GR.