Growth Of Silicon Nanowires Research Articles

The influence of unintentional Au impurities on the doping properties of Si nanowires

Gold is the most commonly used catalyst for the growth of silicon nanowires. During the growth process, Au atoms are inevitably incorporated into the nanowire. In this study, the impact of Au impurities on the doping of silicon nanowires is systematically studied based on first-principles calculations. Our calculations demonstrate that the Au impurity prefers to occupy the substitutional site in the centre of nanowire, which results in midgap deep defect levels, forming a carrier combination centre. Further analysis indicates that both n- and p-type doping efficiencies are strongly inhibited by the unintentional Au impurity in the nanowire. Our results suggest that effective methods should be adopted to reduce the concentration of Au impurities in silicon nanowires, such as low-temperature growth and self-catalysed growth techniques.

Direct growth of germanium and silicon nanowires on metal films

We describe the basic thermodynamic and kinetic aspects that govern the growth of Si and Ge nanowires directly on bulk metal films. We illustrate essential differences between the vapour–solid–solid and the conventional vapour–liquid–solid nanowire growth. Ge and Si nanowires were formed on a select set of metal films including Ag, Al, Au, Cr, Cu and Ni. Metals that form silicides or germanides (Cr, Cu, and Ni) generally yield higher quality nanowires compared to nanowires grown on metal films whose equilibrium phases are defined by alloyed phases below eutectic temperatures (Al, Ag, Au). Combinatorial experiments presented here provide new basic insights into nanowire formation in the context of metal germanide and silicide formation rates. The mechanism established from our experiments successfully predicts the nanowire growth under a broad range of conditions and also predicts the nanowire growth on other metals to provide guidance to future progress in nanowire synthesis.

The effects of substrate self-biasing on the growth of Sn-catalysed silicon nanowires grown at low pressure

We describe the fabrication of silicon nanowire arrays on silicon substrates using Sn as a catalyst metal and electron cyclotron resonance chemical vapour deposition as the growth method. This technique features low deposition pressures and long mean-free paths, allowing the ability to control the ion bombardment energies at the substrate with the application of RF power to the substrate. The applied RF signal generates a DC self-bias across the substrate. Wires have been grown under differing levels of DC self-bias from 0 to −100 V. The impact on wire density, morphology and catalyst stability is described.

Ultra-dense and highly doped SiNWs for micro-supercapacitors electrodes

The use of nanoporous anodic alumina as a template for silicon nanowire growth enables the production of ultra dense nanowire arrays with density up to 8.109cm−2. The integration of such nanowire arrays in micro-supercapacitor electrodes significantly improves the electrode capacitance per planar surface area and nanowires length unit compared to electrodes made from silicon nanowires grown from gold colloids (from 5.2μF.cm−2.μm to 36.7μF.cm−2.μm). Micro-supercapacitors with such electrodes and ionic liquid as electrolyte have a very promising cycling stability featuring less than 1% of losses after 300 000 cycles.

One‐step formation of nanostructures on silicon surfaces using pure hydrogen‐radical‐initiated reactions

One‐step formation of silicon nanowires, sheets, and texture surface on a silicon substrate has been achieved using hydrogen‐radical etching reactions. Metallic tungsten and for comparison purposes a tungsten hot wire, were used as catalysts for the hydrogen‐molecular cracking. It was shown that a variety of surface structures on silicon such as inverted pyramid texture, V‐groove texture, dense silicon nanowire growth over texture, and nanosheet structure can be obtained by controlling the process conditions. The obtained results suggested that the formation of nanotungsten silicide particle is an essential prerequisite to obtain these structures. The particles work as an etching mask against hydrogen‐radical etching, as well as a catalyst for vapor–solid–solid (VSS) growth. SEM, TEM, micro‐RAMAN, and XPS were used for the analysis of the hydrogen‐radical‐treated Si samples. The Si nanowires growth model, as well as the texturing mechanism initiated by hydrogen‐radical treatment of Si surface in the presence of tungsten nanoparticle is discussed. It is concluded that the proposed acid‐free method, which is based on a modification of Si surfaces only by hydrogen radicals, can be considered as a “green” technology approach, which can be used for the cost‐effective fabrication of silicon nanostructures, which can be considered as a base for several types of advanced devices in the future.

Electroless selective deposition of gold nano-array for silicon nanowires growth

Abstract Nanopatterns of gold clusters on a large surface of oriented Si(111) substrates, from the galvanic displacement of gold salt (via the spontaneous reduction of AuCl4 -), are demonstrated in this work. The Si substrate is patterned by Focused Ion Beam (FIB) prior to being dipped in a gold solution. Here, we show that these patterns lead to successful control of the position and size of gold clusters. Sequential patterning reveals a powerful maskless alternative to surface preparation prior to Si nanowire growth.

Gold coverage and faceting of MBE grown silicon nanowires

In this paper, we investigate the faceting of molecular beam epitaxy (MBE) grown nanowires and the post-growth repartition of the gold used as catalyst. Electron microscopy analysis are performed using Scanning Transmission Electron Microscopy - High Angle Annular Dark Field (STEM-HAADF), electron tomography, and Energy-dispersive X-ray spectroscopy (EDS) to collect complementary information. The nanowires present very little to no faceting at the very top, very close to the catalyst, suggesting the nanowires grow with a quasi-circular section at the early stages of growth. The nanowires are then found to have an hexagonal and/or dodecagonal section and present a finer ‘saw-tooth’ faceting on the main faces. We find gold clusters spread on the surfaces of the nanowires, but we could not observe any gold inside the nanowires. Furthermore, the gold coverage is uneven on the different facets of the nanowire. The creation of these facets and the gold coverage are two linked phenomena balancing each other.

Silicon nanowire growth on poly‐silicon‐on‐quartz substrates formed by aluminum‐induced crystallization

AbstractThe vertical growth of Si nanowires on non‐monocrystalline substrates is of significant interest for photovoltaics and other energy harvesting applications. In this paper, we present results on using poly‐Si layers formed by aluminum‐induced crystallization (AIC) on fused quartz wafers as an alternative substrate for the vapor‐liquid‐solid (VLS) growth of vertical Si nanowires. Oxidation of the Al surface to Al2O3 before the a‐Si deposition was shown to be a key requirement in the formation of the poly‐Si template since it promotes the crystallization of the a‐Si into Si(111) which is required for vertical silicon nanowire growth. The effect of Al deposition technique (DC sputtering versus thermal evaporation) on a‐Si crystallization and Si nanowire growth was investigated. The use of Al thermal evaporation yielded AIC poly‐Si layers with the highest fraction of 〈111〉 grains as measured by orientation imaging microscopy (OIM) which enabled the growth of vertical Si nanowires. Cross‐sectional transmission electron microscopy analysis confirmed that the 〈111〉 Si nanowires grew epitaxially off of {111}poly‐Si grains in the AIC layer. This study demonstrates the potential of using AIC poly‐Si as a template layer for the vertical growth of silicon nanowires on amorphous substrates.

In Situ Growth of Si Nanowires Using Transmission Electron Microscopy

We discuss the use of the alloy catalyst AgAu to grow silicon nanowires and Si/Ge heterojunctions. Nanoscale particles of the catalyst with compositions Ag:Au varying from 2:1 to 1:2 can be fabricated and used to form Si nanowires with high crystal quality, and SiGe interfaces that are close to atomically abrupt. In situ experiments in the TEM are essential for investigating the mechanisms of growth with these alloy catalysts. We describe the relationship between growth kinetics and catalyst state, as well as the environmental stability of the alloy catalysts.

Wetting Layer: The Key Player in Plasma-Assisted Silicon Nanowire Growth Mediated by Tin

Unidirectional growth of silicon nanowires (SiNWs) can be achieved via a vapor–liquid–solid (VLS) mechanism. Interestingly, when adopting low surface tension metals such as tin or indium to mediate the growth of SiNWs in a plasma-assisted VLS process, the standard scenario is challenged by the fact that low surface tension metals tend to coat the high energy sidewalls of SiNWs. Moreover, we show that tin-assisted SiNW growth can continue without any apparent metal droplet on top. To address these issues, we investigate the time evolution of tin-assisted SiNW growth. We suggest that, during the initial growth phase, an ultrathin metal layer wetting the SiNW sidewalls allows silicon adatoms to diffuse toward the top of the nanowires, and thus enhances the axial growth while suppressing the radial one (in a way similar to molecular beam epitaxy growth of SiNWs). Later on, the wetting layer can assist the growth even when the tin droplets are exhausted from the top of SiNWs. We propose that this phenomenon ma...

Direct growth and photoluminescence of silicon nanowires without catalyst

One-dimensional (1D) silicon nanowires (SiNWs) were fabricated on catalyst free Si (100) substrate using a thermal evaporation method. Based on SVLS growth mechanism, the obtained SiNWs were 30 to 265nm in diameter and 1.7μm to several tens of microns in length. It was found that the presence of graphite powder only is enough to accomplish growth. A systematic study of how the growth conditions, such as the Ar carrier gas flow rate, and the growth time was performed. There are five resultant PL peaks: two blue emission peaks 465nm (2.67eV) and 482nm (2.57eV) and two green bands centered at 502nm (2.47eV) and 526nm (2.36eV) and one ultraviolet emission peak at 350nm (3.54eV). The theory behind these emissions was discussed.

Atomistics of vapour-liquid-solid nanowire growth.

Vapour–liquid–solid route and its variants are routinely used for scalable synthesis of semiconducting nanowires, yet the fundamental growth processes remain unknown. Here we employ atomic-scale computations based on model potentials to study the stability and growth of gold-catalysed silicon nanowires. Equilibrium studies uncover segregation at the solid-like surface of the catalyst particle, a liquid AuSi droplet, and a silicon-rich droplet–nanowire interface enveloped by heterogeneous truncating facets. Supersaturation of the droplets leads to rapid one-dimensional growth on the truncating facets and much slower nucleation-controlled two-dimensional growth on the main facet. Surface diffusion is suppressed and the excess Si flux occurs through the droplet bulk which, together with the Si-rich interface and contact line, lowers the nucleation barrier on the main facet. The ensuing step flow is modified by Au diffusion away from the step edges. Our study highlights key interfacial characteristics for morphological and compositional control of semiconducting nanowire arrays.

Parallel arrays of Schottky barrier nanowire field effect transistors: Nanoscopic effects for macroscopic current output

We present novel Schottky barrier field effect transistors consisting of a parallel array of bottom-up grown silicon nanowires that are able to deliver high current outputs. Axial silicidation of the nanowires is used to create defined Schottky junctions leading to on/off current ratios of up to 106. The device concept leverages the unique transport properties of nanoscale junctions to boost device performance for macroscopic applications. Using parallel arrays, on-currents of over 500 μA at a source-drain voltage of 0.5 V can be achieved. The transconductance is thus increased significantly while maintaining the transfer characteristics of single nanowire devices. By incorporating several hundred nanowires into the parallel array, the yield of functioning transistors is dramatically increased and deviceto-device variability is reduced compared to single devices. This new nanowirebased platform provides sufficient current output to be employed as a transducer for biosensors or a driving stage for organic light-emitting diodes (LEDs), while the bottom-up nature of the fabrication procedure means it can provide building blocks for novel printable electronic devices.

A review on electronic and optical properties of silicon nanowire and its different growth techniques.

Electronic and optical properties of Silicon Nanowire (SiNW) obtained from theoretical studies and experimental approaches have been reviewed. The diameter dependency of bandgap and effective mass of SiNW for various terminations have been presented. Optical absorption of SiNW and nanocone has been compared for different angle of incidences. SiNW shows greater absorption with large range of wavelength and higher range of angle of incidence. Reflectance of SiNW is less than 5% over majority of the spectrum from the UV to near IR region. Thereafter, a brief description of the different growth techniques of SiNW is given. The advantages and disadvantages of the different catalyst materials for SiNW growth are discussed at length. Furthermore, three thermodynamic aspects of SiNW growth via the vapor–liquid–solid mechanism are presented and discussed.

Growth of silicon nanowires by sputtering and evaporation methods

Silicon nanowires (Si NWs) were fabricated on Si (111) surfaces using both magnetron sputtering and thermal evaporation methods. Au thin layers were deposited using the electron-beam (e-beam) evaporation method and used as metal catalysts. The Au particles were formed by annealing at high temperature; their dimensions depended on the Au layer thickness and affected the formation and dimension of Si NWs. Field emission scanning electron microscopy (FESEM) was used to characterize the Si NWs. Photoluminescence (PL) measurement was conducted to demonstrate the quantum confinement effect of the Si NWs.

Radial heteroemitter solar cells based on VLS grown silicon nanowires

AbstractSilicon nanowires (SiNWs) are an interesting system for the realization of solar cells, as they offer an enhanced light absorption compared to bulk Si. However, due to their large surface, nanowire solar cells suffer from high surface recombination which results in small carrier lifetimes. They therefore need perfect passivation. The use of an amorphous silicon heteroemitter on such structures enables a good surface passivation and therefore enables a higher open circuit voltage (VOC) than in crystalline core–shell structures. In this paper, we present the realization of radial junction SiNW solar cells by the vapor–liquid–solid (VLS) growth of n‐doped SiNWs and subsequent coating by amorphous silicon in a PECVD process. The cells were contacted using atomic layer deposition of a transparent conductive oxide (aluminum‐doped zinc oxide) as a front contact. The results of the SiNW solar cells are compared to a planar device to exclude the influence of the supporting wafer structure. The onset presented in this paper can possibly be used to realize SiNW based solar cells on low cost materials, as VLS enables the growth of SiNWs on almost any kind of surfaces.

Ultradense and planarized antireflective vertical silicon nanowire array using a bottom-up technique

The production and characterization of ultradense, planarized, and organized silicon nanowire arrays with good crystalline and optical properties are reported. First, alumina templates are used to grow silicon nanowires whose height, diameter, and density are easily controlled by adjusting the structural parameters of the template. Then, post-processing using standard microelectronic techniques enables the production of high-density silicon nanowire matrices featuring a remarkably flat overall surface. Different geometries are then possible for various applications. Structural analysis using synchrotron X-ray diffraction reveals the good crystallinity of the nanowires and their long-range periodicity resulting from their high-density organization. Transmission electron microscopy also shows that the nanowires can grow on nonpreferential substrate, enabling the use of this technique with universal substrates. The good geometry control of the array also results in a strong optical absorption which is interesting for their use in nanowire-based optical sensors or similar devices.

Growth of crystalline silicon nanowires on nickel-coated silicon wafer beneath sputtered amorphous carbon

Growth of crystalline silicon nanowire of controllable diameter directly from Si wafer opens up another avenue for its application in solar cells and optical sensing. Crystalline Si nanowire can be directly grown from Si wafer upon rapid thermal annealing in the presence of the catalyst such as nickel (Ni). However, the accompanying oxidation immediately changes the crystalline Si nanowire to amorphous SiOx. In this study, amorphous carbon layer was sputtered to on top of the catalyst Ni layer to retard the oxidation. Scanning electron microscope, transmission electron microscope, Raman spectroscopy and X-ray photoelectron spectroscopy were employed to characterize the wires and oxidation process. A model was developed to explain the growth and oxidation process of the crystalline Si nanowire.

Characterization of silicon nanowires grown on silicon, stainless steel and indium tin oxide substrates

Silicon nanowires (SiNWs) have been grown on crystalline silicon (Si), indium tin oxide (ITO) and stainless steel (SS) substrates using a gold catalyst coating with a thickness of 200 nm via pulsed plasma-enhanced chemical vapor deposition (PPECVD). Their morphological, mineralogical and surface characteristics have been investigated using scanning electron microscopy (SEM), X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS) and Raman analysis. SiNWs growth is accompanied by oxidation, thus yielding partially (SiO x ) and fully oxidized (SiO2) Si sheaths. The mean diameters of these SiNWs range from 140 to 185 nm. Si with (111) and (220) planes exists in SiNWs grown on all three substrates while Si with a (311) plane is detected only for Si and ITO substrates. Computational simulation using density functional theory (DFT) has also been conducted to supplement the experimental Raman analyses for crystalline Si and SiO2. XPS results reveal that ca. 30 % of the SiNWs have been oxidized for all substrates. The results presented in this paper can be used to aid selection of appropriate substrates for SiNW growth, depending on specific applications.

Improved control of silicon nanowire growth by the vapor–liquid–solid method using a diffusion barrier layer between catalyst and substrate

Vapor–liquid–solid (VLS)-grown nanowires are promising building blocks for next-generation devices because of their unique characteristics. Although Au is a widely used catalyst with the largest operable parameter window for Si nanowire growth by the VLS method, Au catalyst droplets diffuse at a high migration velocity over a Si substrate surface and agglomerate at relatively low temperature, thus degrading the uniformity of Au catalyst droplets and Si nanowires. Our aim is to improve the controllability of nanowire growth, positioning, and diameter, which are essential attributes for practical applications. To accomplish this, a diffusion barrier layer was inserted between the catalyst and substrate. Length and diameter uniformity were considerably improved for nanowires grown together with the formation of a silicide layer as a diffusion barrier.