In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> ) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> and GPs. With the same gate space, the short <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance.