Abstract
Electrostatic Discharge (ESD) failure mechanisms of 18V grounded gate NMOS (GGNMOS) for liquid crystal display driver IC (LDI) applications are investigated and effects of layout design parameters on the ESD immunity level are analyzed. Experimental results show that 18V GGNMOS exhibits snapback characteristics and the ESD immunity level is rather high when XO (N-drift overlap over n+ source/drain) is sufficiently large, while GGNMOS does not exhibit the sustaining region and is very vulnerable to ESD stress when XO is relatively small. Simulation results show that the ESD failure mechanism of 18V GGNMOS could be the low-temperature second breakdown induced by the Kirk effect. It is inferred that a certain amount of XO is indispensable to ensure snapback characteristics and high ESD immunity level. Simulation results also show that the ESD immunity level is increased as drain contact to gate space (DCGS) is increased.
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