Graphics Processing Unit Platform Research Articles

HD-TMA: A New Fast Template Matching Algorithm Implementation for Linear DAS Array Data and Its Optimization Strategies

Abstract Distributed acoustic sensing (DAS) technology, combined with existing telecom fiber-optic cable, has shown great potential in earthquake monitoring. The template matching algorithm (TMA) shows good detection capabilities but depends on heavy computational cost and diverse template events. We developed a program named HD-TMA (high-efficiency DAS template matching algorithm), which accelerates computation by 40 times on the central processing unit platform and 2 times on the graphic processing unit platform. For linear DAS array data, we introduced a fast arrival-picking algorithm based on the Hough transform to pick the time window of template waveform. The HD-TMA was successfully applied to the 2022 Ms 6.9 Menyuan earthquake aftershock sequence recorded by a DAS array, and the DAS data result was compared with a collocated short-period seismometer data’s result. Two optimization strategies were discussed based on this data set. (1) Using signal-to-noise ratio in choosing the location and aperture of the subarray and the time window of the template waveform. (2) Considering the decrease in template events’ marginal utility, we proposed applying a neural network to build a template event library, followed by the HD-TMA scanning. Such strategies can effectively reduce computational cost and improve detection capability.

Hybrid CPU-GPU solution to regularized divergence-free curl-curl equations for electromagnetic inversion problems

The Curl-Curl equation is the foundation of time-harmonic electromagnetic (EM) problems in geophysics. The efficiency of its solution is key to EM simulations, accounting for over 95% of the computation cost in geophysical inversions for magnetotelluric or controlled-source EM problems. However, most published EM inversion codes are still central processing unit (CPU)-based and cannot utilize recent computational developments on the graphic processing units (GPUs). Based on a previously proposed divergence-free algorithm developed on CPUs, this study demonstrates the current limits of the CPU-based inversion procedure. To exploit the high throughput capability of GPUs, we propose a hybrid CPU-GPU framework to solve forward and adjoint problems required for EM inversions. The large sparse linear systems arising from the staggered-grid finite difference approximation of the Curl-Curl equation are solved with a mixed-precision Krylov subspace solver implemented on a GPU. The algorithm is then tested in EM forward and adjoint calculations, with real-world three-dimensional numerical examples. Test results show promising 30× kernel-level speed-ups over the conventional CPU algorithm. This approach may further take the complex frequency domain EM inversions onto the next, practical stage on small affordable GPU platforms.

CUDA-Optimized GPU Acceleration of 3GPP 3D Channel Model Simulations for 5G Network Planning

The simulation of massive multiple-input multiple-output (MIMO) channel models is becoming increasingly important for testing and validation of fifth-generation new radio (5G NR) wireless networks and beyond. However, simulation performance tends to be limited when modeling a large number of antenna elements combined with a complex and realistic representation of propagation conditions. In this paper, we propose an efficient implementation of a 3rd Generation Partnership Project (3GPP) three-dimensional (3D) channel model, specifically designed for graphics processing unit (GPU) platforms, with the goal of minimizing the computational time required for channel simulation. The channel model is highly parameterized to encompass a wide range of configurations required for real-world optimized 5G NR network deployments. We use several compute unified device architecture (CUDA)-based optimization techniques to exploit the parallelism and memory hierarchy of the GPU. Experimental data show that the developed system achieves an overall speedup of about 240× compared to the original C++ model executed on an Intel processor. Compared to a design previously accelerated on a datacenter-class field programmable gate array (FPGA), the GPU design has a 33.3% higher single-precision performance but a 7.5% higher power consumption. The proposed GPU accelerator can provide fast and accurate channel simulations for 5G NR network planning and optimization.

Mass transfer of the multicomponent free jet and one numerical implementation on a graphic processing unit platform

Jet flows are ubiquitous in nature and laboratories. For example, helium and argon jets into ambient air are commonly used to produce atmospheric plasma jets. The jets before and after discharge both are typical multicomponent flows. This study reports on the implementation of a numerical solver based on the graphic processing units to model multicomponent mixture gas flows. To this end, two- and three-dimensional Jacobian matrices for the multicomponent Euler equations were obtained to reconstruct numerical fluxes and build a total variation diminishing scheme. The two-dimensional early-stage mass transfer of gas jets was studied for three mixture gases: He/air, Ar/air, and N2/air to numerically verify the steady functioning of the numerical solver despite the high mass fraction gradients. The mass fraction distribution of helium in ambient air exhibited more complex substructures than those of argon and nitrogen in ambient air. Using the watershed method, self-generated bullets were extracted from the mass fraction distributions of the helium jet. The proposed numerical solver implemented in this study is expected to provide a better understanding of gas jet dynamics, and the Jacobian matrices can provide a mathematical foundation for constructing potential higher schemes.

SCM: A Searched Convolutional Metaformer for SAR Ship Classification

Ship classification technology using synthetic aperture radar (SAR) has become a research hotspot. Many deep-learning-based methods have been proposed with handcrafted models or using transplanted computer vision networks. However, most of these methods are designed for graphics processing unit (GPU) platforms, leading to limited scope for application. This paper proposes a novel mini-size searched convolutional Metaformer (SCM) for classifying SAR ships. Firstly, a network architecture searching (NAS) algorithm with progressive data augmentation is proposed to find an efficient baseline convolutional network. Then, a transformer classifier is employed to improve the spatial awareness capability. Moreover, a ConvFormer cell is proposed by filling the searched normal convolutional cell into a Metaformer block. This novel cell architecture further improves the feature-extracting capability. Experimental results obtained show that the proposed SCM provides the best accuracy with only 0.46×106 weights, achieving a good trade-off between performance and model size.

A Hybrid GPU and CPU Parallel Computing Method to Accelerate Millimeter-Wave Imaging

The range migration algorithm (RMA) based on Fourier transformation is widely applied in millimeter-wave (MMW) close-range imaging because of its few operations and small approximation. However, its interpolation stage is not effective due to the involved intensive logic controls, which limits the speed performance in a graphics processing unit (GPU) platform. Therefore, in this paper, we present an acceleration optimization method based on the hybrid GPU and central processing unit (CPU) parallel computation for implementing the RMA. The proposed method exploits the strong logic-control capability of the CPU to assist the GPU in processing the logic controls of the interpolation stage. The common positions of wavenumber-domain components to be interpolated are calculated by the CPU and stored in the constant memory for broadcast at any time. This avoids the repetitive computation consumed in a GPU-only scheme. Then the GPU is responsible for the remaining matrix-related steps and outputs the needed wavenumber-domain values. The imaging experiments verify the acceleration efficiency of the proposed method and demonstrate that the speedup ratio of our proposed method is more than 15 times of that by the CPU-only method, and more than 2 times of that by the GPU-only method.

Real time malware detection in encrypted network traffic using machine learning with time based features

With the increasing amount of Internet users, malware attacks are also growing. The purpose of malicious authors creating malware is to attack, damage, or impair electronic devices. In recent times, malware authors are also using HTTPs traffic; therefore, detecting malware in HTTPs traffic is intriguing since network traffic is enciphered. As the network traffic is enciphered, it is an arduous job to identify benign and malicious traffic. It also poses a significant challenge for firewalls and anti-malware software. Hence, it is essential to monitor the network traffic for detecting malware and threats in this way that maintains the encryption integrity. In this paper, a machine learning based model was proposed, which can effectively and efficiently detect malware without deciphering the network traffic. The prime objective of the research work is to apply several of ML techniques to detect malware in real-time utilizing time-based features. The proposed methodology can classify malware attacks in less than one second, achieving an accuracy of 99% on the Central Processing Unit (CPU) and Graphics Processing Unit (GPU) platform, which is sufficient for detecting malware in real-time.

Hybrid Compression Optimization Based Rapid Detection Method for Non-Coal Conveying Foreign Objects.

The existence of conveyor foreign objects poses a serious threat to the service life of conveyor belts, which will cause abnormal damage or even tearing, so fast and effective detection of conveyor foreign objects is of great significance to ensure the safe and efficient operation of belt conveyors. Considering the need for the foreign object detection algorithm to operate in edge computing devices, this paper proposes a hybrid compression method that integrates network sparse, structured pruning, and knowledge distillation to compress the network parameters and calculations. Combined with a Yolov5 network for practice, three structured pruning strategies are specifically proposed, all of which are proven to have achieved a good compression effect. The experiment results show that under the pruning rate of 0.9, the proposed three pruning strategies can achieve more than 95% compression for network parameters, more than 90% compression for the computation, and more than 90% compression for the size of the network model, and the optimized network is able to accelerate inference on both Central Processing Unit (CPU) and Graphic Processing Unit (GPU) hardware platforms, with a maximum speedup of 70.3% on the GPU platform and 157.5% on the CPU platform, providing an excellent real-time performance but also causing a large accuracy loss. In contrast, the proposed method balances better real-time performance and detection accuracy (>88.2%) when the pruning rate is at 0.6~0.9. Further, to avoid the influence of motion blur, a method of introducing prior knowledge is proposed to improve the resistance of the network, thus strongly ensuring the detection effect. All the technical solutions proposed are of great significance in promoting the intelligent development of coal mine equipment, ensuring the safe and efficient operation of belt conveyors, and promoting sustainable development.

Matrix-matrix multiplication on graphics processing unit platform using tiling technique

Today’s hardware platforms have parallel processing capabilities and many parallel programming models have been developed. It is necessary to research an efficient implementation of compute-intensive applications using available platforms. Dense matrix-matrix multiplication is an important kernel that is used in many applications, while it is computationally intensive, especially for large matrix sizes. To improve the performance of this kernel, we implement it on the graphics processing unit (GPU) platform using the tiling technique with different tile sizes. Our experimental results show the tiling approach improves speed by 56.89% (2.32× faster) against straightforward (STF). And tile size of 32 has the highest speed compared to other tile sizes of 8 and 16.

EC-ECC: Accelerating Elliptic Curve Cryptography for Edge Computing on Embedded GPU TX2

Driven by artificial intelligence and computer vision industries, Graphics Processing Units (GPUs) are now rapidly achieving extraordinary computing power. In particular, the NVIDIA Tegra K1/X1/X2 embedded GPU platforms, which are also treated as edge computing devices, are now widely used in embedded environments such as mobile phones, game consoles, and vehicle-mounted systems to support high-dimension display, auto-pilot, and so on. Meanwhile, with the rise of the Internet of Things (IoT), the demand for cryptographic operations for secure communications and authentications between edge computing nodes and IoT devices is also expanding. In this contribution, instead of the conventional implementations based on FPGA, ASIC, and ARM CPUs, we provide an alternative solution for cryptographic implementation on embedded GPU devices. Targeting the new cipher suite added in TLS 1.3, we implement Edwards25519/448 and Curve25519/448 on an edge computing platform, embedded GPU NVIDIA Tegra X2, where various performance optimizations are customized for the target platform, including a novel parallel method for the register-limited embedded GPUs. With about 15 W of power consumption, it can provide 210k/31k ops/s of Curve25519/448 scalar multiplication, 834k/123k ops/s of fixed-point Edwards25519/448 scalar multiplication, and 150k/22k ops/s of unknown-point one, which are respectively the primitives and main workloads of key agreement, signature generation, and verification of the TLS 1.3 protocol. Our implementations achieve 8 to 26 times speedup of OpenSSL running in the very powerful ARM CPU of the same platform and outperform the state-of-the-art implementations in FPGA by a wide margin with better power efficiency.

Ship Collision Avoidance and Anti Grounding Using Parallelized Cost Evaluation in Probabilistic Scenario-Based Model Predictive Control

The ability to effectively process large amounts of information in reasonable time will be important for robust deliberative collision avoidance (COLAV) planning algorithms. Failure to do so can lead to collision, and can be compared to lack of proper supervision from officers on watch (OOW). The main contribution in this article is a parallelized implementation of the Probabilistic Scenario-Based Model Predictive Control (PSB-MPC) on a Graphical Processing Unit (GPU) platform which incorporates both dynamic obstacle avoidance and anti-grounding. Simulation results demonstrate that the COLAV planner can produce collision-free trajectories with respect to grounding hazards and nearby vessels at relatively low computational cost, and which also comply to the COLREGS when deemed possible. Corresponding run-time results show that the algorithm utilizing parallel processing performs better than the alternative for increasing numbers of own-ship control behaviours, nearby static and dynamic obstacles, and dynamic obstacle prediction scenarios considered.

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM). Channel emulation is used for functional and performance verification of such models in the network planning phase. These models use multiple finite impulse response (FIR) filters and have a very high degree of parallelism which can be exploited for accelerated execution on Field Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) platforms. This paper proposes an efficient re-configurable implementation of the 3rd generation partnership project (3GPP) 3D-SCM on FPGAs using a design flow based on high-level synthesis (HLS). It studies the effect of various HLS optimization techniques on the total latency and hardware resource utilization on Xilinx Alveo U280 and Intel Arria 10GX 1150 high-performance FPGAs, using in both cases the commercial HLS tools of the producer. The channel model accuracy is preserved using double precision floating point arithmetic. This work analyzes in detail the effort to target the FPGA platforms using HLS tools, both in terms of common parallelization effort (shared by both FPGAs), and in terms of platform-specific effort, different for Xilinx and Intel FPGAs. Compared to the baseline general-purpose central processing unit (CPU) implementation, the achieved speedups are 65X and 95X using the Xilinx UltraScale+ and Intel Arria FPGA platform respectively, when using a Double Data Rate (DDR) memory interface. The FPGA-based designs also achieved ~3X better performance compared to a similar technology node NVIDIA GeForce GTX 1070 GPU, while consuming ~4X less energy. The FPGA implementation speedup improves up to 173X over the CPU baseline when using the Xilinx UltraRAM (URAM) and High-Bandwidth Memory (HBM) resources, also achieving 6X lower latency and 12X lower energy consumption than the GPU implementation.

In-Memory Realization of Eligibility Traces Based on Conductance Drift of Phase Change Memory for Energy-Efficient Reinforcement Learning.

Reinforcement learning (RL) has shown outstanding performance in handling complex tasks in recent years. Eligibility trace (ET), a fundamental and important mechanism in reinforcement learning, records critical states with attenuation and guides the update of policy, which plays a crucial role in accelerating the convergence of RL training. However, ET implementation on conventional digital computing hardware is energy hungry and restricted by the memory wall due to massive calculation of exponential decay functions. Here, in-memory realization of ET for energy-efficient reinforcement learning with outstanding performance in discrete- and continuous-state RL tasks is demonstrated. For the first time, the inherent conductance drift of phase change memory is exploited as physical decay function to realize in-memory eligibility trace, demonstrating excellent performance during RL training in various tasks. The spontaneous in-memory decay computing and storage of policy in the same phase change memory give rise to significantly enhanced energy efficiency compared with traditional graphics processing unit platforms. This work therefore provides a holistic energy and hardware efficient method for both training and inference of reinforcement learning.

A GPU-Accelerated Radiation Transfer Model Using the Lattice Boltzmann Method

A prototype of a three-dimensional (3-D) radiation model is developed using the lattice Boltzmann method (LBM) and implemented on a graphical processing unit (GPU) to accelerate the model’s computational speed. This radiative transfer-lattice Boltzmann model (RT-LBM) results from a discretization of the radiative transfer equation in time, space, and solid angle. The collision and streaming computation algorithm, widely used in LBM for fluid flow modeling, is applied to speed up the RT-LBM computation on the GPU platform. The isotropic scattering is assumed in this study. The accuracy is evaluated using Monte Carlo method (MCM) simulations, showing RT-LBM is quite accurate when typical atmospheric coefficients of scattering and absorption are used. RT-LBM runs about 10 times faster than the MCM in a same CPU. When implemented on a NVidia Tesla V100 GPU in simulation with a large number of computation grid points, for example, RT-LBM runs ~120 times faster than running on a single CPU. The test results indicate RT-LBM is an accurate and fast model and is viable for simulating radiative transfer in the atmosphere with ranges for the isotropic atmosphere radiative parameters of albedo scattering (0.1~0.9) and optical depth (0.1~12).

Multi GPU parallelization of maximum likelihood expectation maximization method for digital rock tomography data

Digital rock is an emerging area of rock physics, which involves scanning reservoir rocks using X-ray micro computed tomography (XCT) scanners and using it for various petrophysical computations and evaluations. The acquired micro CT projections are used to reconstruct the X-ray attenuation maps of the rock. The image reconstruction problem can be solved by utilization of analytical (such as Feldkamp–Davis–Kress (FDK) algorithm) or iterative methods. Analytical schemes are typically computationally more efficient and hence preferred for large datasets such as digital rocks. Iterative schemes like maximum likelihood expectation maximization (MLEM) are known to generate accurate image representation over analytical scheme in limited data (and/or noisy) situations, however iterative schemes are computationally expensive. In this work, we have parallelized the forward and inverse operators used in the MLEM algorithm on multiple graphics processing units (multi-GPU) platforms. The multi-GPU implementation involves dividing the rock volumes and detector geometry into smaller modules (along with overlap regions). Each of the module was passed onto different GPU to enable computation of forward and inverse operations. We observed an acceleration of sim 30 times using our multi-GPU approach compared to the multi-core CPU implementation. Further multi-GPU based MLEM obtained superior reconstruction compared to traditional FDK algorithm.

An Improved Back-Projection Algorithm for GNSS-R BSAR Imaging Based on CPU and GPU Platform

Global Navigation Satellite System Reflectometry Bistatic Synthetic Aperture Radar (GNSS-R BSAR) is becoming more and more important in remote sensing because of its low power, low mass, low cost, and real-time global coverage capability. The Back Projection Algorithm (BPA) was usually selected as the GNSS-R BSAR imaging algorithm because it can process echo signals of complex geometric configurations. However, the huge computational cost is a challenge for its application in GNSS-R BSAR. Graphics Processing Units (GPU) provides an efficient computing platform for GNSS-R BSAR processing. In this paper, a solution accelerating the BPA of GNSS-R BSAR using GPU is proposed to improve imaging efficiency, and a matching pre-processing program was proposed to synchronize direct and echo signals to improve imaging quality. To process hundreds of gigabytes of data collected by a long-time synthetic aperture in fixed station mode, a stream processing structure was used to process such a large amount of data to solve the problem of limited GPU memory. In the improvement of the imaging efficiency, the imaging task is divided into pre-processing and BPA, which are performed in the Central Processing Unit (CPU) and GPU, respectively, and a pixel-oriented parallel processing method in back projection is adopted to avoid memory access conflicts caused by excessive data volume. The improved BPA with the long synthetic aperture time is verified through the simulation of and experimenting on the GPS-L5 signal. The results show that the proposed accelerating solution is capable of taking approximately 128.04 s, which is 156 times lower than pure CPU framework for producing a size of 600 m × 600 m image with 1800 s synthetic aperture time; in addition, the same imaging quality with the existing processing solution can be retained.

Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method

An extensive survey of the literature shows that the Lanczos eigensolver is a popular iterative method for approximating a few maximal eigenvalues of a real symmetric matrix, particularly if the matrix is large and sparse. In recent years, graphics processing units (GPUs) have become a popular platform for scientific computing applications, many of which are based on linear algebra, and are increasingly being used as the main computational units in supercomputers. This trend is expected to continue as the number of computations required by scientific applications reach petascale and exascale range. In this paper, building on our earlier work [22], we investigate in detail the error checking mechanism for the Lanczos eigensolver. We identify a low cost invariant for efficient error checking, and through mathematical analysis determine the efficiency of our mechanism when used by the Lanczos eigensolver. We evaluate the proposed fault tolerant scheme using an open-source sparse eigensolver on a GPU platform, with and without the injection of faults. We use a large number of sparse matrices from real applications, to determine the efficiency and efficacy of our method and our implementation shows that the proposed fault tolerant method has good error coverage and low overhead. To the best of our knowledge, we are the first to introduce such a scheme for the Lanczos method.

100 Mbps Reconciliation for Quantum Key Distribution Using a Single Graphics Processing Unit

An efficient error reconciliation scheme is important for post-processing of quantum key distribution (QKD). This paper concerns the improvement of reconciliation performance. Recently, a multi-matrix low-density parity-check code-based reconciliation algorithm which can provide remarkable perspectives for high-efficiency information reconciliation was proposed by Gao (Opt Express 27:14545–14566, 2019). The multi-matrix algorithm is implemented and optimized on the graphics processing unit (GPU) to obtain high reconciliation throughput. Experimental results indicate that the GPU-based algorithm can highly improve reconciliation throughput to an average of 85.67 Mbps and a maximum 102.084 Mbps with typical code rate and efficiency. This is the best performance of reconciliation on GPU platform to our knowledge.

Microwave Correlation Forward-Looking Super-Resolution Imaging Based on Compressed Sensing

Forward-looking correlated imaging plays an increasingly important role in modern radar imaging systems. It overcomes disadvantages of traditional side or squint synthetic aperture radar (SAR) which is dependent on specific relative motion between the radar and target scene. A new microwave forward-looking correlated 3-D imaging method based on random radiation field combined with sparse reconstruction is proposed in this article. Firstly, phased array radar (PAR) is adopted to form different and random antenna patterns. Then, combined with the compressed sensing (CS) theory, the target image can be recovered with very few samples which can break through Rayleigh resolution limitation. Furthermore, the proposed method can achieve resolution at least 5.5 times higher than real aperture imaging. To raise computation efficiency of sparse reconstruction, an improved quasi-Newton iteration method based on graphics processing unit (GPU) platform is developed. Meanwhile, a GPU-based (NVIDIA Tesla K40c) accelerated computing method can significantly reduce the processing time compared with the time given by a personal computer (PC). Both simulation and field experiment verify the validity of the proposed method.

Powers of Large Matrices on GPU Platforms to Compute the Roman Domination Number of Cylindrical Graphs

The Roman domination in a graph $G$ is a variant of the classical domination, defined by means of a so-called Roman domination function $f\colon V(G)\to \{0,1,2\}$ such that if $f(v)=0$ then, the vertex $v$ is adjacent to at least one vertex $w$ with $f(w)=2$ . The weight $f(G)$ of a Roman dominating function of $G$ is the sum of the weights of all vertices of $G$ , that is, $f(G)=\sum _{u\in V(G)}f(u)$ . The Roman domination number $\gamma _{R}(G)$ is the minimum weight of a Roman dominating function of $G$ . In this paper we propose algorithms to compute this parameter involving the $(\min,+)$ powers of large matrices with high computational requirements and the GPU (Graphics Processing Unit) allows us to accelerate such operations. Specific routines have been developed to efficiently compute the $(\min,+)$ product on GPU architecture, taking advantage of its computational power. These algorithms allow us to compute the Roman domination number of cylindrical graphs $P_{m}\Box ~C_{n}$ i.e., the Cartesian product of a path and a cycle, in cases $m=7,8$ ,9 $n\geq 3$ and $m\geq $ 10 $, n\equiv 0\pmod 5$ . Moreover, we provide a lower bound for the remaining cases $m\geq $ 10 $, n\not \equiv 0\pmod 5$ .