Graphene Logic Research Articles

Selective nano-buckling improves the performance of graphene logic transistors.

Selective nano-buckling improves the performance of graphene logic transistors.

Design and simulation of graphene logic gates using graphene p–n junctions as building blocks

Design and simulation of graphene logic gates using graphene p–n junctions as building blocks

Demonstration of programmable ternary graphene field-effect transistor using ferroelectric polymer doping

Ternary logic technology facilitates simplifying logic circuits and reducing power consumption. In this study, a universal ternary device that can be programmed into an n-type and p-type ternary device is demonstrated using a graphene field-effect transistor with a P(VDF-TrFE)/graphene stack channel. The feasibility of a standard ternary inverter function is demonstrated by complementary ternary GFETs, which have discretely programmed n-doped and p-doped graphene channels with different channel widths. Even though the performance of the ternary inverter should be improved further, the concept of the programmable ternary logic, based on channel width modulation and ferroelectric doping, is useful for future experimental studies on the multi-valued logic architecture. • Complementary ternary graphene field-effect transistors using ferroelectric polymer doping effects were demonstrated. • Modulation of the channel widths of series-connected GFETs has been demonstrated. • Semi-empirical graphene logic device model confirms complementary ternary logic system viability.

XNOR/XOR graphene logic gate based on plasma disperison effect

In this paper, a novel XNOR/XOR logic gate with the double-layer graphene embedded in micro-ring waveguide based on plasma disperison effect is proposed. By changing the voltage loaded on the graphene, the light absorption capacity of graphene is affected, changing the resonant state of the micro-ring resonator, and the logic operation function of XNOR/XOR is achieved simultaneously in two output ports. When the working wavelength is 1.551 μm and the chemical potential of graphene is 0.45eV or 0.50eV, the light intensity of the two output ports is simulated and calculated by MATLAB and COMSOL software. The simulation results reveal that under the four logical operands of ‘00′, ‘01′, ‘10′, ‘11′, the novel U-shaped micro-ring waveguide structure with double-layer graphene as the modulation region can perform the logic operation of XNOR/XOR at high speed. In addition, compared with the existing micro-ring logic gates, the proposed structure can not only greatly enhance the extinction ratio and 3 dB bandwidth of the logic gate, but also reduce the modulation voltage, insertion loss and crosstalk.

Lanthanide complexes as molecular dopants for realizing air-stable n-type graphene logic inverters with symmetric transconductance

In this communication we have unveiled the importance of lanthanide dopant, to realize n-doping of GFETs with an exceptional ambient stability and enhanced mobility. An unconventional mechanism proposed for such phenomenon is well supported by various analytical methods and rationalized by computational calculations.

Graphene Logic Gates

Graphene is a biocompatible material that can be incorporated safely into living tissue. This property makes graphene an ideal material for bioelectronics applications. The main obstacle for using graphene as a material for bioelectronic circuits is the lack of a bandgap, which results in noneffective current switching. Here, we use rectangular L-shaped graphene nanoribbons as a building block for graphene logic gates. Electrons are initially transported along the zigzag-edged nanoribbon and then the transport direction changes by 90°, resulting in transport along the armchair edge. Our computations showed that electron scattering because of this change in the direction causes the appearance of a pseudobandgap, which is large enough for logic operations. This pseudobandgap appears as a zero-conductance region for electron energies near the Fermi level. We propose an and , an or, and a not logic gate and use tight-binding Hamiltonians and nonequilibrium Greens functions to show that these designs can reproduce effectively the desired logic operations.

Modeling of Physical Defects in PN Junction Based Graphene Devices

Graphene's exceptional electro-mechanical properties make it a strong contender to replace silicon-based Complementary Metal-Oxide Semiconductor (CMOS) devices in the future. Among other novel material-based devices, graphene is pushing the research community to find new technological solutions that exploit its special characteristics. As it is a semimetal, the key challenge for graphene-based devices to be used in digital circuits is introducing band gap. Among the proposed approaches, electrostatic doping represents a key option. It allows the implementation of graphene pn junctions through which building a new class of reconfigurable logic gates is possible. This devices are analyzed in this work. Recent works presented a quantitative analysis of such gates in terms of area, delay and power consumptions, confirming their superiority w.r.t. CMOS technologies below the 22 nm. This paper explores another dimension, that is testability, and proposes a study of possible physical defects that might alter the functionality of the graphene logic gates. Two major kinds of manufacturing defects, which are possible in these gates, namely the S h o r t s between the device's terminals and O p e n terminals, are considered. These faults have been injected into non faulty devices at the SPICE-level and the resulting behavior is mapped to appropriate fault model. Most of such models belong to the CMOS domain, but for some specific class of defects, new fault definitions are needed.

CVD-Graphene Complementary Logic on Ultra-thin Multilayer Hexagonal Boron Nitride

ABSTRACTGraphene, a two-dimensional carbon allotrope, has raised great interests as a material candidate for future electronics due to its superb carrier transport and unique physics. The demand for future-generation large-scale carbon-based electronics motivates assembly of large-area graphene and selection of ideal substrate material that best preserves the transport property of graphene. In this work, CVD-assembled large-area graphene on thin multilayer hexagonal boron nitride (h-BN) is employed to demonstrate the basic building block of digital circuit - inverter prototype made of two graphene-channel field-effect transistors (GFETs). The doping in the CVD-grown graphene, probed via electrical measurements, is implemented through non-uniform local surface chemistry. The full transfer response of the graphene logic inverter is demonstrated in the localized P/N doping region.

Complementary‐Like Graphene Logic Gates Controlled by Electrostatic Doping

A facile electrostatic modulation method is developed to control the charge neutrality points of ambipolar graphene transistors and to form a complementary-like structure for the fabrication of elementary logic gates. Graphene logic NOR and NAND gates are demonstrated, which are building pillars for logic computation. The result provides a possible route for graphene logic circuits.

Reconfigurable Graphene Logic Device Based on Tilted P-N Junctions

ABSTRACTIn this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the operation of the device, leading to reconfigurable multi-functional logic. A device model is derived from carrier transmission probability across the p-n junction for allowing quantitative comparison to CMOS logic. Based on this model, we show that the proposed graphene logic has significant advantages over CMOS gate in terms of area, delay, power, and signal restoration. Furthermore, the device utilizes a large graphene sheet with minimal patterning, allowing feasible integration with CMOS circuits, for potential CMOS-graphene hybrid circuits.

One graphene device makes three amplifiers

Graphene devices are showing amazing flexibility, and not just the mechanical kind. Researchers at Rice University and the University of California, Riverside, recently demonstrated an amplifier, based on a single graphene transistor, that can do the job of three different amplifiers. The device could lead to smaller, lower-power analog circuits, such as Bluetooth radios, they say. Separately, scientists at IBM are developing a type of graphene device that can be reconfigured, on the fly, into six different logic gates. Despite this, engineers agree that practical graphene logic is many years away.

Low Operating Bias and Matched Input−Output Characteristics in Graphene Logic Inverters

We developed a simple and novel method to fabricate complementary-like logic inverters based on ambipolar graphene field-effect transistors (FETs). We found that the top gate stacks (with both the metal and oxide layers) can be simply prepared with only one-step deposition process and show high capacitive efficiency. By employing such a top gate as the operating terminal, the operating bias can be lowered within 2 V. In addition, the complementary p- and n-type FET pairs can be also simply fulfilled through potential superposition effect from the drain bias. The inverters can be operated, with up to 4-7 voltage gains, in both the first and third quadrants due to the ambipolarity of graphene FETs. For the first time, a match between the input and output voltages is achieved in graphene logic devices, indicating the potential in direct cascading of multiple devices for future nanoelectronic applications.

Reconfigurable Graphene Logic

In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the operation of the device, leading to reconfigurable multi-functional logic. A device model is derived from carrier transmission probability across the p-n junction for allowing quantitative comparison to CMOS logic. Based on this model, we show that the proposed graphene logic has significant advantages over CMOS gate in terms of area, delay, power, and signal restoration. Furthermore, the device utilizes a large graphene sheet with minimal patterning, allowing facile integration with CMOS circuits, for potential CMOS-graphene hybrid circuits.